Device Scaling of High Performance MOSFET with Metal Gate High-K At

Device Scaling ofHigh Performance MOSFET with Metal Gate High-K at 32nm Technology Node and Beyond

Xinlin Wang, *Ghavam Shahidi, Phil Oldiges and Mukesh Khare IBM Semiconductor Research and Development Center Systems and Technology Group, Hopewell Junction, NY 12533, Research Division, ·IBM T.J. Watson Research Center

Abstract - In this work, two different methodologies are used to high-k dielectric and polysilicon gate oxide dielectric at a fixed quantitatively evaluate devices with metal high-k gate dielectrics total leakage current ofa chip. for their scaling benefits over conventional polysilicon gate devices. For each method, device characteristics and ring II. SIMULATION METHOODOLOGY oscillator delay calculations are performed. Our results show that aggressive channel length scaling continually provides transistor Drift diffusion simulations were performed on PDSOI performance gain with the use of metal gate high-k technology. A MOSFETs with either PG/OX or MG/HK gate stack as band edge work function for the metal gate offers potential showed in Fig. 1, and ring oscillator delays are calculated by benefits for device scaling over conventional polysilicon gates for FIELDAY [6] mixed-mode simulations. In this study, we high performance (UP) application at the 32nm CMOS focus on a band-edge metal gate which is required for higher technology node and beyond. performance applications [5]. NFET devices are simulated Keywords-device scaling, metal high-k gate, channel length with Lnom ranging from 23nm to 35nm, Tinv is 19A for PG/OX scaling, high performance CMOS and 14A or12A for MG/HK as listed in the table 1. In order to de-couple the performance adder between MG NFETs and I. INTRODUCTION PFETs, all ofthe PFETs used in the ring oscillator simulations are PG/OX devices with Tinv=20A. Two methodologies are Scaling the transistor gate length (Lgate), which is one of the used in our scaling study. (I) fixed drain induced barrier key parameters driving MOSFET scaling, has significant lowering (DIBL) scaling at a single channel length (one performance impact at the 32nm node and beyond [1,2]. point). In this method, we center the devices to satisfy the I Because the gate oxide cannot be further scaled down due to Off constraint at different nominal channel lengths and different large gate tunneling currents, channel length scaling without gate dielectric scaling beyond the 45nm node actually degrades inversion layer thicknesses. Then we study how Tinv scaling transistor drive current and performance. With a high-k enables channel length scaling for the fixed DIBL condition. material as gate dielectric, effective oxide thickness (EOT) can (II) Double-point methodology, in which we assume 30' Lgate be further scaled down without increasing gate tunneling variation in the process between L nom and L mim then we match leakage. Also, using metal as a gate electrode (MG), the I Off of the MGIHK devices to that of the PG/OX control polysilicon gate (PG) depletion effect is eliminated, which devices at both L nom and Lmin by adjusting the doping profile, allows designers to push the scaling limit through a reduction nominal channel length and Tinv ofthe MG/HK devices. of the inversion layer thickness (Tim') [3,4]. There are different ways to evaluate the electrostatic and performance advantage associated with metal gate high-k technology. In our previous study [5], the off-state leakage current (I~ff) is constrained to a fixed value for minimum channel length (Lmin) devices at Vdd= IV, then we compared metal gate high-k «MG/HK) devices to poly oxide gate (PG/OX) devices at nominal channel length (Lnom). However the sub-threshold leakage (Ioff) does not match to that of PG/OX control devices at Lnom• In this work, we evaluate EOT and Tinv scaling benefits quantitatively by two different methods: a single point methodology and double point methodology. For the single point methodology, we compared devices at nominal channel length with a fixed I Off target. For the double point methodology, devices are compared at both nominal and minimum channel length with the fixed I Off targets. Fig. 1 Simulated PDSOI structures with different gate and dielectrics. Gate: By using the double point method, for the first time we show a metal or polysilicon; dielectrics: oxide or high-K. fair performance comparison between devices with metal gate

309 TABLE!. CHANNEL LENGTH AND T~v FOR SIMULATED MOSFET. 1.E+04 Lnom (nm) Tinv (A) ---.- Lnom=23nm Polysilicon/oxide (PG) 35 19 ,~~ Lnom=27nm ~~ Metal/High-k (MG) 35,31,27,23 14 or 12 -a- Lnom=31 nm , ~ ~~om=35nm E 1.E+03 :::J III. SIMULATION RESULTS AND DISSCUSIONS C .5. \ ~,~... Short channel device properties ofMG NFETs are compared ::: " to 35nm PG NFETs. I Off is matched between MG and PG at .S! 1.E+02 ~ Lnom for Figs 1-6.

0.40 -+- Lnom=23nm 1.E+01 ...... - Lnom=27nm 15 25 35 --.- Lnom=31 nm 45 0.30 -+-- Lnom=35nm Lgate (um) ..--. >...... Fig. 4 10ff vs. Lgate at different L"a",' Open symbol lines: PG (Tim,=19A), solid symbol lines: MG (Tim' =14A). Compared to PG, there is little improvement ..ca 0.20 II) for MG on the lojf vs. Lgute curves when EOT is not scaled. Because at the IOff >.. condition (Vgs=O), there is little poly depletion at the gate electrode. So EOT has to be scaled down to improve 10ff vs. Lgo,e when the channel length is 0.10 scaled down.

In Figs. 2-4, T;nv =14A for MG and 1inv =19A for PG and 0.00 effective oxide thickness (EDT) is the same for both MG and 15 25 35 45 PG devices. During the channel length scaling without EaT scaling, ~ roll-off and DIBL become worse even though halo Lgate (nm) doses are increased to control Ioffat the target Lnom• And IOff of minimum channel length device keeps increasing due to worse Fig. 2 Threshold voltage (VJ vs. Lgo,e at different Lnom (Vds=l.OV). At each short channel effect (SeE) control at shorter channel length. nominal channel length, loff is matched. Open symbol lines: PG (Tim.=19A), From Figs. 2-3, we can see that at the same EDT, MG devices Solid symbol lines: MG (Tinv =14A). When nominal length is scaled down, Vt show better ~ roll-off and DIBL reduction compared to PG roll-off becomes worse. When MG and PG devices have the same EOT, MG devices provide better VI roll-off compared to that of the PG devices at the counterpart due to the removal ofthe potential drop in the poly same nominal channel length. gate electrode under the sub-threshold condition. However there is only small improvement in IOff vs. Lg for the MG over the PG when EaT is not scaled as shown in Fig. 4. 350 -+- Lnom=23nm >' 160 300 ----- Lnom=27nm .,~ MG, tinv=12A --.- Lnom=31 nm S -e-- Lnom=35nm c -.-MG, tinv=14A ~ °e 120 250 ~ -e-PG, tinv=19A ...... @ ..J \ ~ 200 >E 80 o c ~ 150 @ 40 l 100 w ~ -t------~ 15 25 35 45 0 Lgate (um) 20 25 30 35 40 Lnom (nm) Fig. 3 DIBL vs. Lgo,e at different Lnom (Vdrl.OV). Open symbol: PG; solid symbol: MG. When the nominal channel length is scaled down without EOT scaling, DIBL is degraded. Because there is different potential drop in the poly Fig. 5 SCE (= vt®Loom- Vt®Lmin) vs. Loom. Scaling channel length degrades SCE gate electrode at the sub-threshold conditions when Vds=50mV or Vdd, MG even though the halo doping concentration is increased to control IOff at Lnom . devices show 30-50mV DIBL reduction compared to PGs at different Lnom . The SCE degrades faster for the PG devices compared to the MG Devices at the DIBL benefit ofMG over PG becomes larger when the channel length is scaled Same EaT (compared MG 14A case to PG 19A case). SCE can be further down. improved by EOT scaling for MG devices (MG 12A case vs. MG 14A case).

8-1-2

310 260 1.E+04 ._-+- MG, tinv=12A ~ --..l- MG, tinv=14A 220 "~nV=19A 1.E+03 >" E E ~ :; 180 1.E+02 In 1 C ~ -+- PG, tinv=19A, LnorTF35nm 140 1.E+01 ....,,*...... PG, tinv=19A, LnorTF31nm ~ tv1G, tinv=14A, LnorTF33nm --{}- tv1G, tinv=12A, LnorTF31nm 100 1.E+00 20 25 30 35 40 25 30 35 40 Lnom (nm) Lgate (nm)

Fig. 8 loj! vs. L gate comparison between MG and PG NFETs. MG devices Fig. 6 DIBL comparison at different L nom• Removal of poly depletion in the gate electrode improves DIBL at the same channel length. lA EOT scaling for provide 2nm Lg scaling with Tjll\'= 14A and 4nm Lg scaling with Tim' = 12A for MG devices provides 3-4 nm channel length scaling for the fixed DIBL the same 10fftargets at both L nom and Lmin respectively to PG NFETs. For the condition. PG devices, simply increasing halo dose for the shorter Lg without EOT scaling degrades IOff vs. Lg curve due to degraded SCE. Fig. 5 shows that short channel effect (SeE) is degraded during the channel length scaling even though the halo dose increases 250 r------....., to meet IOff target at shorter Lgate• The PG device SCE degrades a",,- faster than that ofMG devices for shorter devices. Fig. 6 shows ,...,..•,~...... 200 the DIBL comparison at different L nom for scaled EaT (MG, Tinv =12A) and non-scaled EaT (MG, tinv=14A) cases >" compared to PG. For MG devices, lA EaT scaling provides ~ ..I 150 3--4 nm channel length scaling for the fixed DIBL condition; £II ~ and at the fixed L IA EaT scaling provides lOmV DIBL C nonn -+- PG, tinv=19A, Lnom=35nm improvement. AC performance is compared between PG and 100 _....-._. PG, tinv=19A, Lnom=31nm MG by running mix-mode ring oscillator simulation. Fig. 7 ~ MG, tinv=14A, Lnom=33nm shows that for the loaded ring oscillator, there is --13% -0- MG, tinv=12A, Lnom=31nm performance improvement by replacing a 35nm PG NFET 50 (linv=19A) with a 27nm band-edge MG/HK NFET (T;nv =12A); 25 30 35 40 and 2A EaT scaling of MG/HK yields 4% AC performance Lgate (nm) benefit. If we apply MG to the PFET, the performance gain over PG will be doubled. Fig. 9 DIBL vs. L gate comparison between MG and PG NFETs. MG (Tinv=12A) provides more than 50mV DIBL benefit over PG (T;nv =19A) at 30nm channel length. 1.00 ~ MG nfet, tinvn=12A 130 0.95 f:l MG nfet, tinvn=14A

0.90

0.85 -+- PG, tinv=19A, LnorTF35nm ~ PG, tinv=19A, LnotTF31nm ~ MG, tinv=14A, LnotTF33nm 0.80 -0- M3, tinv=12A, LnorTF31nm 70 23 27 31 35 25 30 35 40 Lnom (nm) Lgate (nm)

Fig. 7 Relative loaded ring oscillator delay for different L nom at fixed IOff condition. At Lnom=35nm, replace PG with MG for NFET will provide 8% Fig. 10 Sub-threshold swing vs. Lgote comparison between MG and PG NFETs. performance gain. Continually scaling channel length for MG devices will MG (1j,rv=12A) provides 15mV/dec sub-threshold swing (SS) benefit over PG reduce higher effective capacitance loading penalty due to smaller Tinv for (Tinv =19A) at 300m channel length. For MG, with EOT scaling, SS is not MG, so more performance benefit is obtained by Lg scaling down to 270m for degraded at both Lnom and Lmin• However, due to lack of EOT scaling for PG, MG. shrinking Lg degrades SS at both L nom and Lmin•

8-1-3

311 In Figs. 8-13, we used the double-point methodology to study the scaling benefit ofMG over PG devices. Fig. 8 shows 1.E+04 that scaling L nom ofPG device from 35nm to 31 without scaling T doubles I at L . However, the MG device can match 1 inv Off min 0ff 1.E+03 at both Lnom and L min respectively when the channel length is E scaled down due to Tinv and EaT scaling. In other words, the ~ perfonnance is improved, but the total sub-threshold leakage of l1.E+02 a whole chip does not increase during Lgate scaling for MG devices. Figs 9-11 are DIBL, sub-threshold swing and V, roll tt: off curves for MG and PG. We can see that MG exhibits oS! -+- FG, tinv=19A, Lnorn=35nm 1.E+01 '~~~A'" FG, tinv=19A, Lnorn=31nm superior SCE control over PG. There is a 370/0 drive current -I:r- fvI3, tinv=14A, Lnorn=33nm (Ion) improveinent for MG with T;nv =12A as shown in Fig. 12. -0- fvI3, tinv=12A, Lnorn=31nm However, EaT of PG can not be scaled down due to larger 1.E+OO gate leakage, so there is no current improved when Lgate continually scaled. 0.7 0.8 0.9 1 1.1 Relative loaded ring delay 0.25 Fig. 13 IOff VS. loaded ring oscillator delay. Replacing 35nm PG NFET (tinv=19A) with 31nm BEMGIHK NFET (tinv=12A), loaded ring delay is 0.20 improved 12% without degrading IOff. While channel length scaling on PG gate does not provide any performance gain. ~ 0.15 ..as IV. CONCLUSIONS 0.10 $ Two different methodologies are used in our simulations to --+- PG, tinv=19A, Lnom=35nm quantitatively evaluate the benefits of channel length scaling 0.05 ~ PG, tinv=19A, Lnom=31nm -&- MG, tinv=14A, Lnom=33nm together with Tinv and EOT scaling. Our results show that MG -0-- MG, tinv=12A, Lnom=31 nm devices with scaled Tinv and EaT exhibit electrostatic and 0.00 perfonnance advantages over PG devices. MG/HK also 25 30 35 40 provides additional channel length scaling without degrading Lgate (nm) the total 10ff of the chip for 32nm high perfonnance CMOS devices and beyond.

Fig. 11 VlSat VS. Lga,e comparison between MG and PG NFETs (VLfi= Vdd). There is Vt roll-off improvement during EOT scaling. ACKNOWLEDGMENT This \\'ork was performed by the Research Alliance Teams 1.E+04 at various IBl\1 Research and Development Facilities.

1.E+03 REFERENCE E [1] J. W. Sleight, I. Lauer, O. Dokumaci, D. M. Fried, D. Guo, B. Haran, S. ~ Narasimha, C. Sheraw, D. Singh, M. Steigerwalt, X. Wang, P. Oldiges, 1 E 02 ~ /;; 1 . + D. Sadana, C.Y. Sung, W. Haensch, and M. Khare, "Challenges and :t: Opportunities for High Performance 32 nm CMOS Technology", IEDM o -+- PG, tinv=19A, Lnorn=35nm Tech. Dig. 2006 - 1.E+01 ~ PG, tinv=19A, Lnorn=31nm [2] P. M. Zeitzoff, "Proceedings of the Custom Integrated Circuits -I:r- WG, tinv=14A, Lnorn=33nm Conference", 2004, p. 233-240. -o-WG, tinv=12A, Lnorn=31nm [3] Y. Abe, T. Oishi, K. Shiozawa, Y. tokuda, and S. Saton," Simulation 1.E+00 study on comparision between Metal gate and polysilicon gate for sub quarter-micron MOSFET's", IEEE Elec. Dev. Lett., vol. 20, No. 12, 0.5 1 1.5 2 p632-634. 1999. Ion (mAlum) [4] E. Gusev et al., "Advanced Gate Stacks with Fully Silicided (FUSI) Gates and High-K Dielectrics Enhanced Performance at Reduced Gate Fig. 12 IOff VS. lOll comparison between MG and PG NFETs. There is 24% and Leakage", IEDM Tech. Dig. 2004, p79-82. 37% Ion improvement for MG with Tilll·=14A, L =33nm and ~1l\,=12A L =3lnm g g [5] X. Wang, A. Bryant, P. Oldiges, S. Narasimha, R. Dennard and W. respectively. Haensch, "Simulation Study on Channel Length Scaling of High Fig. 13 shows that replacing a 35nm PG NFET (T;nv=19A) with Performance Partially Depleted Metal Gate and Poly Gate SOl a 31nm band-edge MG NFET (T;nv =12A), loaded ring delay is MOSFETs"SISPAD 2006, p283-286. improved 120/0 without degrading the total Ioffofthe chip. [6] E. M. Buturla, P. E. Cottrell, B. M. Grossman, and K. A. Salsburg, "Finite-element analysis of semiconductor device: the FIELDAY program," IBM J. Res. Develop., vol. 25, pp. 218,1981.

8-1-4

312