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Video and Image Processing Design Example Video and Image Processing Design Example Date: September, 2016 Revision: 1.0 ©2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and serv ices at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the la test version of device specifications before relying on any published information and before placing orders for products or services. TABLE OF CONTENTS INTRODUCTION .............................................................................................................................................................. 3 1 INSTALLING THE EXAMPLE DESIGN ............................................................................................................ 6 2 SYSTEM REQUIREMENT ..................................................................................................................................... 8 2.1 HARDWARE REQUIREMENTS ................................................................................................................................ 8 2.2 SOFTWARE REQUIREMENTS ................................................................................................................................. 8 3 DESIGN EXAMPLE OVERVIEW......................................................................................................................... 9 3.1 QSYS .................................................................................................................................................................... 10 3.2 QUARTUS II SOFTWARE ...................................................................................................................................... 11 3.3 NIOS II SOFTWARE BUILD TOOLS FOR ELIPSE................................................................................................... 11 3.4 SYSTEM CONSOLE............................................................................................................................................... 12 4 FUNCTIONAL DESCRIPTION ...........................................................................................................................13 4.1 VIDEO INPUT ....................................................................................................................................................... 14 4.2 VIDEO PROCESSING ............................................................................................................................................ 15 4.2.1 Composite Video Processing.....................................................................................................................15 4.2.2 DVI Video Processing ...............................................................................................................................18 4.3 VIDEO OUTPUT ................................................................................................................................................... 20 4.4 GRAPHIC OVERLAY (RADAR) AND SCAN LAYER .............................................................................................. 21 4.5 INTERVAL TIMER ................................................................................................................................................ 22 4.6 VECTORED INTERRUPT CONTROLLER................................................................................................................ 22 4.7 DDR3 SDRAM CONTROLLER ........................................................................................................................... 22 4.8 I2C BUS MASTERS .............................................................................................................................................. 22 4.9 DEBUGGING SYSTEM .......................................................................................................................................... 22 4.10 TRACE SYSTEM ................................................................................................................................................... 23 4.11 MONITOR............................................................................................................................................................. 23 4.12 EXTERNAL DDR3 SDRAM................................................................................................................................ 24 4.13 NIOS II PROCESSOR AND ON-CHIP MEMORY FOR PROGRAM CODE ................................................................ 24 5 OPENING THE EXAMPLE DESIGN .................................................................................................................28 5.1 OPENING THE QUARTUS II TOP-LEVEL PROJECT .............................................................................................. 28 5.2 OPENING THE QSYS SYSTEM .............................................................................................................................. 28 5.3 VIEWING THE PARAMETERS ............................................................................................................................... 28 5.4 EXAMINING AND RECOMPILING THE CONTROL CODE ...................................................................................... 31 5.5 BUILDING THE SOFTWARE IN THE NIOS II SBT FOR ECLIPSE........................................................................... 32 5.6 RUNNING THE NIOS II CONTROL PROGRAM ..................................................................................................... 33 5.7 DEBUGGING THE APPLICATION SOURCE CODE ................................................................................................. 33 5.8 SETTING UP SYSTEM CONSOLE FOR DEBUG VISUALIZATIONS ........................................................................ 34 6 SET UP THE HARDWARE AND CONFIGURE THE FPGA ........................................................................40 6.1 SET UP THE CYCLONE V VIDEO DEVELOPMENT PLATFORM............................................................................ 40 6.2 CONFIGURE THE CYCLONE V DEVICE ............................................................................................................... 41 6.3 DOWNLOAD THE NIOS II CONTROL PROGRAM.................................................................................................. 42 7 APPLICATIONS FOR THE EXAMPLE DESIGN ...........................................................................................43 7.1 SINGLE VIDEO STREAM INPUT ........................................................................................................................... 43 7.2 MULTIPLE VIDEO CHANNEL INPUT.................................................................................................................... 44 7.3 OTHER VIDEO INTERFACE STANDARDS............................................................................................................. 45 8 CONCLUSION .........................................................................................................................................................46 9 REVISION HISTORY ............................................................................................................................................47 2 Introduction The Altera® Video and Image Processing Design Example demonstrates the following items: A framework for rapid development of video and image processing systems Dynamic scaling, clipping, flashing, moving, sharpening and FIR filtering of both standard definition (SD) and high definition (HD) inputs Picture-in-picture mixing with a background layer Run-time control of different parts of the system, including a radar that uses on-screen display functions. Debugging components for monitoring the video stream from within the data path The design example runs from the Bitec HSMC DVI and Bitec HSMC Quad Video daughter cards. The standard definition video stream is in either National Television System Committee (NTSC) or phase alternation line (PAL) format. The high-definition video stream uses a digital video interface (DVI) port. The design example uses some of the parametrizable IP cores that are available in the Video and Image Processing Suite. Table 1 shows some of the available IP cores. Table 1 Video and Image Processing Suite IP Cores IP Core Description Implements a 3x3, 5x5, or 7x7 finite impulse response (FIR) filter on an image 2D FIR Filter data stream to smooth or sharpen images. Mixes and blends multiple image streams—useful for implementing text Alpha Blending Mixer overlay and picture-in-picture mixing. Changes the sampling rate of the chroma data for image frames, for example Chroma Resampler from 4:2:2 to 4:4:4 or 4:2:2 to 4:2:0. Provide a w ay to clip video streams and can be configured at compile time or Clipper II at run time. Clocked Video Input (CVI),
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