DIRECT MEMORY ACCESS INTERFACE OF MC6800 WITH THE
TDCIOIOJ LSI MULTIPLIER AND THE APPLICATION AS A DIGIT.~ FILTER
A Thesis Presented to
The Faculty of the College of Engineering and Technology
Ohio University
In Partial Fulfillment
of the Requirements for the Degree
Master of Science
by
Hsiao-Chen Hsueh/
March, 1983 ACKNO\~EDGEMENTS
I wish to express my gratitude to Dr. Harold F. Klock whose guidance and patience make this work possible. Thanks are also due to my wife
Jenny for her patience and understanding throughout the course of the work.
ii LIST OF CONTENTS
page
ACKNOWLEDGMENTS · . ii LIST OF FIGURES · . vi LIST OF TABLES ...... viii Chapter
1. INTRODUCTION · . 1
1.1 Objectives ••••••••••••••••••••••••••••••••••••••••••••• 1
1.2 Scope of the Succeeding Chapters ••••••••••••••••••••••• 3
2. REAL-TIME DATA PROCESSING OF THE MICROPROCESSOR SYSTEM 6
2.1 Multiplication ••••••••••••••••••••••••••••••••••••••••• 6
2.2 Multiplication with LSI Fast Multiplier •••••••••••••••• 8
2.3 Multiplication with LSI MPY-16 and DMA Technique ••••••• 12
2.4 DMA Controller ••••••••••••••••••••••••••••••••••••••••• 15
3. CONTROL FUNCTION OF THE MICROCOMPUTER FOR REAL-TIME PROCESSING 16 3.1 Microprocessor ...... 16
3.2 Control Function Description - DMA Control •••••••.•.••• 18
3.3 The Maskable Interrupt (IRQ) and WAIT Instruction •••••• 23
4. HARDWARE IMPLEMENTATION OF DMA INTERFACE FOR LSI MULTIPLIER 28
4.1 Introduction ...... 28
4.2 The Control Logic of The Multiplier, MPY-16 (TDCIOIOJ) 28
4.3 Initialize and Start The DMA ••••••••••••••••••••••••••• 29
4.4 Address Counter of The DMA Controller 32
iii 4.5 DMA Word Counter and Sequence Control ...... 38
4.6 Accumulation Control and Output Control of The Multiplier 42
4.7 Conclusion ...... 45 4.8 Modification and Testing Experiment on Heathkit ET-3400
for DMA Data Transfer Design ...... 51 5. DIGITAL FILTERING, AN APPLICATION OF A FAST LSI MULTIPLIER AND DMA TECHNIQUE ...... 53 5.1 Digital Filtering S3
5.2 Elements of A Digital Filter 56
5.3 A Simple Digital Filter 57
5.4 AID, D/A and SiR Device ...... 64 5.5 IRQ Configuration ...... 69
6. DATA FORMAT AND SIGNAL SCALING 73
6.1 Data Format 73
6.2 Scaling Factor ...... 74
6.3 Signal Scaling 75
7. SOME REAL EXAMPLES OF DIGITAL FILTER 81
7.1 Maximum Sampling Rate 81
7.2 Digital Filter Examples 81
7.3 Errors and Accuracy ...... 100 8. CONCLUSION AND SUGGESTIONS ...... 101 8.1 Review ...... 101
8.2 Further Developments and Studies 102
LIST OF REFERENCES 104
iv APPENDIX
A Multiplier-Accumulator Parallel 16-Bit ••••••••••••••••• 105
B Timing Diagram of DMA Control Signals •••••••••••••••••• 110
e.l ADC-HX12B 12-Bit AID Converter ••••••••••••••••••••••••• III
C.2 DAC-UP8BC 8-Bit D/A Converter •••••••••••••••••••••••••• 115
C.3 SHM-IC-l SiR Device •••••••••••••••••••••••••••••••••••• 118
v LIST OF FIGURES
1-1 Block Diagram of D!A, AID Converters with the Fast LSI
Multiplier and DMA Logic in A Micro-system ••••••••••••••• 4
2-1 The Basic Logic Diagram for TRW 16-Bit MAC Unit •••••••••• 9
2-2 MPY-16 Multiplier Interfaces with 6800 ••••••••.•••.•••••• 10
2-3 A Direct-Memory-Access Interface 13
2-4 A Simple Data Channel for DMA Controlled Multiply •••.•••• 14
3-1 The 6800 Microcomputer System •••••••••••••••••••••••••••• 17
3-2 HALT CPU Signal Timing ••••••••••••••••••••••••••••••••••• 1y
3-3 Block Diagram of Sychronizing HALT and BA ••••••••••.•.••• 21
3-4 Synchronized HALT and BA Timing •••••••••••••••••••••••••• 22
3-5 Flowchart for A Simple Input/Output Interrupt Program 26
4-1 TDCIOIOJ Control Timing Diagram •••••••..••.••••••••••••.• 30
4-2 Address Decoding for Initializing and Starting D}~ ••••••• 31
4-3 Synchronizing HALT and BA, Pulse Width Generated with a
One-Shot •••••••••••••••••.•••••••••••••••••••••..•••••.•• 33
4-4 Block Diagram of DMA Address Generator 35
4-5 Timing Diagram of D}~ Address Counter 36
4-6 Hardware Implementation of Address Counter 37
4-7 Interface Between The Data Bus and The Multiplier •••••••• 40
4-8 Timing Diagram for Word Counter •••••••••••••••••••.•••••• 41
4-9. Hardware Implementation of Word Counter and" Sequence
Control 43
4-10 The Difference by Using Rip~le Counter or Synchronous
Counter for word Counter 44
vi 4-11 The Accumulation Control Signal •••••••••••••••••••••••••• 45
4-12 Control Timing for The Multiplier Output and Interface
with The Data Bus •••••••••••••••••••••••••••••••••••••••• 46
4-13 Output Control Logic for The Multiplier •••••••••••••••••• 47
4-14 Timing of Related Control Signals in A DMA Cycle ••••••••• 48
4-15 The Pin Connections between The Multiplier and Data Bus 50
4-16 Modification Being Made on Heathkit ET-3400 to Fit DMA
Block Data Transfer •••••••••••••••••••••••••••••••••••••• 52
5-1 Block Representation of A Digital Signal Processing System 54
5-2 The Realization of (a) N-th Order Nonrecursive Filter
(b) 2nd Order Recursive Filter •••••••• 58
5-3 A Simple Digital Signal Processing Based on The 6800 with
DMA and The MPY-16 ••••••••••••••••••••••••••••••••••••••• 59
5-4 The Processing Flow of A Simple Digital Filter System 61
5-5 The Analog-to-Digital Converter and The Interface with
Data Bus ...... 65 5-6 The Digital-to-Analog Converter and The Interface with Data Bus ...... 67 5-7 The Sample-And-Hold Device and The External Clock •••••••• 68
6-1 Variable Gain,Digital Filter ••••••••••••••••••••••••••••• 77
7-1 Timing Diagram of WAI and IRQ at Optimum Response •••••••• 83
vii LIST OF TABLES
2-1 An 6800 Coded Application Program for The MPY-16 •••••••••• 11
3-1 Memory Maps for 6800 Address Used in Response to Interrupts and Reset ...... 23 5-1 Digital-Filter Elements •••••••••••••••••••••••••••••••••• 57
7-1 Mathod of The Maximum Sampling Rate Calculation •••••••••• 82
viii Chapter 1
INTRODUCTION
1.1 Objectives
Real-time processing is the act of processing data as it arrives, as opposed to storing it, and processing it at a leisurely pace. In years past, real-time processing tasks were difficult to handle using microprocessors because of the machines' slow speed and small data-word size, especially if complex arithmetic operations are involved.
Multiplication and division naturally slow most microprocessors, because few have multiply and divide instructions. At least 16 bits of data are used in any serious arithmetic processing, so double precision mathematics must be performed on 8-bit microprocessors, further hindering processor performance.
A more reasonable approach to this problem is the use of an external arithmetic processing unit dedicated to performing double-precision arithmetic at a very high rate. Such a processor can be built out of discrete components, or one of the new monolithic processing units can be interfaced directly to a microcomputer bus. The objective of this
thesis is to demonstrat~ how to achieve the multiplications in a micro
system at high speed with a dedicated hardware multiplier and how to get the data to and from the multiplier fast. For these purposes, high-
speed monolithic multipliers such as TRW's MPY-16 (TDCIOIOJ) can be
used. The MPY-16 is a 16 x 16 one-chip multiplier that can generate a
32-bit product in 200ns. When interfacing chips such as this to a
1 2 microprocessor, careful analysis must be done beforehand to determine if the vast multiplying power can successfully be utilized by the microprocessor. Interfacing a 200ns multiplier to a 1MHz 6800, for instance, would be overkill, because it takes at least 12us just to move two operands to the multiplier under processor control.
Alternatively, a more effective way is to apply the direct-memory- access technique to the data transfer between the memory and the multiplier. However, the DMA data transfer is device-initiated. A program-dependent decision to transfer data requires a programmed instruction to cause a DMA service request. This is hardly worth the trouble for a single-word transfer. Most DMA transfers, whether device or program initiated, involve not single words but blocks of data words. Many forms of processing such as graphics, image, and signal processing require many multiplication operations. For these applications, high-speed DMAblock data transfer is especially suitable.
A particular application of the fast multiplier with the AID and D/A converters as a digital filter is discussed in the later chapters. An example is a 2nd order nonrecursive digital filter which is characterized by Equation(l.l): (see also Figure 5-1)
(1.1) where n = 0,1,2,3,.... The system has to perform three multiplications, two additions and transfer seven data words to or from 3 the multiplier during each T time increment (T is referred to the sampling period of the system). A block diagram of such a system is depicted in Figure 1-1; it shows that DMA interfacing is applied between the multiplier and the microcomputer system to make fast data transfer.
1.2 Scope of the Succeeding Chapters
In chapter 2, the Heathkit 6800 trainer (ET-3400) will be the example used to discuss the advantage of applying a hardware multiplier to the micro-system. The general interfacing and the direct-memory-access logic between the micro-system and the multiplier will be discussed.
Chapter 3 introduces the INTERRUPT and HALT features of the processor and the constraints in linking these features with the DMA operation to achieve an automatic block data transfer. The special WAI instruction of the 6800 is emphasized during this application. In chapter 4, the specifications of the LSI multiplier are introduced. The detailed design for hardware implementation of DMA logic is also shown in this chapter. Although the 6800 system is taken for the example to demonstrate the DMA logic between the processor and the multiplier, the
DMA logic is designed to allow the LSI multiplier to be able to interface with some other major processors. In chapter 5, the digital filter will be the particular example to demonstrate the application of the LSI multiplier. A general description on the digital filter and the supporting software are also provided. The AID and D/A converters are included in the digital filter to allow it to act on analog signals directly. In chapter 6, several constraints such as the unity gain of ~ A(jdreS~i~ '"""':;IE:-" Addl'eu~ _ Bus .,..) ~
'-oil Load address DIM Start convert Sampling -, Logic
Sequence
CPU Control MEMORY
rv s/H LSI ---.
Multi plier Analot! in
A/D II D/A
Data I/O data out data in data I/O 4 ~ ~
'IiIII",.. ,.,'IiIII I L ~ll..I...... , Data K .....~ Da ta Bus
Figure 1-1
Block Diagram of the Particular Application of O/A and AID Converters with the Fast LSI Multiplier and DMA Logic in A Micro-system -+> 5 the digital filter and the fixed point 2'8 complement data formats, and the data scaling factors which are applied during the digital filtering processing, are discussed. Chapter 7 presents the experimental results of several different types of digital filters. The amplitude responses, input/output waveforms of those filters are shown. Chapter 8, concludes the topic with a brief description of how the LSI multiplier and the
DMA technique upgrade the microprocessor's capabilities. Some further approaches are also suggested. Chapter 2
REAL-TIME DATA PROCESSING OF THE
MICROPROCESSOR SYSTEM
2.1 Multiplication
The algorithm for multiplication can be implemented perfectly well in software. but such programmed approaches to arithmetic operations can often prove Quite slow. The software of the 6800 microprocessor takes about 300 microseconds(l) to perform an 8-bit multiplication algorithm.
There are a number of possible approaches to gain speed in operations involving multiplication. These may vary all the way from just tightening up the code to putting a full hardware arithmetic unit into the processor.
In the 6800 example, the result of a 8 x 8-bit multiplication is a
16-bit Quantity, but sometimes only the most significant 8 bits are used; the rest are truncated. It is therefore a waste of time to compute the entire 16-bit product when only H bits will be used. To gain maximum speed we use a special multiply routine called 'fractional multiply'. Here the multiplicand and multiplier are assumed to be rn/256 and n/256 where m, n are the actual values passed to the subroutine.
The multiplication thus executes only those steps required to form the
8-bit result desired. The following program shows the fractional multiply subroutine coded for the 6800.
6 7
NAM FRACMUL * PARA~~TERS IN A AND B AceL~ruLATORS * PRODUCT RETURNED IN A ACCU~uLATOR * FRAC!\1L STAA TErw1P SAVE CONTENTS OF A eLM * MLOOP LSR TEMP ARGl = ARG1/2 ASLB CARRY = MSB(ARG2) sec NONADD CARRY = 01 * ADDA TEMP ADD IF CARRY = 1 * NONADD ENE MLOOP LOOP AGAI~ IP ARG2 NE 0 * RTS OTHERWISE DONE * TEMP Rr.13 1 * END
It expects the multiplicand in the A accumulator and the multiplier in the B accumulator. The program takes 140 microseconds to do an
8 x 8-bit multinlication. It cuts down the executing ti~e by half but with a penalty of less accuracy. However it is still far from the requirements for a microprocessor in real-time application. The requirements in real-time applications such as real-time data acquisition, signal processing and digital filtering demand both speed and accuracy. Another solution to the multiplication problem is to apply a special piece of hardware to perform the multiplication for the host processor. 2.2 Multiplication with LSI Fast Multiplier 8
The MPY-16* fast multiplier integrated circuit (Figure 2-1) is especially suited for an 8-bit microprocessor supplying 16 x 16 multiplication that greatly upgrades the real-time capability of the microprocessor system. The multiplier accepts X and Y input operands
in the 2's complement form and supplies the double-precision products with the same form in 200nsec. Because of the tri-state output buffers, it can interface with a microprocessor through a single data bus. Figure 2-2 diagrams the interfaces with the 6800. The 6800's bus concept, with addressable input/output, keeps the interface problem to a minimum and programming relatively simple. In these setups, the X and
Y operand registers are treated as memory locations. Four such locations are required for MPY-16 and only four store accumulator and load accumulator instructions are required to perform one 16 x 16 multiplication. Table 2-1, an excerpt from an application program, illustrates the simplicity of programming.
This subroutine uses the accumulators in the 6800 to store and load the X and Y operands into and out of the MPY-16. The clock and control signals for the multiplier's tri-state output buffers are easily generated from the address, read/write, and clock signals from the microprocessor. The CPU is left to perform the tasks it is more efficient at, memory management (getting data into and answers out of
the MPY-16) and control. The MPY-16, on the other hand, does the
* TDCIOIOJ, by TRW, also see Appendix A THREE STATE EP PRE LOAD ORMSP OR lSP
MAC-I6 (TOC101Wt. N :: 16 CLOCK PRODUCT
EXTENDED PRODUCT. N EP X1N >--+---I REGISTER
CLOCK X
ACCUMULATE. MOST SUBTRACl ~ .' • SIGNIFICANT ROUND OfF. ~ + t--+--I REGISTER PRODUCT. 2'S COMPLEMENT MSP
CLOCK Y .. YIN ~ REGISTER LEAST ~ .'.. SIGNIFICANT I PRODUCT. LSP CLSPOUT. I 2N.1 LSP PRE LOAD IN. II MAC·1S ONlV. I 'I PRELOAD ~ I L ~------J
Figure 2 - 1
The Basic Logic Diagram for TRW 16-Bit MAC Unit
\0 10
CLOCK AND MCsaOO RESTART
ADDRESS 16
DATA CONTROL
ROM RAM
LSI ~8 LSI MS8 lSI .., ¥ X MSP ....._--.n CONTROL Mpv·18
Figure 2-2
~~-16 Multiplier Interfaces with 6800 11
Table 2-1
An 6800 Coded Application Progr~m for The MPY-16
SUBROUTINE MPY # OF CLOCK eye LES
LDAA O,X LOAD X OPERAND 5 LOAB i .x 5 STAA MPYXL STORE X OPERAND 4 STAB WLPYXlw1 4 LDAA 2,X LOAD Y OPERAND 5 LDAB 3.X 5 STAA MPYYL STOR! Y OPERAND 4 STAB MPYYM 4 LrAA MYiYL LOAD PRODUCT (LSP) J LDAB MPYYM J STAA PRODLL STORE PRODUCT (LSP) 4. STAB PRODLM 4 LDAA l'fJ'YXL LOAD PRODUCT (r~p) J LDAB MPYXM 3 RTS RETURN 56 To-:al 12 number-crunching operation on the data t at a speed of a thousand times faster than possible with the microprocessor. The much slower speed of
the MC6800 means the multiplier can complete a multiplication long
before the processor can return to get the result. The actual multiply
time is 56 microseconds for a 16 x 16-bit multiplication, whereas
software execution takes 300 microseconds. This great increase in the
computational power extends the range ot applications for the 68UO into
the signal-processing domain.
2.3 Multiplication with LSI MPY-16 and DMA Technique
Even memory management tasks are sometimes too time-consuming for the microprocessor central orocessing unit, necessitating the nse of a
separate high-speed memory-address generator and a direct-memory- address controller. Direct-memory-access systems can transfer data
blocks at very high rate (106 words/second is readily Dossible) without elaborate I/O programming. This arrangement leaves the microprocessor with just the job of system controller, sending only macro-instructions
and memory-block locations to the real-time processing section. Such a
system organization is shown in Ef gur e 2-3 and Ei.gure 2-4 _ It c.an
perform real-time vector or array multiplications. In operation, the
CPU of Figure 2-4 uses the DMA controller to transfer a block of data
from main menory to the MPY-16 and essentially deals with buffer areas
in its own memory_ Only a few I/O instructions are needed to initialize
or reinitialize transfer. The DMA controller takes full control of the
system bus for the block data transfer at top speed. 13
Data Bus "- Memory ~...E:t======:E;~Data Read or Write
Transfer Cycle-Steal Request Service Request Priority Grant DMA Transfer Data ., Control Timing Logic Enable Decrement
1 [ncrement Current '----...---t Address Word ~ Multiplexer Address - -: -= -: ~ -_- or Sequence Memory Gates Counter Counter -jControl Address Initial --~ ...jII1I~~ Preset Address Word Counter
Digital Device on Computer II Channel Programmed I/O Bus
(Data, Address, and Control)
Figure 2-3
A Direct-Memory-Access Interface 14
Data X - N I/O ~ Address Algorithm RAM c crrtr-ol : Logic Multiplier ( MPY-16 ) Data N Address Y I/O RAM/ROM
Sequence _ Control
OUT
2N+J Direct Micro Memory Program Latch I I Access Control I Control
To CPU Main Bus
Figure 2-4
A Simple Data Channel for DMA Controlled Multiply 15 With the special feature of MPY-16, controllable addition or substraction in the output accumulator, the real-time system can calculate a sum of products in just a few microseconds. It no longer make sense to use a more complicated algorithm than necessary, and. in fact the simple canonical algorithms are beginning to be attractive. In some application, there are many signal-processing algorithms that are nothing more than a sum of products, such as finite-impulse-response digital filters. All that is needed is for the direct-memory-access controller to send a series of coefficients and data words into the
MPY-16 and read out the answers once the multiplier has exercised its number-crunching expertise.
2.4 DMA Controller
A simple D~~ system involves a DMA controller, address gates, a current-address counter and a word counter; as shown in Figure 2-4.
~fhen a service request arrives from, say, an analog-to-digital converter or data link, the D~~ control logic implements successive cycle-steal requests and gates successive current addresses into the memory address register as the current-address counter counts up. A block of words to be transferred will occupy a corresponding block of adjacent memory registers. In Chapter 4 the digital design will deal mainly with the DMA controller of the 6800 for the specific realtime device, the MPY-16. Chapter 3
CONTROL FUNCTION OF THE MICROCOMPUTER
FOR REAL-TIME PROCESSING
3.1 Microprocessor
The MC6800 is one of the most widely used microprocessors. The 6800
instruction set's direct addressing mode and extensive conditional
branch capabilities allow the majority of the instructions being
performed to be two bytes long. This reduces memory requirements and decreases memory access, thereby increasing processor performance(2).
These factors make the 6800 desirable in real-time application in which
execution speed is important. Figure 3-1 shows the 6800 system.
The 6800 relies on memory-mapped 1/0(3). No independent I/O channel
or I/O instructions are provided. Device registers that act as memory
locations must be provided. The advantage to this approach is that
fewer processor control lines are required, so I/O programming is
considerably simplified. The DMA peripherals can communicate directly with other devices as with memory with no additional control lines or
logic. The disadvantage of memory-mapped I/O is that every interface on
the bus must be able to recognize its address and go through the strict
protocol as memory access. The 6800 however, avoids these pitfalls
with a simple memory r/o protocol. He may reserve a certain section in
the top 32K of the 64K address space for I/O devices. The most
significant bit of the address (A1S) thereby acts as an I/O bit and can
be used along with a few other bits to distinguish between interfaces
16 17
Control Signals ~ lfRlf I SA 08£ ¢2 CPU ¢~ TSC H1'tT NMi VMA .0-A15
AO-A9 080-017 ROM E E
AO-A6 010-017 8 data 16 address lInes lines £ RAM E E E ! R/W E
To Ifrom odd itionol memory end lor 110 ports
Figure 3-1
The M6800 Microcomputer System on the bus , 18
3.2 Control Function Description - DMA Control
The HALT line provides an input to the CPU to allow control of program execution by an outside source. It is a negative-going, level- sensitive input. If HALT is high, the CPU will execute the instructions; if it is low, the CPU will go to a halted mode. A response signal. Bus Available (BA), provides an indication of the c.urrent CPU status. When BA is low, the CPU is in the processing of executing the control program; if BA is high, the CPU has halted and all internal activity has stopped. Meanwhile the address bus, data bus, and R/W line will be in high impedance state, effectively removing the
CPU from the system bus. V}~ is forced low so that the floating system bus will not activate any device on the bus that is enabled by VMA.
Figure 3-2 shows the timing relationships involved when halting the
CPU. The instruction illustrated is a one-byte, 2-cycle instruction such as CLRA. When HALT goes low, the CPU will halt after completing execution of the current Lns t ruct Lon , The transition of HALT must occur tpcs before the trailing edge of ¢1 of the last cycle of an instruction
(noint A of Figure 3-2). The fetch of the operation code by the CPU is the first cycle of the instruction. If HALT had not been low at point
A but went low during ~2 of that cycle, the CPU would have halted after completion of the following instruction. BA will go high by time t BA (bus available delay time) after the last instruction cycle. At this point, the V}~ goes low; the R/W line. the address bus and the data bus L...., Cyde of Current 'n~truc:tlon , n • .,uction I,nt,ruction I Fetch E lC8cute .1 teA I .2
H;'it 'SA
8A
VMA ~ \ II / c=\
/-----;----~ -~ II 1~ ~ AiW F.tch h_ut. M t Add,... I <,.._ BUI
Date BUI tnl' )(
Note: Midrange waveform indicates high impedance state
t pc s Processor Control Setup Time, 200nsec min
t per Processor Control Rise and Fall Time t pc f lOOnsec max t BA Bus Available Delay, 250nsec max
Figure 3-2
HALT CPU Signal Timing
...-... TNill go low at tBA after the leading edge of the next ¢1, Lnd i ca t i.n g that the address bus, data bus, V}~ and R/W lines are back on the bus. The ru\LT signal which is the Cycle-Steal-Request signal in the D~~ logic block diagram (Figure 2-3) will float the processor for a IDlrnber of clock cycles fnr the DMA automatic block transfers. On the other hand, the BA will be the role of Priority-Grant signal. The HALT is generated by the Service":"Request signal from the outside source. In order to meet the constraint on the transition of HALT, it is necessary to synchronize the HALT with the ¢1 clock to ensure that the transition of HALT occnrs at least 200nsec before the tr~iling edze of 01- The CPU responds to the Service Kequest by executing the ST~~* ONESHT instruction at extended mode addressing, the address decoding out ou t will enabLe the DlylA control logic to issue a Cycle- SteRI-Request signal. With this modification, it ensures that the transition of ~~LT occurs not only 2UUnsec before the trRiling edge or tl but also in the last cycle of the STAA* ONESHT instruction. The i~DlementRtion is shown in Figure 3-3, and Figure 3-4 shows the timing i·.' Cycle # ~ Address Bus Data Bus 1 1 Op Code Add. Op Code STAA Destination Add. High-byte or 2 1 Op Code Add. +1 1 Op Code Add. +,2 Destination Add. Low-byte STAB J 4 0 Operand Destination Add. Hi-Z 5 1 Operand Destination Add. Data from Accumulator ONESUT VMA DECODEH .• ST ONE RHOT tr 6800 CPU _.... -- TRIGGF:RED D-FF .~-- - BA(,1 _._- FigLlre J- 3 Ulock Diagr'am of Sychr-on l z i ng HALT and BA N ~ I 4flt crcle • last cycle I ¢1 --I·-Lf~ IL ¢2 . : .'.. . VMA I I :: I ~ ...,; . " . ------..------: : :: . STAA ONESHT ~ ] :: ~ . " .'. . ~ : ONESHOT ---1 : :: : OUTPUT I ; .: · ·• .• I , ·• . I.. HALT I ::.' .: .• -_~~t-ur--~!------BA ______..:.;__ . -.~ I ~2 usee ~ I~-- BAQ -·__ Figure 3-J.~ Synchronized HALT and BA Timing N N 23 of those signals. BA is synchronized with the 02 clock. This gives us a constant delay between the occurrence of HALT and BAQ. This modification is necessary for the later application on digital filtering; BA will be replaced by BAQ as the Priority-Grant signal. 3.3 The Maskable Interrupt (IRQ) and WAIT Instruction The HC6800 responds to an Interrupt(4) by executing the following sequence: 1. Complete the current instruction. 2. Save the contents of all the user registers in the Stack. 3. Disable the maskable interrupt(IRQ); i.e., it sets bit 4 (I) of the Condition Code Register. 4. Get the identify and service routine address by fetching an address from a specified pair of memory address and put that address into the Program Counter. Table 3-1 contains the addresses used by the various inputs and instructions. Table 3-1 Memory Maps for 6800 Addresses Used in Response to Interrupts and Reset Source IAddresses Used Reset (RESET) _I FFFE, FFFF Non-maskable Interrupt (NMI)i FFFC, FFFD Software Interrupt instruc tion (SWI) FFFA, FFFB Interrupt Request (IRQ) FFF8, FFF9 24 The content of addresses FFF8 and FFF9 is either a starting address of the interrupt service routine, or the starting address of a routine that chooses the starting address of the interrupt service routine. A typical monitor routine would be: UIRQ L~ USRINT GET ADDRESS INTADD • FOR INTERRUPT • SERVICE ROUTINE ~ 0, X where UIRQ = (FFF8,FFF9), INTADD = (USRINT, USRINT + 1). The WAIT instruction is used to decrease the time required to service a hardware interrupt; it stacks the CPU registers and then floats the system buses and waits for the interrupt to occur. This technique effectively removes the stacking time from a hardware interrupt sequence. A high-speed device in a real-time system always requires fast interrupt response and data transmission. Thus in such a system, the interrupt and DMA techniques are always concatenated. As discussed in the previous chapter, with the fast LSI multiplier doing the mathematical function in real time, the microprocessor is left to perform memory management tasks. The following program structure shows a typical real-time interrupt routine for this example. The main program should start at the RESET address so that the system will operate correctly when power is turned on. It will be: 25 ORG RSTADD • WAIN PROGRAr.! eLI ENABLE INTERRUPTS Pl WAI WAIT FOR INTERRUPT BRA Pl ORG INTADD . SERVICE ROUTINE RTI Figure 3-5 contains flowcharts of the main program and the interrupt service routine. Hardware rather than software checks the interrupt bit. The eLI instruction re-enables the interrupt that has been prohibited by RESET. In the 6800 CPU structure, instructions which affect the I-BIT act upon a one-bit buffer register, 'ITMP'*. This has • Condition code register (S) 'ITMP' l-Bit 'buffer register (a) Main program 26 ( START <, CONFIGURE INTERRUPT SYSTEM ..I CWAIT LOOP) I ~------ IS INTERRUPT NO ACTIVE~ YES (b) Interrupt service routine OUTPTJT DATA Figure 3-5 Flowchart for A Simple Input/Output Interrupt Program 27 the affect of delaying any CLEARING of the I-BIT one clock time. With the delay, it guarantees that the interrupt won't go active right after the eLI instruction has completed. An important feature of the program structure is that the branch always instruction leads interrupt-return back to the wait state. This makes the system have the optimum response to an interrupt and is easily expanded into multiple-channel interrupt systems. Chapter 4 HARDWARE IMPLEMENTATION OF D~~ INTERFACING FOR LSI FAST MULTIPLIER 4.1 Introduction The hardware design for the direct-mernory-access interface between microprocessor and the LSI fast multiplier is based on the Heathkit ET-3400. a 6800 system. As we described it. the DMA dRta transfer is device-initiated. A program dependent decision to transfer data, even directly from or to memory, still requires a program~ed instruction to cause a D~~ service request. All of the design is beginning froM the interrupt service routine program: * * INTERRUPT SERVICE ROUTINE * ORG INTADD INTADD STAA C~R *INITIALIZE DMA PREPARE DATA . STAA ONESHT *START DMA TR~NSFER RTI The 'STAA CLEAR' initializes the D~~ controller by resetting its flip-flops and counters; the 'STAA ONESHT' starts the DMA transfer. In Chapter 2. the Figure 2-3 shows the DMA interface block diagram. The hardware design will be based upon this scheme. 4.2 The Control Logic of The Multiplier, MPY-16 (TDCIOIOJ) The Figure 4-1 illustrates the control timing of TDCIU1UJ for the 28 D~~ processing. where: 29 Data input (X to X and Yo to Y ) o 15 15 Data inputs are loaded into the X register and Y register at the rising edge of eLK x and eLK Y, respectively. Data output (Po to PJ4) The product generated is loaded into the output register at the rising edge of eLK P. Tri-state least, most and extended control (TSL, TSM, TSX) The LSP, MSP or XTP output buffers are at high impedance when TSL,TSM or TSX is high. The output buffers are enabled when TSL, ISM, or TSX are low, and PREL is low. The detailed operation description and the parameters in Figure 4-1 can be found in Appendix A. The 2'8 complement fractional notation will be carried over to the design. 4.3 Initialize and Start The DMA In the Heathkit ET-3400 system memory mapping, the addresses from SDUOO to $EFFF are reserved for I/O purpose. The addresses of CLEAR and ONESHT, where CLEAR EQU $EFFO and ONESHT EQU SEFF3 are not fully decoded. The address bits from A4 to All are DON'T CARE actually. Fi~ure 4-2 shows the pin connection of hardware implementation for the address decoding. X'N'Y'N,TC ~ I'V ANO, ACC, SUU-.M0NTROl AND DATA I~ _ l--- TS - -+---TH----t FTPW~ ClKX,ClKY _ I.... TMA------t I LOAD TIMING I OUTPUT TIMING PRELOAD TIMING I ., I - ~ , eLK P . , I I I I I I I PREl I I f I TSL,TSM,TSX I I I I J ~ ~I ~ ----I T01S I , ~TS-+-TH--l 4L I OUTPUT PINS ~ ~ ~ DATA OUT I~RElOAD IN D~ HIGH IMPEDANCE I I I I l---TO---t Figure 4-1 TDCl0tOJ Control Timing Diagram w :;> A 11 I _ 1 5 A -1_2 14 At) B_ tllG 1Y 14 STAA CLEAR A12-(>o 51 74LSJO O A ...... J 1Y1 5 HBYT A 1 2 71J.04 1Y 6 LBY'f 2 1/2 74LS139 TAA ONESHT 1YJ I? s 2 A1 lA 1 AO 1B A - are 16 address bits * O 15 of 6800. Figure 4-2 Address Decoding for Initializing And Starting DMA LoU ~ 32 The active low decoder output, STAA ONESHT, produces a programmable pulse period output by triggering a monostable multivibrator. The basic pulse time is programmed by selecting external resistance and capacitance values~ Equation 4-1(6) defines the value of pulse time. t = ~ w k· RTe C ·(1+ R (4-1) ext T for C where k=O.]2, R is in Kn, C is in pF ext>1000pF T ext t w is in nanoseconds The pulse is the HALT input of the 6800 CPU as a cycle-stealing request. The design is made to transfer a memory queue of 38 bytes by D~~ technique at a speed of 106 byte/second, so, the pulse width must be at least 38 microseconds long. From Equation 4-1, RT of 22K and Cext of 5490pF will produce a 40 microseconds pulse width by the 74123 monostable multivibrator. The requirements of synchronizing HALT and BA as described in Section 3.2 are implemented in Figure 4-3. 4.4 Address Counter of D~~ Controller The design defines a memory queue of 38 bytes in the user's RAJ1 soace with the starting address of $2000. The first 36 bytes are assigned to nine pairs of double-precision multiplicands and multipliers; the last two bytes are reserved for storing of a 16-bit product (or sum of products). Therefore, the address counter should be able to generate a string of successive addresses from $2000 to $2025 at a rate of 106 counts/second. The DMA controller simulates the 6800 CPU's fetch cycle to access the memory by applying the 6800 system clock ¢1 as the clock v cc Heathkit ET-J400 LAYOUT Cext -)1 lL_c_ Cext STAA ONES~T lIlA U !7412) 21tH Vce lQ J 11CLR Figure 4 -3 Synchronizing HALT and BA, Pulse Width Generated With a One-Shot W '.JJ 36. input of the address counter. The counter outputs are gated from the address bus by 16-bit tri-state buffers. Since there are 38 addresses to be generated by the counter, only the six least signification inputs of the 16 address buffers are defined by the outputs of the address counter, the other ten bits are left out as fixed inputs. As described in a previous chapter, BA is the signal which indicates that CPU has acknowledged the cycle-stealing request of DMA and transferred the control of system buses to the DMA controller. Also, BA serves as the enable signal of these address buffers. The counter will be disabled whenever it counts UP to 37 (decimal). Figure 4-4 gives the logic block diagram of the address generator, and Figure 4-5 specifies the timing of those signals which are related to the address generator and its outputs. The timing diagram reveals that the counter has to be reset by the decoding out pu t of •STAA. CLEAR' each time the direct-memory-access is incurred. That ensures that 52000 will be the first address being output onto the address bus as soon as the buffers are enabled by BA. Each address output from the counter will be valid for one microsecond, all the operations such as read/write data out-of/into memory, transfering data to or from the Multiplier or latching it into latches, have to be done during the one microsecond. It takes 38 microseconds to achieve the 38-byte DMA data transfer. The cpu's execution has been halted for 3Y microseconds. The one microsecond overtime is caused by the Bus Available Delay, tEA. of the 6800 CPU and the synchronization of HALT. The actual hardware configuration and pin connection are described in Figure 4-6. To meet STAA CLEAR ------ CLEAR COUNT ENABLE ~0=D---fCk ;1 Synchronous Counter Os °4 0] °2 °1 °0 LO HI LO OUTPUT BA ENABLE 16-Bit Trl-state Buffer To System Address Bus A1S ------AO Figure 4-4 Block Diagram of DMA Address Generator '...;.) 'J1 . Last Cycle Fet.ch Cycle of Cu~~ent I I I Inalcuctlon I4------. 1-- ---1 -l r r-l j-l_j-;:·::U:tlon 1 ,01 __J __ ~ _ ~2 lSl_JLJ-IJLJ~ FI_JUlJ L r DMA Process Period )I HALT l f S I t BA ~~~ ::tlr-t.-.------~- BA ------1 r------1, r------BAQ .. ------( 11l - . - _ CKl STAA CLEAR 1 2 3 ]7 Reset counter ~~~~::: (Y~x~ Output Addr 0 Addr 1 Ad<;tr 2 1~ Addr 31 ) l 00--- Q ' L-~ --1 S t-. F'igure 4-5 LV Timing Diagram of DMA Address Counter (j\ STAA CLEAR BAQ ---n-cK1 CKI 2 CKI 2 14LSl61 ill ir;o( Qc QD QA QB Qc QD TTl 1 2° 2 22 2) 24 25 GND GND -J 18 DU ,U QU JU ~u lU Vee ,LE tJD 7U I Vee 1: rE80- ?4LSJ?J .~I - OD BA --l...I 00 ft_ ~- t._ ...... -- -- BA 8~ 119 1 15 12 9 A A A A A A A A A A A A A 15 14 At) l 2 All IO 9 a 7 6 5 4 J 2 Al O Note. LE - Lateh Enable, Active-Lo on - output Disable, Active-Hi Figure 4-6 Hardware Implementation of Address Counter W '-J 38 the design requirement of minimum gate delay y the counter should have features of synchronous counting and asynchronous clear; the 74L5161 meets the requirements. 4.5 DMA Word Counter and Sequence Control The binary output of the word counter indicates that the nth byte of the queue is valid on the data bus. The locations of multiplicands, multipliers, and product in the memory queue must be defined in order to assign a series of sequence controls to transfer the data to or from the proper register of the Multiplier. The queue is arranged as follow: $2000 XeH MSB $2001 XoL LSB $2002 YaH $200) Yet $2004 XIH $2005 X1L $2006 Y'1.H ~ Tt I $201D X7 L $201E y~ $201F Y7L $2020 XSH $2021 XsI, $2022 YaH $2023 Ysl $.2024 P.H P,L 39 where Xi, Yi i=O to 8 are the operands which are corresponding to the X and Y registers of the Multiplier respectively. Figure 4-7 diagrams the i~terface between the Multiplier and the 6800 8-bit data bus. There are two 8-bit tri-state output transparent latches which hold the most significant 8 bits of Xi's, Yi's and the 16-bit products. The timings of the word counter and related control signals are described in Figure 4-8, the number which is shown in each CKI pulse represents the decimal equivalent of the address counter output. The number 'n' in each CK2 pulse indicates that the nth byte of data in the memory queue is valid on the data bus. The first data (XoR) is valid on the data bus during the first pulse period of CK2. During the same period, LE goes high and that allows the high byte of Xo to go through the transparent latches. XOH will be latched at the outputs of the transparent latches when LE goes low. When the second pulse from CK2 arrives, it indicates that both the high and low bytes of Xo are available at the X-register input of the Multiplier. The rising edge of X clock loads the 16-bit data into the X-register. The same sequence will be applied to loading data for the Y-register. The product (or the sum of products) will be generated and become valid 200ns after the Multiplier recognizes both the rising edges of X clock and Y clock. The P clock loads the product generated into the output register SOOnsec after the rising edge of Y clock. Since the LSP(Po to Pts) outputs are time-shared with Y data inputs, the 8-bit tri-state buffer has to be included to prevent bus contention while reading out the product onto the data bus. Data Bus Memory '" __ _ _R_;W----- ._-_ _~_. -- , " -~-- R/W from 8-bit 8-bit 8-bit CPU LE- Transparent ODI-J Tri-state TSM Transparent 001- Latch Buffer 002_ Latch BA Tis Buffer I WE r--- LE .------"1 D-. -001 n------Control -OD2 MSB LSB MSB LSB LSB MSB TSM '--v--.J \ " '------' XCK- X y MSP Logic XCK and YCK YCK- LSP ~K RjK_ ACe MPY-16 ( TDC 1010J ) ACC- Figure 4-7 Interface Between The Data Bus And The Multiplier o+-' - -~ BAQ _J rl _ next fetch J~l_J -~l_r--LF :~-IF:l_J~l_r:-LFLtL CKl 2 '-_J ~-----v---v---v~ Addre•• E add. Bus Add. 1 XAdd. 4 x: ~~~~~~dd.16 Add. 11 Data 8u. Cl(1 J. ti \ n _ x N I ~~ _ ~l----- y N I\ (I-- p W LJ I ACC ___I 001 ----s t------_I Figure 4 -8 p.. ~ Timing Diagram for Word Counter 42 The hardware implementation in Figure 4-9 is based upon the timing sequence of Figure 4-8. Same as the address counter, the word counter is cleared everytime the STAA CLEAR instruction is executed. It is noticed that ripple counters are used rather than synchronous counters, since the propagation delay at the outputs of the ripple counter is employed to eliminate those undesired glitches during the logic operation to produce the LE, X, Y, etc. control signals. The effect is demonstrated in Figure 4-10. 4.6 Accumulation Control and Output Control of The Multiplier As described in Section 4.4, the DMA controller is designed for sending a series of 9 pairs of 16-bit multiplicands and multipliers into the MPY-16, and restoring the sum of products. The TDCIOIOJ did not provide the 'CLEAR' function for its output register, so the Accumulation Control* (ACC) has to be reconfigured each time the DMA operation cycle is issued. It prevents accumulating the sum of product which is left over from a previous DMA cycle into the next cycle. Referring to the timing of ACe in Figure 4-8 and the operation description, the ACe line is brought low before the first rising edge of P-CK in each DMA cycle. Thus the first multiplication without ~::~~~~a:ion :ontrcl (ACe) wr.er. A':: is r.igh. the =ontents of the cu t put reglsters are adjed to the nex't produc t generated and tr.e i r 5~~ is st~r~d ~ack ir.'to the output registers at tte r:sir.g edge of the next CLK P. when ACe is lo~. m~l::p:icati~~ witnout acc~ulation is performej and the next product generated will oe stored ir.tc ~r.e ::.;tp.Jt registers di:-ectly. The ACe signal is loaded into the ACe register at the rising edg e of ~ ~- "'I'AA CLEAR ---- ... --r ..J Vee J _ Vee 12·7T}-~·-- frJ2r- ·---R~lh~--=R-o""""~------' Ho \ Ro\.::: ~2 ---r\ L11_ CK2 14 14 BAQ ~ , lAin 74LS9J in 74LS9J QB Qc QD QA Bin QB Qc -...-..-.----,r 19 ~. - 5 20 2 DDt I• Y x+y p I X ·Note: All the - r> are 7404 - ;' p- ,OLE All the =0---- are 7408 Figure 4-9 Hardware Implementation of Word Counter and Sequence Control -l-' LV CK2 .r!.1 i-: --"1:I: ILr:::: QA(20) · !;:: I I r Effect with ripple counter x+y= n~: ~ ·· . . . . CK2.0A n: :j.11~: QA(20 ) 1 il " II .. :• :... :< :' ., : ;:: Effect with synchronous " counter X+Y glitch glitch Figure 4-10 The Difference by Using Ripple Counter or Synchronous Counter for Word Counter .j> +:--- 45 accumulation is performed and the first product generated will be stored into the output register directly. The hardware configuration to generate the ACC is shown in Figure 4-11. STAA CLEAR----..., BAQ 1Q 5 Ace P CK i74L574 1Q 6 lPR Figure 4-11 The Accumulation Control Signal The D~~ controller reads the X, Y operands for the Multiplier from the memory. It also writes the 16-bit sum of products into the last two bytes which are reserved for it in the memory queue. The output control timing of the Multiplier is depicted in Figure 4-12, and the hardware implementation by applying a 74LS139 2 to 4 decoder, is shown in Figure 4-13. 4..7 Conclusion The timing diagram in Figure 4-14 is the recapitulation of the design which is discussed in previous sections. It shows the whole picture of the control signals which are related in a full period of the DMA 46 ODl BA j i-:------ 001 • SA 0....---_1 ",----I TSM U OD2 u TSM ------n------WE LJLJ DATA op codes or operands BUS Figure 4-12 ~ontr~l Timing for The Multiplier Output and Interface with The Data Bus Q · OD2 *Note& a is the 2° output of Address Counter Figure 4-1J Output Control Logic for The Multiplier -J::,' -.j fllJ·Lf:-LJ~LFU:UlFl§lJ~J:-U:t.FLFL-R§IRFLr~LJ~ r:LFl§LR,J:-ly:LRJ: __ ~~lf~t_fLJ~l_R_j~I:LflR ;2 --LfLJ-UU"U urn nJ-U-1J"l_n ruuuLJlJ1J-ULJl-ft un r"Lf-LrLnIl~Ul_JLJuu I_T t rt nnn__ J" HALT-----t -. f 8A?!. rL BAQ .l.__ 1 :. CKl _ J1FlJ1RJ;LJ:Lr~1_J·-LfLFLJ:t_FLRJ:LFLFLRJ:v:LFU~FLFI __ RYL.rlFLRJ~L.RJU1J-1-R r::tJ:1J-L_ CK2 1~'lJ:-LJ~l __RJ7LlliU~-Lfli·LFlFlJU:U:U=LFLFLFl,r:u:·LFLFLFLR-I:tj:l.-FIJ::U:-LFLFLRJ;LrLR, _ L£ __.-S-L__ fL_J--L5L J-L--l--l__JL._.fL_r-l..-SLfLJl JL_Jl__fLfL--'-LJ-' , X+y rL11.__JLJL-JL_-_JLrL_JL rL.-l-Ln~--l~-'_fL_rLSLrL__ ll,---__ x j-' n n tL_~l n n fl -j-l-.~ ._, _ y fl -n flu J-l n rL ~ I n f1- _ p u--Lr------Lt Lf U L_f U ----- ACC ----.J------001 --'----0------_.------_._------, WE------~------uu- TSM------lJ 002 ----.--- U·- Figure 4-14 Timing of Related Control Singals in A DMA Cycle -f-- cc 49 cycle. The actual pins connection of the Mtutiplier and system data bus is shown in Figure 4-15. There are two points should be noticed in that scheme: (1) only 16 bits out of the 32 bits product is fetched from a 16 x 16 multiplication. (2) the 16 bits of the product being fetched are from P1J to P 2S• The reason for the first point is that for the 2'5 complement fraction numerical system, the accuracy still meets the requirements of real-time applications if only the 16 most significant bits are put into processing and the others are truncated. Besides, to use all the 32 bits for a 16 x 16 multiplication on an 8-bit processor will be tedious and unnecessary. The reason for the second one is concerned with the scaling factor which will be covered in Chapter 6. Although several direct-memory-access controller chips are available to implement the D~~ processing in a particular micro-system, such as Motorolor MC6844 DMA controller to the 6800 system, the DMA interface between the LSI multiplier and the micro-system may vary from processor to processor. The DMA handshaking logic in this chapter has been designed as general as possible, just few program oriented controls along with the interrupt and the halt features of the processor are involved. :fost processors can interface the LSI multiplier with this D~~ interfacing logic without making any major change, since the processor halt and interrupt are provided by most of the microprocessors. Sys'tem Data Bus 50 t-t-t--t-+-+-+-+-+---.:.19~8Q OD LE 8D~~~_B""",, IIIlII.l'iiI6.... X1.s .....-;-...... ,...-+-+-+-+- -:;,1.-67Q 10 1? 57 X14 ~-+--+-o+-+ _ ..l~t; 6Q 6D 14 cA X1j ,....;--t--+--l1--lto_...1...2 SQ SD 13 .Q X12 ...... _9'-'4Q 4D B ~IO Xll t'-+-+-...-_6-., )Q jO :L t,1 X10 ...... - ...···~... 2Q 2D 4 ~12 19 .....__2=-41Q lD j 61 X8 7~I.SJ7J vee .!2-... SV ...... -+-~...... -+- 2:.;;4.~Yl 5 -+-~I-+ a.2';~Y14 ...... SUB~ -...... - 22 Y1j ...... -+-~~21 Y12 ...... 20 Y11 lQ IIO --U.Y9 ~Y8 PRnlW v OD1 ~ce M cc 11 111 r-----+--+--+-...... -...:;".19"18Q OD L.E 81' 18 64 X7 U }llt ~--+--+-~~-+-__16~?Q 7D ~1~?+--t -=1~X6 TC~ f-+...... -+-+--+...... _.a.1...'i6Q 6D 14 2 X5 L f-to-+-~-...__12~ 5Q SD 13 3 X4 t-+-+--+-...--~Q~ 40 18 4 XJ T Ace JL-ACC ...... -_6....JQ 3D17 15 X2 ...... --..~2Q 2D 46Xl I ...._ ...... 2 lQ ID 3 , XO eLK x S.Lx 7l.tl.S37J P L I E R ~ T DI 15M ~ r-t-r-rr-t-t--t------"-3'7~P26 C .SM H ...... ,.....~t-t------...l1~6p2? 1 TSl t-1--t--+-~~------~J 5'-1P26 14 o 33 1'25 ,.....-+-+-- ....o- ....~ P24 1 ....-+...... ~1'''4P2j GND~ t-t 'lI.i..l 1'22 11 o ...... ~;O~P21 J ~ ,....,.----t--r-;-t-+-+- ....&.19~ 8QIJ~ u 80 ...1..B ....2~9 1'20 ....-+ 1.-,6 ?Q 7D I? 28 P19 t-t-+--+-+-t __1...5 6Q 6D 14 27 P1a ...-.+-+--+-~_....111i.4~ SQ 5D 13 26 PI? ...... --+- ..-._9~ 4Q 41) B 2 a; 1'16 ...... -+- _Itt~)Q )I)~P1S(Y1S) ~ 2Q 2D r+--~14(Y14) ....-4-...... 1Q 1D ~P1)(Y1J) 7~LSJ7J Figure 4-15 The Pins Connection between The Multiplier And Data Bus 51 4.8 Modification and Testing Experiment on Heathkit ET-3400 for DMA Data Transfer Design The Heathkit 6800 system's layouts are fully buffered to protect the system, but it also prohibits some operation on the system. For example, when the HALT line is brought low, the VMA line is also brought low by the response of the CPU; this will disable all the memories in the system(7). In order to fulfill the design, some modification has to be made on the circuitry of the Heathkit 6800 system. Figure 4-16 shows the modification. It forces the memory enable signal to be active when the DMA controller takes over the control of the memory and system bus. Now, with the modification above, the design is ready for its applications. Before that, we would like to run the testing program to verify the results predicted in the design. Load the following program segment into the kit: $1000 Pl STAA $EFFO * CLEAR EQU $EFFO $1003 STAA $EFF) * ONESHT EQU $EFF) $1006 BAA Pl By running the simple loop, we can see the real timing relation of those control signals from a multi-channel scope. Appendix B shows the experi~ental results. They match the predicted results perfectly. +svs ~ To Pin 12, Ie 200 R4) IC4 on 8~ 6 I VMA.02 - cutx-off I 10 1'" From Pin) Ic6 5 rc I BA lett 174LS125 6800 CPU BA i74LS125 VMA ~l- _, BA I ~ Heathkit Layout R,IW ~ ~ I a WE i74LS125 BA HE ~- t74LS125 Figure 4-16 Modification Being Made on Heathkit Ul N ET-J400 to Fit DMA Block Data Transfer Chapter 5 DIGITAL FILTERING, AN APPLICATION OF A FAST LSI MULTIPLIER AND DMA TECHNIQUE 5.1 Digital Filtering As mentioned previously. many signal processing algorithms are nothing more than a string of sum of products. Among them, a digital filter is the nrototyne application of the LSI multi~lier. In general. the term 'digital filter' refers to any device which operates on an input number sequence to produce a second sequence of numbers by means of a computational algorithm. If the digital filter is part of a signal orocessing system, like that in Figure 5-1, the input number sequence is usually the digital version of an analog signal. The output sequence may be converted to the analog form if required. Two types of digital filter can be identified: nonrecursive and r e curs i ve filters(8). Nonrecursive Filter Input x(nT) and outout y(nT) are the excitation and response at instant nT, respectively. oc y(nT) = L: a. x(nT - iT) i=-.o ~ where ai are constants. By assuming causality, it can be shown that 53 x*(t) x(nT) Digital y(nT) ...... , r y (t) x(t) -rr S/H I' A/D r D/A Filter Clock Figure 5-1 Block Representation of A Digital Signal Processing System v' +- 55 and so 00 y(nT) =L a. x(nT - iT) i=O ~ If. in addition. x(nT) = 0 for n < 0 and ai = 0 for i ) N. n QC y(nT) = a. x(nT + a. x(nT L: ~ - iT) L: ~ - iT) i=O i=n+l N n = a. x(nT + a. x(nT iT) 2: ~ - iT) 2: ~ - i=O i=N+l N = a. x(nT iT) (5 .1) L: ~ - i=O Therefore, a linear, time-invariant, nonrecursive filter can be re?resented by an Nth-order linear difference equation. An example N=4 nonrecursive filter is 4 y(nT) = a. x(nT - iT) L ~ i=O Yo = a o Xo a + a X Yl = o xl 1 o a x .... a + a X Y2 = o 2 1 xl 2 o y a x + a x + a + a; X 3 = o 3 1 2 2 xl o where Yn = y(nT). xn = x(nT) n = 0,1,2,3,4,5 .••••••••• 56 Recursive Filters The response of a recursive filter is a function of elements in the excitation as well as the response sequence. In the case of a linear, time-invariant, causal filter ~o ~ yen!) = a i x(nT - iT) - 0i y(nT - iT) If instant nT is taken to be the present, the present response is a function of the present and past N values of the excitation as well as the past N values of the response. Equation (5.2) simplifies to Equation (5.1) if bi = 0, and the nonrecursive filter is a special case of the recursive one. 5.2 Elements of A Digital Filter The basic digital filter elements are the unit delay, the adder, and the multiplier. Their characterizations and symbols are given in Table 5-1. If the signals are sequences of binary numbers, the unit delay will be in the form of a shift register, whereas the adder and multiplier will be combinational or sequential networks comprising NAND or NOR gates. For purpose of digital signal processing, digi.tal filters can be characterized as performing functions that have a number of dt=lay elements and required several multiplications and addititons. The MPY-16 is optimally configured for these kinds of problems. The realizations of nonrecursive and recursive filters are shown in Figure 5-2. Table 5-1 57 Digital-filter Elements Symbol Equation Unit delay ~ • 0 y(nTJ = J«nT - T) x(nT) y(nT) x:("T) I( Adder y(nT) == r xt(nT) ~. 1 ~ o/ xk(nT) m 0 Multiplier y(nT). m.a:(nT) 0 • @ • 0 x(nT) y(nT) 5.3 A Simple Digital Filter As seen in Figure 5-1. a digital filter contains an analog-to-digital converter at its input and a digital-to-analog converter at its output. It can act directly on analog signals. A simple digital signal processing system based on the direct-memory-access feature of the 6800 micro-system and the MPY-16 is shown in Figure 5-3. An external clock is applied to enable the sample-and-hold device and acts as the IRQ (interrupt request) signal that switches the attention of the CPU to serve the digital signal processing in the interrupt service routine. The external clock can be as simple as a pulse generator and the frequency of the clock can be adjusted as required but it is subject to the limit of the maximum sampling rate of the system. (a) 58 aN (b) oT I Figure .5-2 The Realization of (a) N-th Order Nonrecursive Filter (b) 2nd Order Recursive Filter Data Bus '" Memory ~BYT/LBYT Start Bus Interface Analog Analog Input Output Data I/O IRQM • External Clock Address Address Bus Gates MPr-16 Cycle-Steal Request HALT r Priority Grant Sequence Control BAI DMA ., Timing J Controller 6800 System Figure 5-3 A Simple Digital Signal Processing Based on The 6800 V1 with DMA And The MPY-16 \.C An The processing flow of the simple digital filter system is shown in Figure 5-4. It depicts how the system software supports the external hardware to perform the digital signal processing. The circulating memory can be a parallel FIFO register but it also can be implemented in a memory queue by prograMMed instructions. The data manAgement program is constructed on the basis of the memory queue arrangement that is introduced in section 4.5. The memory queue can fit up to 8th order for the nonrecursive filter or 4th order for the recursive filter. The Xi (1= 0 to 8) operands are fetched from the output of the analog-to-digital converter: the Yi (i=O to 8) operands are loaded with the coefficients of the digital filter, where the Xis and Yi5 are the operands which are corresponding to the X and Y registers of the multiplier respectively. The data arrangement in the Queue follows the rules: ( N is the order of the filter) (I) For nonrecursive filter x. = x i 0 to 8 1 n-i = v , . .;- = a 4- 0 N, ~ -i i to .. N< 8 then v .: a . : 0 N< i ~ 8 . = 1 where ai are the coefficients in Equation (5.1). (II) For recursive filter x. 1 = xn-i i = 0 to N v a } -i = i Xi + 4 = Yn-i i 1 to N v = b -i+4 i } v v .;-¥:" .. . a . = = b. 0 for N<: is 4 -L.... N(4 1 = 1 -i+4- 1 = where 8i and bi are the coefficients in Equation (5.2). Digital Filter CIRCULATING Analog ~ D/A Analog AID j MULTIPLY Output Input MEMORY }-0- l J ". Delay Line Memory MPY-16 Coefficient Memory CIRCULATING l--J MEMORY Controlled ; Controlled • Data Management Controlled by • by , by · by , · External ·, Programmed ~ Software Program ... · DMA Controller Clock · Instruction Figure 5-4 The Processing Flow of A Simple Digital Filter System Q'\ ...... 62 The data management program. which is implemented to function like a shift register, executes the LDX and STX instructions until all the X- operands have been shifted one position (i.e. Xi ---) Xi+! for i=O to 7, discarding the previous Xa for a nonrecursive filter) and loads in a new data from the analog-to-digital converter into Xo. The operation is shown below: QUEUE Load from x n AI: STAA CLEAR ·RESET DMA & START QUEUE+2 a AID CONVERT o LDX QUEUE+28 QUEUE+4 ~-1 STX QUEUE+J2 QUEUE+6 LDX QUEUE+24 QUEUE+8 x 5TX QUEUE+28 n_ 2 WX QUEUE+20 QUEUE+I0 a 2 STX QUEUE+24 QUEUE+12 xn-J LDX QUEUE+16 QUEUE+14 a J STX QUEUE+20 QUEUE+16 x LDX QUEUE+12 n_ 4 QUEUE+18 STX QUEUE+16 a4 QUEUE+20 LDX QUElIE+8 xn-5 QUEUE+22 a· STX QUEUE+12 5 LDX QUEUE+4 QUEUE+24 xn _6 STX QUEUE+8 QUEUE+26 a6 LDX QUEUE QUEUE+28 ~-7 STX QUEUE+4 QUEUE+JO a LDX HBYT 7 QUEUE+J2 STX QUETJE ~-8 Discard QUEUE7J4 STAA ONESHT ·!~VCKE DYA TRANSFER as QUEUE+J6 P,H P.L ~ 63 The advantages for such a straight forward program structure are: (I) It consumes the least execution time for this particular application. (II) It can be changed into a recursive filter (up to 4th order) by replacing only one operand address. For a recursive filter the program and operation are shown below: QUEUE Load from AID xn QUEUE; 2 a STAA CLEAR *RESET DMA & START O AID CONVERT QUEUE+!;. LDX QUEUE+28 Xn-1 QUEUE+6 STX QUEUE+J2 a1 QUEUE+a LDX QUEUE+24 x n_ 2 STX QUEUE+28 QUEUE+10 a2 LOX QUEUE+20 QUEUE+12 ~·Xn-J STX QUEUE+24 QUEUE+14 a J LDX QUEUE+J6 +-- QUEUE+16 x STX QUEUE+20 n_4 Discard QUEUE+18 a LDX QUEUE+12 4 QUEUE+20 STX QUEUE+16 Yn-l LDX QUEUE+8 QUEUE+22 b1 STX QUEUE+12 QUEUE+24 Yn-2 QUEUE+4 LDX QUEUE+26 b 2 STX QUEUE+8 QUEUE+28 LDX QUEUE Yn-J QUEUE+;'O STX QUEUE+4 oJ QUEUE+)2 HBYT LDX Yn-4 Discard STX QUEUE QUEUE+)4 04- -1 STAA ONESHT *INVOKE DMA TRANSFER QUEUE+J6 mPL 64 5.4 A./D. D/A And SiR Devices Analog-to-Digital Converter The ADC-~X12Bx 12-bit, bipolar, -5V to SV analog-to-digital converter will be used for the digital filtering system. It supplies the 12-bit complemented 2's compleMent output in 20usec (the maxirnu~ conversion tiMe:). The 12-bit data will be taken for a 2-byte data during the filtering operation by putting O's into the least significnnt four bits while loading them into the memory. Since the 12 data bits of the converter are not tri-state outputs. 12 inverting tri-state buffers are needed to make it bus compatible. Some extra components are also needed for external adjustments of zero or offset and gain. Figure 5-5 describes the setup and the interfacing with the data bus. ~~ile the 6~OO system is running as a digital filter. the address decoding output of ST.~ CLEAR. which resets the D~~ controller, serves as the START CO~vERT signal of the analog-to-digital converter in its complemented state. It takes B8us to go through the data shifting operation before the LDX HEYT instruction, which enables the buffers and loads the digital outputs of the AID converter into the memory queue, is executed. The 88 microseconds are more than enough for the A/D converter to complete the data conversion. * By DATEL-INTERSIL, Inc. Also see Ap~endix e.l for detailed descrintions. ~}rl'I\H'I' - CONV~STU CLEAR +5V [-~~ ~ OC l'l ~J18 _IOUfl .15V • • OC 5V GND 14 9 1) 12-Bit LOX HBYT .•~----l .. . ' -- U . 1 .=:ill·_-1J.!L.--.--!.?. Analog 21 ~ • .11 01 G2 10K 12 11 To E22 To '/4LSJ68 lOOK to 10 Digital Converter 6-oAHALOG INPUT (-5V to .. 5V) 1?5 15V AOC HXI2B ., I J I I GND 10K 'VV'v I ~ 1'0 I I • • n b~_ lOOK -15V I 1- •• •• IX: J!4~ -+ .Oluf LOXf'HBYT =:5 1 S ar1 LOX LBYT~i2ti" . • I. 11 , us 6 74lS125 5 _ •J t -2. ~ 2 Figure 5-5 The Analog-to-Digital Converter And the Interfacing with Data Bus 0' L11 Digital-to-Analog Converter 66 The DAC-UP8BC* 8-bit, -5V to SV digital-to-analog converter with the 1 high impedence inputs and a level triggered 1 LOAD control allow it to interface directly to the data bus. Only a 7404 inverter is needed at the most significant bit input to convert the Z's complement data into offset binary to meet its data format. Figure 5-6 shows the setup, same as the AID converter, but some extra hardware components are needed for external adjustments of zero or offset and gain. The load control(LOAD) shares the T5M control signal with the MPY-16(see also Figure 4-12), only the high byte of the 16-bit output from the MPY-16 will be loaded into the converter. Although it suggests overkill, an 8-bit D/A converter is sufficient for demonstration. Sample-And-Hold The Figure 5-7 depicts how the sample-and-hold device (SID'1- I C-l ) * operates cooperatively with the external clock. The O.OluF hold capacitor gives an acquisition time of lOusec and a hold mode droop of 5mV/sec, so the width of the negative going external clock pulse must be at least lOusec long. The frequency of the external clock pulses are dependent on the sampling rate for which the digital filter is designed. The 74123 monostable multivibrator gives a 30msec debouncing tine that allowes the manual control to turn the digital filtering on * By DATEL-I~lERSIL,Inc. Also see Appendix C.2, C.3 for detailed description. Data Bus 1 22 DO I - 2 ~f-_~_M_P _ Dl I• I .1 3I W I rl--lQj ::: ±I_ 1OODp' ~ +J:OK ZERO I II JUNC. i 1N4148 IIillp' l ADJ. I 4 I R . - - 15V D2 II• .1-4 E 51< 19 • I · +15V G , I 0.1", ~ ~ DJ I .l2t I : 1 OACOUTPUT 5 8 BIT D4 I --I . 6 T DAC I SK E II 1-= D5 7 R ~"" D6 8 BIPOLAR PIN20 FOR BIPOLAR 15 OFFSET OPEN FOR UNIPOLAR D7 I 9 14 REF IN 7404 'rSM . 10 -,sLOAD GAIN ADJ. NC 11 10K 5K 4: Figure 5-6 The Digital-to-Analog Converter And the Interfacing with Data Bus ()\ --.1 + ';v +';IJ l (, 1K t-!-!Lr;' x t .rt. ~PST 2Q I~-- ~7412) SHM-IC-l Samplc-und-Hold . Vee [-~ u ~alog , l-t Output Analog --=-2 270n Input AI' I~ED J I lK lQ 12 ic L Vee -J- .OluF Vee -l- .: Jf=~O rogrammablel-t--~2D 2Q,9 ') ...To IRQ of CPU Pulse ----u- ~2!lt2CK 74LS125 Generator 174LS'l4 Figure 5-7 The Sample-And-Hold Device And The External Clock 0'co 69 and off by the SPST switch. The 74123's out?ut also triggers the 74L573 flip-flop to toggle the enable signal of the 74L5125 tri-state buffer, which allows the external clock to go through or to be gated from the S/H load control and the IRQ of the 6800 cpu. When the LED is lighted. it indicates that the system is running as a digital filter. The 74L574 D-type flip-flop synchronizes the external clock with the system clock ¢z; since the 6800 CPU requires that the transition of the IRQ signal can occur no later than 250nsec before the trailing edge of clock ¢2. 5.5 IRQ Configuration In the 6800 monitor of the Heathkit, the contents of IRQ vector (FFF8.FFF~) equal SOOF7(i.e. UIRQ EQU SOOF7). It has to be pre- configured before applying the interrupt feature to the digital filtering system. The simplest way to implement that is to load the cp-code of an unconditional jump instruction and its destination address into memory as follow: ORG $OCF7 UIRQ FU,lB J J:,:P EQU $7E ORG $0100 LDAA #4.lT!fJJ STAA $OOF7 LDX #INTADD STX $OOF8 whe re I~IT.A.DD is the starting address of the interrupt service routine. 70 Also, the memory queue which is involved in the DMA operation has to be initialized before entering the DMA mode. Following are the listings of the programs for both of the nonrecursive and recursive filters: 71 "6BSA~ IS THE PROPE!TY OF ~OTOROLA SPO, IWC. COPYRIGHT '97~ TO 1976 BY ~OTOROLA INC MOTOROLA ~6800 CROSS ASSE"BLEP, R!LEASE 1.3 00001 NA~ RSUER 00002 ••••• FIR FItTER PROGRArt *•••• ~0003 0200 O~G S0200 00004 0200 0026 QUEUE RfllIB 38 00005 EFF'O ClEAR lQU SErFO 00006 EFPl HBYT !QU S!FF1 00007 EFF3 ONESHT lQO JEFP) 00009 OO"! J!'!P !QU S7! 00009 0100 ORG S0100 00010 0100 q6 7E LOA A 'JPlP O~ 0'1 ('102 97 1'1 5T1 A $001"7 • CONFIGURE INTERRUPT (')0012 0'04 CE 0'10 LOX tP3 00013 0''11 D"P 1"8 STX soors } On01ij Q'O~ C6 OA LOA !3 'SOA 00015 i)'OB CE 0200 LDX iQOEUE 00016 Q10E 61' 00 P1 eta , x 00017 0110 6F 01 eLR 1,X 00019 0' 12 OB IMX 0001Q ()'13 OB INX • INITIALIZE MEMORY QUEUE OfJ020 ""4 08 I NX Q0021 1115 oa IN:( 00022 ~'16 SA DEC B (),J023 f)'1~ 26 FS 8M! P1 00024 O"q OE eLI OOJ25 o,,~ JE P2 Wll 1)0026 O"B 20 FD BRA P2 0002'7 n"D 87 EPFO ~3 STA A CL!AR 00028 0'20 FE 'J21C LOX QUEiJE+28 00029 0123 FF 0220 STX QOEtJE+J2 00030 ()'26 FE 0218 LDX QU!OE+21.& 00031 012Q P" 021C STX QD!OE+28 00032 012C FE \l21ij LOX QOEtJ!+20 00013 012? FF 11218 STX QUEOE+24 OOOJu 0132 F! ')210 LDX QUEUE+16 00035 0135 P!2' 021a STX QUEUE+20 0003& 0138 FE: 020C LDX QtJEtJE+12 00031 0118 Fro ~2'() STl QUEUE.16 00038 013E FE 0209 LOX QUEO!+8 ()003CJ 0141 FF 020C STX QU!!JE+12 OOO~O Q1164 FE 02~4 LOX QUEUP;+~ 00001 J1~1 ,~ 02J9 STX Q.UEUE+a 00042 O'~A FE 0200 LOX QUEOE O!)O~3 o14D PF 02,14 STX QU!U!+4 000414 0150 FE !F?1 lDX HBYT ~004 5 0153 'F' 02(l() STI Qu!ue 00046 0156 87 EFF3 stA A ORESRT 00041 * • • HALT • • )0048 RTI 00049 !ND S!~Bot T\BLE QUEUE 0200 CLE~R tFFO H8IT EFFl ONESRT Ery] J"P 001E P1 010E P2 011A P3 0110 ~OTOROLl ~68SA~ CROSS-ASS!Bt!R PAGE 72 ~n8SA~ IS THE PROPERTY OF !OTOaOLA SPD, INC. COPYRIGHT lq74 TO ,Q76 ay ~OTOROLA INC 00001 N~" HSUER f)0002 •.••** rIft PILTER PROGRAl1 *.*** 00003 0200 QRG $0200 00004 ozno 0026 QUEUE R!1B 38 00005 E~l'O CLEAR EQU SErpo 1()OQ6 EPP1 HBTT EQU SEFP1 00007 EF'P'l C'urSHT E~tl SEFr3 00008 001E Jf1P EQU $7E JOOQ3 <1100 ORG 30100 00010 J1 t)O 86 7E LDA A tJMP 0001' 0102 97 Fi 51'1 h $OOF7 ")0012 0104 CE 0110 LOX #p3 * CONFIGURE INTERRUPT 00013 0101 Of F8 STX $OOFS } 0101i.4 010Q Co OA LDA B .$OA 00015 010B CE 0200 LDX .QUEUE n0016 010e 6P 00 P1 CLR ,x 00017 o110 6F 0 1 eLY? 1,X ')n018 o1 12 08 INt f)00 1,9 0'13 03 INX * INITIALIZE MEMORY QUEUE ,}0020 0114 08 rMX .10021 J"5 08 INX 00022 0'16 SA DEC 3 00023 0'17 26 PS BNE P1 ':)'1') 24 (11 1 q OE eLI 0')025 O'1A 3"e p~ WAI JJ026 '1115 20 FD BRA P2 ',)'l02~ ~'10 B7 EFFO P3 STA A CLEAR J0028 1120 FE 021C LDX QU!UE+26 n;)02t? t) 12 3 P P 0 2 2 0 srr QUETJE+32 00030 0126 FE D'-1R LDX Q.U EU E+ 24 JO 03 1 0129 FF 021C STX QUEUE+28 0')Q32 012C FE 0214 LDX QOEUE+20 1)0033 012P FF fl2,Q srr QUEUE+24 "~()34 i1132 FE ~224 tDX QUEUE+36 ')0035 \'1l5 F~ 0214 STY QUEU!+20 nO()~6 0139 FE 020C LOX QtJEtJE+12 00037 0118 FF 0210 srx QOEUE+16 10038 013E FE 0208 LOX QrJEtJE+3 00 :J39 o1 Ll 1 FF 02 oc STX QUEUE+'2 00040 o,~q FE 020U LOX QUEOE"~ 00041 0147 Fl." 020a srx QUEUE+8 OOO~2 014~ Fe 0200 LOX QUEue 00043 014D P'r 0204 STX QcrEUE·~ 0004Li 0150 PE !FF1 Lor RBYT OOOLJ5 0153 FP 0200 STX QUEO-e 00046 0156 87 E1'F3 S't'A 1 OMESHT ()Q047 • • • HALT • * 00048 O'S9 3B BTI 00049 END S!!!80L TABLE QUEUE 0200 :LEAR EFFO HBfT EFF1 ON~SHT EPf3 J~P 007E Pl O'O! P2 0'11 P3 0110 Chapter 6 DATA FORMAT AND SIGNAL SCALING 6.1 Data Format The 2's complement fraction, fixed-point, binary data format is used to implement the digital filtering. The 2'8 complement representation of a number X is defined as for X ~ 0 for X < 0 Conversely, if x = X.X1 L-1X······L-2 X1X o then L X = -XL'" L i=l where XL is the sign bit, and L, referred to as the word length, is the number of bit locations in the register to the right of the binary point. For example, L • 15 If X = 0.010101 then x ~ L ... 1- = = 4 ... 16 64 0.)28125 73 74 and if X = 1.101011 then X = -1 + ~ + ~ + 12 + ~4 = -0. :328125 6.2 Scaling Factor For the registers of the A/D, D/A and the MPY-16 with a word length of L, the '2-L, is referred to as the scaling factor. (1) Analog-to-Digital Converter It is a 12-bit, bipolar. ±S volts nominal, 2's complement binary converter such that 11 Nhex) decimal v. = (N x 5 x [2- ] x 5 ~n h ex )decimal 2048 where [Z-l1] i s the scaling factor. For example: v. is positive v. is negative In l.n v. = volts v. volts l.n J·.5572 l.n =-J.5572 Ndecimal = 1457 Ndecimal = -1457 2's N 5Cl . N = A)F hex complement hex where Nhex will be the actual value being put into processin2. (2) Digital-to-Analog Converter It is an 8-bit offset binary input, ±5volts bipolar nominal output range converter. Since offset-binary code is the 2's-compleMent code with the sign bit reversed, the factor still follows Z-L as of 2's-complement binary: Vout = (Nhex,offset x 5 x [2-7]~eCimal - 5 75 where 2- 7 is the scaling factor. For example: = $)6 Nlhex,offset = CA Nhex, offset = 54 Ndecimal = 202 Ndecimal = volts V =-2.8906 volts Vout 2.8906 out where the N ff t will be the actual value being converted by D/A h ex,o se converter. 6.3 Signal Sca~ing During signal filtering: if the amplitude of any internal signal in a fixed-point implementation is allowed to exceed the dynamic range. overflow will occur and the output signal will be severely distorted. On the other hand, if all the signal amplitudes throughout the filter are unduly low, the filter will be operating ineffieiently and the signal-to-noise ratio will be poor. Therefore, for optimum filter perforMance suitable signal scaling must be employed to adjust the various signal levels. Furthermore, in fixed-point arithmetic: the numbers are usually assumed to be proper fractions like the outputs ot AID converter (or the inputs of the }~Y-16 X-register). But for a digitrtl filter being designed; the coefficents are not always in fractions. A pro~er scaling factor has to be applied to the Y-register of the ~Y-16 which holds the coefficients during the filtering processing_ 76 There are several ways to avoid the flaws of a fixed-point implementation. While designing the digital filter: (1) the gain of the digital filter is restricted to be equal or less than 1. A scaling amplifier can be included in the output section, as in Figure 6-1, if some other gains are desired. This will ensure the outputs and the feedback signals, y(nT) in Equation 5.1 and 5.2, stay in the fraction range and meet the data format of the MPY-16 and the D/A converter (2) find the proper scaling factor for the digital filter coefficients in order to fit the worst case of the design. By examining the characteristics of the prototype digital filter(9); the nonrecursive filter will have no problem to fit the design since its coefficients are never beyond the fraction range. But, for the recursive filter, the magnitude of the largest (absolute value) coefficient goes up as the order of the filter is increased. Fortunately, for a fourth order recursive filter which is the highest order recursive filter in this design, the coefficients are always smaller than 4(10). The scaling constants are usually chosen to be the nearest powers of 2 satisfying the overflow constraints. In this way scaling multiplications can be reduced to simple data shifts. The scaling for the Y-register of the MPY-16 which holds the coefficients is illustrated as follow: The Z's complement fraction, fixed-point, binary representation of a number Y in the Y-register is R 2 R1 I Digital r~;;~-- v. -.- S/H A/D I• v In -- Filter --r- o L I.-vvv It t v· H) == Hl II R2 R v ( 1 t -..£.) v : i o H 0 t Figure 6-1 Variable Gain Digital Filter ~ ".J 73 = -1 S Y < 1 where Y15 is the sign bit. The scale has to be adjusted to allow the Y-register to fit the data range of IYli4; then shift the binary point right of 2 bits position, in other words, shift the contents of the Y-register left twice: x2 x2 r i y = +~Y15-" 2- J x 2 ] x2 l(-1' Y15 i= ... ~ 15 .... 2 -it ...1 Jx rI -~.- 1 15 + Y14 + z: Y15-- • 2 ~ i=2 1 15 • 2-i+ 2 = 4 v + 2·Y14 .... 1 +~ Y -• "'1.5 13 i=) 15-i = Y1SY14Y1J'Y12Yl1 . . . . . Y1Y o 79 where -45.Y.(4 t Y15 is the sign bit. The data format of the Y register has been changed into mixed-number, 2's complement binary with the scaling factor of [2-1~; such as: Yhex) decimal 8192 For example: Fraction, 2's Mixed-number, 2's Y 0.75 0.110000000000000 000.1100000000000 --.J LJL..JLJ LJU'-lU $ 6 0 a 0 $ 1 800 Y =-0.625 1.011000000000000 111.0110000000000 LJUULJ 1---1I-lULJ $ BOO 0 $ E COO y 1.75 N/A 001.1100000000000 LJUULJ $ J 8 0 0 Y =-2.125 N/A 101.1110000000000 L-'\_/LJ'_' $ B COO Then, ths products of X and Y will be: 6 5 4 3 2 1 ,..-1 2 11 12 1) 14 15 25 26 27 28 2 2 2 2 2 2 2° G 2- 2- 2- 2- 2- 2- 2- 2- 2- 2- \~P1JC ~ ..-- XTP .AI MSP •• LSP '-- v 80 (3) As mentioned before, the data format of the AID converter output is 2's complement fixed-point fraction. As long as it is an unity gain filter; the digital filter output, y(nT), which is fetched from the output of the Multiplier should be in the same format as its input, x(nT), which is fetched from the output of the AID converter. So, the 16 bits (P1J to P2S) will be the product being outputted or fed back during the filtering processing. On the other hand, only the 8 most significant bits of the 16-bit output are loaded and converted by the D/A converter; and the MSB of the 8-bit output which is in the 2'8 complement fraction format has to be complemented to be consistent with the offset binary data format of the D/A converter. (4) The TDCIOIOJ LSI Multiplier is applied as the multiplier of the digital filter, the three additional most significant bits (P J4 , PJJ , Pj2) are provided to allow valid summation beyond that available for a signal multiplication product. With the scaling adjustment of Y-register, the most significant bit (P'34 ) of the product register is on the order of 26 which is more than enough to cover the worst case* and allows it to exceed the dynamic range during signal filtering. On the other hand, the constraint that only the unity gain filter is allowed, eliminates the possibility of output distortion. * It is assumed that all the values of X equal +1(-1), and all the values of Y equal +4(-4). Chapter 7 SOME REAL EXAMPLES OF DIGITAL FILTER 7.1 Maximum Sampling Rate In determining the bandwidth limits in the digital processing of analog signals, the first rule is that the highest frequency a sampling process can detect is one-half of the sampling rate, or alternatively, the sampling rate must be greater than twice the highest frequency which is to be present in the input. This minimum sampling rate is called the Nyquist frequency. The highest frequency that a digital filter can handle is subject to the hardware limits and the support software. Table 7-1 shows the way to derive the maximum sampling rate of the digital filter in this design. The time between two samples equals: 6 f ~ = l§O x 10 = 5.555 K Hz so, the highest frequency that the filter in this design can detect is 2.8K Hz approximately. 7.2 Digital Filter Examples This section will demonstrate the design's application as a digital filter by running several prototype digital filters(8,9) which have been available. The way to design a filter is not covered in this 81 82 Table 7-1 Mathod of The Maximum Samnling Rate Calculation # of cycles P2 ~J'JAI 9 GotTO .. BRA P2 4 9 uSES MONITOR PJ STAA CLEAR 5 .. ! LDX QUEUE+28 5 I' STX QUEUE+32 0 ~ LDX QPEUE+24 -I STX QUEUE+28 6 LDX Qi_iEUE+20 5 STX ~t;3UE+24 6 LDX QUEUE+16 (+36)5 STX QUEUE+20 6 LDX ;UEUE+12 5 STX QUEUE+16 6 LDX QUEUE+8 5 STX 1~:-:El}E+ 12 6 LDX QUEUE+4 5 I' STX :~UEUE+8 0 r" ("")n~PH' LDX ' STX QFEUE+4 6 r..:7:)V~ LJX .... STX ~~--;-'~ -' ST.":.~. ON~.sE= 5 * ?~OC~SSOR HALT FOR 39 uSEC.* RTI 10 * see Figure 7-1 .- V'Ji\1 Tn:;;t. -~l 04----- ...- ....------. ------...------.. ----.---.•--- ¢') L-'----U---l~ c: __ r--l__r-,___ r-1_ _1-- -L__ I--- -l_J--- - l __ J---1 I ADUHESS-- -) C~-~----- r~~;-p(X~ Ulf:) : Addt2 SP(n-6) SP(n-?) FFF8 FFF9 OOF? OOF9 DA'l'A --D I ----- BUS : ACCB CCR • IRQ \ « 10 us Synch w/~2) ;J ~ BA * See Sec. 5.5 & Sec. J.J Figure 7-1 Timing Diagram of WAI and IRQ at Optimum Response o: w 84 thesis. The input and output waveforms and the frequency response are provided: I. Recursive Filter: (1) IIR, Low-pass, 2nd order (8) i. Cut off frequency: 200 Hz ii. Sampling rate 2000 Hz iii. Transfer function: 1 2 y(z) 0.0674552 + O.lJ491z- + 0.0674552z- H(z)= 1 2 x(z) =------0:------1 - 1.14298z- + O.412801z- y(nT) = 0.0674552 x(nT) + 0.lJ491 x«n-l)T) +0.0674552 x«n-2)T) + 1.14298 y«(n-l)T) - 0.412801 y«n-2)T) iv. Coefficients in hexdecimal: decimal hexdecimal ao 0.0674552 $0229 0.1)491 $0451 a1 0.0674552 $0229 a 2 1.14298 $249J b1 b -0.412801 $F2CA 2 85 v. Amplitude response: Samnling frequency f s = 2000Hz Normalized frequency: 2f/fs =f/1000 o. co. N ~. 0.0 .1 .2 .J .4 .5 .6 .7 .8 .9 1.0 NORMALIZED FREQUENCY 86 vi. Input and output waveforms frequency: 100Hz 2V/DIV_ Input 11_111111_...... ~IIIIIIIIII 1111111111111111. II _111111111111 _111111_1111 Output: 1111;11111111- -- 2mS/DIV frequency: 500Hz 2V/DIV ~ Input _11- I, r.tll1.a~,.gnl _11111111_1111' 111111111111111111 1111111111_11 Output: 111111_1111 ' _~ ...__ _II.. • lmS/DIV frequency: 800Hz 2VIDIV Input _ l'lI~ ~II.I~ _r4III1I1~11 _1111- _11M 1111111111111111 _111111111111 1111111111111111 Output: ------1. . ------'2:n.S/DI - -_.. v (2) IIR. bandpass, 4th order (9) 87 i. Cut off frequency: 300 - 400 Hz (pass band) ii. Sampling rate 2000 Hz iii. Transfer function: 2 4 0.0200834 - 0.0401667z- + O.0200834z- H( z ) = ------~-----~----- 1- 1.63682z-1 + 2.23761z-2 - 1.30712z-J + o.641352z-4 y(nT)= 0.02008)4 x(nT) - 0.0401667 x«(n-2)T) + 0.02008)4 x«(n-4)T) + 1.63682 y«(n-l)T) - 2.23761 y«n-2)T) + 1.30712 y«(n-3)T) - 0.641352 y(n-4)T) iv. Coefficients in hexdecimal: decimal hexdecimal 0.02008J4 $00;"5 aO' a 4 0 a , a 0 1 J a ..... -0.0401667 $FE37 t:. 1.6J682 $)461 b1 b -2.2)761 $:8866 2 b_ 1.J0712 $29D4 ) -0.641352 $EB7A b4 8B v. Amplitude response: Sampling frequency f s = 2000Hz Normalized frequency: 2f/fs = f/1000 o. N ...... 0.0 .1 .2 .J .4 .5 .6 .7 .8 .9 1.0 NORMALIZED FREQUENCY 89 vi. Lnnut and output waveforms: frequency~ 350Hz Input Output: lmS/DIV frequency: 250Hz 2V/DIV Input Output: 2mS/DIV 90 (3) IIR, High-pass, 3rd order (8) i. Cut off frequency: 800 Hz ii. Sampling rate 2000 Hz iii. Transfer function: O.01809-0.05428z-1.0.05428z-2-0.01809z-J H{ z) = 1 + 1.76004z-1+1.18289z-2.0.27811Jz-J y(nT)=0.01809 x(nT)-O.05428 x«n-l)T)+0.05428 x((n-2)T) -0.01809 x((n-J)T)-1.76004 y«n-l)T)-1.18289· y«n-2)T)-O.27811J y«n-J)T) iv. Coefficients in hexdecimal: decimal hexdecimal $0094 a 0.01809 O -0.05428 $FE4J a1 0.05428 $01BD a 2 a -0.01809 $FF6C J $C7AE °1 -1.76004 -1.18289 $DA26 b 2 b -0.27811) $F71A J 91 v. Amplitude response: Sampling frequency f s = 2000Hz Normalized freauency: 2f/f s = f/1000 -s. 0\. co. ..... 0.0 .1 .2 .) .4 .5 .6 .7 .8 .9 1.0 NORMALIZED FREQUENCY 9L vi. Lnput and out pn t waveforms: frequency: 960 Hz 2V/DIV Input (square wave) Output: ,ms/DIV frequency: 700 Hz 2V/DIV - . 1I1I_1It]_lIrJ~ Input _nllll__1I1I1 tJlI.,l1l1rJlI 1111111111111111 Output: 11.11_11111111 !MiI!!IIlIiiiil ---- ,mS/DIV 93 II. Norrrecur s Lve Filter: (1) FIR. Low-pass. 6th order (8) i. Cut off f r equency r 125 Hz ii. Sampling rate 1000 Hz iii. Transfer f unc t Lon : ~(z)=o.075026J6.0.15915494z-1+0.22507908z-2+0.25z-J+ O.00507908z-4+0.15925494z-5+0.075026J6z-6 y(nT)=O.075026J6+0.15915494 x((n-l)T)+O.22507908 x(n-2)T) +0.25 x«n-])T)+O.2250790 8 x«n-4)T)+O.15915494. x«(n-5)T)+O.075026J6 x((n-6)T) iv. Coefficients in hexdecimal: decimal hexdecimal $0267 a6' a o 0.07502636 $0518 ac:.' a 0.15915494 ...I 1 0.22507908 ~07J4 a4' a 2 a 0.25 ~O800 3 94 v. ~~plitude response: Sampling frequency f s = 1000Hz Normalized frequency: 2f/fs = £/500 0.0 .1 .2 .9 95 vi. Input and output waveforms: frequency: SO Hz 2V/DIV I~-II.~ Input ---__IIBII 1I~~lIlIalili 1111111111111111 _11111111111 Output: 111111111••11111111 SmS/DIV frequency' J80 Hz 2V/DIV Input Outputt Sm5/DIV frequency I 460 Hz 2V!DIV 'j _l1l1l1ft Input "1"1111"'1"1"1E~E__III1_J 1111111111111111 1111111111111111 1111111111111111 Output I IIIIlIilllililII - I... 2mS/DIV 96 (2) FIR, Band-pass, 8th order (9) i. Cut off frequency: 400 - 600 Hz (pass band) ii. Sampling rate 2000 Hz iii. Transfer function: y(nT)=O.151J65-0.1871 x«(n-2)T)+O.2 x«(n-4)T)-O.1871. x«n-6)T)+O.151J65 x«n-8)T) iv. Coefficients in hexdecirnal: decimal hexdecimal $04D8 aO' as 0.151365 a 0 0 at' 7 a , -0.1871 $FAOJ 2 a6 a • 0 0 J as a4 0.2 $0666 'J] v. Amplitude response: Sampling frequency f s = 2000Hz ~ormalized frequency: 2f/fs = £/1000 o. N 0.0 .3 .5..7 1.0 NORMALIZED FREQUENCY 98 vi. Input and output waveforms: frequency: 450Hz Input output: frequency: 550 Hz Input output: yg frequency: 150 Hz 2V/DIV Input Output: 2mS!DIV frequency: 700 Hz 2V/DIV Input lIDS/DIV 100 . 7.3 Error and Accuracy Once the register length is a fixed-point implementation is assigned, the set of machine representable numbers is fixed. If the word length is L bits, any number consisting of b bits, where b>L, must be quantized. Obviously, if a number x is quantized, an error e will be introduced as e = x-Q(x) where Q(x) denotes the quantized value of x. The coefficient quantization and the product quantization are the two major error sources which may introduce the inaccuracy to the performance of a digital filter. The easiest way to estimate the output deviation is to compare the output waveform attenuation with the calculated value which is depicted in the amplitude response curve. As we can see the higher the order of the digital filter and the higher the sampling frequency to passband frequency ratio, the more accurate results it can achieve. Chapter 8 CONCLUSION AND SUGGESTIONS 8.1 Review Throughout the previous chapters, we presented how the external math chip, the LSI multiplier, upgrades the real time capabilities of microprocessors. As a result by applying the fast multiplier chips, perforMance in such fields as telephony, television, and sound reproduction will be greatly enhanced, and digital signal processing will assume the dominance in these areas once held by analog techniqnes. ~~en interfacing the chips to a microprocessor, careful analysis must be done beforehand to determine if the vast multiplying power can $uccessfully be utilized by the microprocessor. Interfacing a 200ns multiplier to a IMHz 6800, for instance, would be overkill, because the much slower speed of the 6800 means the multiplier can comnlete a multiplication long before the processor can return to get the result. For faster processing, the D~L~ technique has to be applied with the powerful multiplier. Although the DMA interfacing speeds up the processing, the trade-off will be extra hardware and much more complicated circuitry. We have Made the DMA handshaking logic as general as possible: which involved just few program oriented controls, processor interrupt and halt features. Most processors can interface the LSI multiplier with this DMA interfacing without making any major change, since the processor halt and interrupt features are provided by most of the 101 102 microprocessors. 8.2 Further Developments and Studies In the design's application as a digital filter, there are several explorations for further development to make the design more general and feasible: (1) In the DMA controller, the address generator (counter) and the word counter can be replaced by the programmable counters such as 74L8169. With the pre-load feature, we can configure the counters by software to adjust the size of the memory queue which the DMA is referred to. Of course, a programmable timer has to be applied to replace the manastable multivibrator which generates the time interval for the CPU halt. (2) Referring to Figure 4-14, the timing of related control signals in a DrL\ cycle is suitable to be stored into PROM or FIFO shift register and call them out by issuing proper address or as simple as clock them out. The complicated hardware of the DMA controller can be replaced by just few chips of PROH's or shift registers. (3) The scaling of the data format in the design is fixed to some scaling factor, but it can be changed to be more flexible by loading all the 32-bit product (or sum of products) of a 16 x 16 ~ulti?lication into memory and adjust the scaling to the proper factor by several shift instructions. The trade-off of flexibilitv is the increasing of execution cycle time during the digital filtering. 103 Additional improvements may require more hardware. We leave them as further studies such as: (1) Implement the data queue which holds the operands of the LSI multiplier by FIFO registers, such as Fairchild 9403 16 x 4 FIFOs. That eliminates the most tedious and time-consuming memory management program and the memory access delay. (2) The nonmaskable interrupt (or the highest priority interrupt) service routine can be configured as an automatic coefficient dump routine which loads the coefficients of the desired digital filter from a coefficient bank into the data queue. This may reduce the ti~e required to update the digital filter coefficients. (3) Interfacing one of the dedicated LSI digital signal processor(ll), such as Intel 2920 or k~erican Microsystems 52811 to the microprocessor may further enhance the digital signal processing abilities of the system. Overall, the design and discussions in this thesis are trying to emphasis how the LSI math chips expand the wide range applications of :nicroprocessors. Followed by memory and control hardware, they are more sophisticated and less expensive now. It no longer makes sense to use a more complicated algorithm than necessary, and in fact, the simple canonical algorithms are beginning to be attractive. LIST OF REFERENCE (1) Leventhal, L. 6800 Assembly Language Programming, Osborne & Associates, 1978 (2) Motorola's 6800 vs. Intel's 8080, short-course notes, Integrated Computer System, Inc., 1975 (3) Artwick, B. Microcomputer Interfacing~ Prentice-Hall, Inc., 1980 (4) M6800 Micrprocessor Programming Manual, Motorola Inc., (current edition) (5) The Computer Motorola Microcomputer Data Library, Series A, Motorola Inc., 1978 (6) The Bf.poLar Digital Integrated Cf.rcuLt s Data Book, Texas Instruments Inc., 1978 (7) Schematic Diagram for Heathkit ET-3400 Trainer, Heathkit-Zenith Inc., 1976 (8) Antonion, A. Digital Filters: Analysis And Design, McGraw-Hill Inc., 1979 (9) Stanley, W. Digital Signal Processing Reston PubLf.sbi.ng Co. Lnc ,, 1975 (10) Charalambous, C. t and M.!. Best Optimization Recursive Digital Filters with Finite Word Length. IEEE Trans. Acoust., speech, Signal Process •• December, 1974 (11) Blasco, R. V-MOS Chip Joins Microprocessor to Handle Signals in Real Time, Electronics, Aug , 30.1979 APPEI~DIX A Model: TDC1010J BIDIRECTIONAL PORT (YIN lSP 001 f'"ELOI\O UATA INI )(IN CLOCK x (,;LOCI( '( r The TOCtQl0J is a multifunction arithmetic unit j-~--i---'f--:t--I capable of performIng 16 X 16 bit multipjication and product accumulation. The numerical system can be I I I I I either two', comp4ement or unsigned magnitude. )( INPUT I I I AEGIST[R The output contents can be added to or subtracted I from the next product, or tne accumulate function I 1 can be dtsab'ed for multlplv only. Initia' data can be , I preloaded into the output register directly. Input and I .(8} I output registers are provided. ~~~~T..f..... ~ in I The TDC1010J is a unicue builc:ng block for digital $ .. 1 : Signal processing. oar ncutartv complex multipliers, fil· ter s. and F FTs. t~ ! FEATURES r--'--,~.....j~" i !I 35 I • 16 x 16 Bit Para"el Multip6ication 1 i f • Two's Complement or Unsigned Magnitude I I • Cootrouabte Addition or Subtraction in Output I Accumulator I I I i • 115 nsec Multlply.Accumulate Time: f I I ~~~~~I I • Accumulator Pre-Load C.Plbiiity I '/\.,.(_ "t4!J I I J 16 1 I • Oou~e or Singte Precision L __ _ :_...J..---.J .~ v • Round Control ,lDIRECTIONAl 'ORTS (XT' OUT.*"'5P OUT, '''ELOAO OArA ;~l • TTL Input and Output • Three Independent Three-State Output Controls P'N 1 • Dual In-Line Package IDENTlfllER X5 , 64 X7 XI 2 63 x. • Radiation Hard x. 3 62 xe )(3 • 61 X10 )(2 ~ 60 • Single Power Supply, +5 Volts X1 I 59 X12X" XO 7 58 X13 VO.PO 57 X1. • 3.5 Watts Power Consumption Y'.", •9 S6 X15 Y2,"2 '0 55 TSL Y3,"3 5. "NO Y..... '2" 53 SUB YS ... S 13 52 Ace VI,ltS '4 51 CLK X V,.", 15 50 CLK V 32301 GNO 16 .9 vee J 110 va,'" 17 48 TC V.,... 18 47 TSX V10.P'O 19 .6 PREL 'I'll."" 20 45 TSM V'2."" 21 .4 CL.~ P Y13,,.,3 22 43 p~ V1 ••,.,. 23 .2 P33 Y'6.P16 ,. ., P32 P1G )~ 40 P31 39 P30 :~~ ~~ 38 P29 P19 28 37 P28 L "20 :l~ 36 P27 P21 30 3!:» P2E . P2~ -]1 34 P25 __...fU.....l.L 33 P2~ TOP v lEW 0.800 r---: U.010----4 iuS lu6 ELECTRICAL CHARACTERISTICS absolute maximum ratings over operating temperature range -IJ.S 10 7.0 V I"put VOituIJ11 o to 5.5 V OutlJut voltaye o to 5.5 V Operattng temperature range TOC101OJ (T ambient) oOC to 70°C TOC101QJM (T case) -SSoC to 125°C Stor"uc temr>t:ro1turc ro1nljC -65°C to l:>o°e Lad temperature ( 10 secof1ds) 300°c Junction tempe'atur~ 17SoC recommended operating conditions TOC1010J I TDC101OJM ---J - -..----- UNIT MIN NOM MAX MIN-rNOMl-MAY r I SUpply voltage. Vee 4.75 5.0 5.25 4.5 S.U ! ~.~ V \ I 1 I ! ~19f'-,evel O~lput current, IOH -0.4 -VA I rnA ! 1 ! ( I I Law-level output current, lOL 4.0 i ~ 4.U LnA ---_. -"-- ._---- I t.-, .- C'o."pw.,. ",,""h. tttw (m...~'.cl at 1.~" ',,",uO 2G ao 11~t.: --_._ ... I 1 I Input relJ1uer setun time. 's hoee F,gure 9) ! 2S 30 j nscc I ! Inn~1 rCljluer hOltJ time. t (W~ F'CJure 9) 0 0 Il~UC H I I I I I I Opl'rulllllJ tpmo,crillurt! (T~rntJII:1l1 for TOC10tOJ. T for TOC1010JMI 0 "10 -~~ u(; CAJ 5U 12!.J I electrical characteristics over recommended temperature rnnqe (except as otherwise notect) TDC1010J TDC1010JM PARAMETER TEST CONDITIONS UNIT MIN NOM MAX MIN NOM MAX V'H HI I"-le",el Input voua Je 2.0 20 V V LIIIN' II'VI" 1111111 t "'1I1t.1l"~ 1L Uti U l~ V V ~ OH H l'Itl-It.:",cl ou t1>UI volliJlJe "cc " MIN. IOH -0.4 mA 24 2.7 24 'l."I V Low-Icve~ VOL ou1';>ut lIoltOJ'jC Vee" MIN. 'OL ;: 4.0 rnA 0.3 0.5 OJ a.s v t H,qh-II'\II'I II II IU I \,;urrellt "'0 ...1... li i Vee=MAX. v IH = 2.4 I!J Low-tevei Inpu t current V .. 0.4 -0.4 mA IlL Vee" MAX. 1L -u 4 I ClockS~lllljll I~vclln~ut current Vee" MAX. t H V'M • 2.4 75 75 ..A V .. 0.4 I u, Clocks: lOw level Input current vee" MAX. ,L -1.0 -1U mA 'CC Supp1v current Vee· MAX, (see F;gute 6) 680 900 Gao 10~0 rnA *NOTE. Clock P IS two eQUIvalent ctocx toacs. switching characteristics across Vee and temperature ranges {except as otherwise noted) TYp·· MAX PARAMETER I TEST CONDITIONS ~'OJ TOC1010JM UNIT! I Multlp1v-eccumUllte time. t I For timing. see Figure 9 115 MA 155 200 nsec input regine, clock to I outPYt register Clock r I I i Output o~l ..., I Load 1 . sec F Iyur~ 5 25 35 40 fl..,('(; to ! I I Three state outnut delay 40 T}':..l- .: c Output enaoie. tENA I Load 2. see F IYUI e 5 25 35 I OutQut olsable. t Loao 2. see FIgure S 25 35 40 OIS 1 I J **NOTE At VCC =5.0 V. T A • 2S0e 10] PRE-LOAD TRUTH TABLE PREL TSX TSM TSL XTP MSP I LSP 0 0 0 0 Q a Q 0 0 0 1 Q Q H,Z 0 0 1 0 Q HIZ U a 0 , 1 Q HiZ HiZ 0 1 0 0 Hll Q 0 0 1 0 1 HIZ Q HIZ 0 1 1 0 HIZ HIZ Q a 1 1 1 HIZ HiZ HIL 1 0 0 0 HIZ HIZ !-ill , 0 0 , HiZ HiZ PL 1 0 , 0 HIZ PL HIZ 1 0 , 1 H,Z PL PL 1 1 0 0 PL H,Z HIZ 1 1 0 1 PL HIZ PL 1 1 1 a PL PL HIL 1 1 I 1 1 PL PL PL : I ! I NUll: HI Z Ou i out huf fer s at hlqh irnoeuance (output dl~alJleu.) Q Output butters at low Impedance. Contents of output reqrster will be transferred to output prns. PL Output buffers at hl(.:Jh Impedance, or output disablud. Pre-Load Data (PO) supplied ex ternullv <.it output oms WIll he loaOed Into the output reqrs ter at the rising edu~ of Cl.K P. DATA FORMAT FOR INTEGER MAGNITUDE NOTATION 15 n ~ X 2 34 X'N = II INPUT 0 OUTPUT P e- ~ Pm- 2'1\ 1S 0 n v Y 2 YIN /I 0 X 1N 15 6 5 4 3 1 2 2 7 7 7 '}2 7 ,0 2'5 INPUT FORMAT Eill~_...... _...... _"",---,_...... XTP 34 2 233 r2 231 OUTPUT ~PPP FORMAT 34 33 32 31 -...._...... _...... -""-...... _...... ~ DATA FORMAT FOR 2s COMPLEMENT FRACTIONAL NOTATION (NOTE 1) 15 XIN :II -, - X, 5 + ! XN• 2-r; where X 15 IS the sign b't X SGN IN'UT 1S YIN = -1 • Y15 ... ! Y - 2-r; h Y . N were 15 IS the 5.gn bit YSGN 108 V IN 20 2-92-t02-1'2-122-132-142-15 IHftUT FORMAT 5f]~_...... __...... _...... _...... _....._..&.....a~ SIGN errs FOA MuLTIPLICATION ONLY (NOTE 2) ~ SIGN liT FOR MULTIPLICATION AND ACCUMULATION NOTE J I Format is shown using a 25 complement fractional notation. In this notation the location of the binary point signifying separation of the integer and fractional fields is just after the sign, between the sign and the next most significant bit for the multiplier inputs. This scheme is carried over to the output format, except that an extended significance to the inte ger field is provided (to extend the utility of the accumulator). Consistent with the input notation, the output binary point is located betweed the P and P bit positions (for the 29 JO nonaccumulate mode). For the accumulate mode the binary piont position is the same between the P29 and PJo bit positions. It is arbitrary where the binary point is considered located as long as one is consistent with both input and output formats. One can consider the number field entirely integer, i. e , , with the binary point just to the right of the least signifi- cant bit for input, product, and accumulated sum. When nonaccumulating, all first four bits (P to PJ4) will indicate the sign of the product. J 1 The P30 term will also indicate the sign except for the one exceptional case when multiplying -1 * -1. Note that. with the additional significant bits available on this multiplier, -1 * -1 is a valid operation yielding a +1 product. NOT~ J: 7here is no change in the format whether one is ~ccumulating the sum of products or simply doing single products. However, the three additional most significant bits are provided to allow valid summation beyond that available for a single multiplication product. For further clarification, no difference exists between this cr-gani.aat i on and one which would have the product accumulation off-chip in a separate )4 bit wide adder. Taking the sign at the mast significant bit position guarantees that the largest number field will be used. In operation the sign will be extended into the lesser significant hi t positions when the accumulated sum only occupies a right hand portion of the accurnula1:or. As an example, when the sum only cc- :~pi~s tne least three bit positions then the sign will be extended througn the J1 ~ost significant posi t Lons . lU~ OPERATION DESCRIPrION Data Input (Xo to XIS and Yo to Y1S) X and Y are le~st significant bits and X and Y15 are most significant bits. Data inputs are loaded J J 15 into the X register and Y register at the rising edge of eLK x and CLK Y, respectively. Note: the LSP (PO to P outputs are time-shared with the Y data inputs (Yo to Y 1S) 1S)' :)ata (P ?J4) Output J to ?~ is the least significant bit and PJ4 is the most significant bit. The product is divided into Least (LSP: Po PIS)' (MSP: P P)l) Signi.ticant Product to Most Significant Product I 6 to and Extended Product (XT?, PJ 2 to PJ4). The product generated is loaded into the outputs registers at the ri3ing edge of eLK P. ?re-i..oad Data (PDo to PD J4) Jata applied externally to output pins, to initialize output register to a register to a given'value at the rising edge of eLK P. PD a to PD J4 are prOVided to output pins Pa to PJ4 respectively, where PDQ is ~east significant bit and PD J4 is the most significant bit. Two's :omplement Control (TC) When TC is high, the inputs are I6-bit two's complement numbers. When TC is low the inputs are 16-bit 'msigned magnitude numbers. The TC signal is loaded into the TC register at the rising edge of either eLK x or CLK Y. The TC signal must be valid over the same period that the input data is valid. Round Control (RND) Nhen RND is high, a "1" is added to the most significant bit of the LSP in the multiplier array (PIS) to ::-ound up the product in MSP and XTP rather than truncate it. The RND signal is loaded into the RND ::-egister at the rising edge of either CIK X or eLK Y. The RND signal must be valid over the same period that the input data is valid. A:c~~ulation Control (ACC) When ACC is high, the contents of the output regis~ers are added to the next product generated and their sum is stored back into the output registers at the rising edge of the next eLK P. When ACC is low, :nultiplication without accumulation is performed and the next produc t genera'tediiill be stored into :he output registers directly. The ACC signal is loaded into the ACC register at the rising edge of either eLK x or eLK Y. The ACC signal must be valid over the same period that the input data is valid. S~btrac~ion Control (SUB) When ACC and SUB are both high, the contents of the output register are subtracted from the next pro duct generated and the difference is stored back into the output registers at the rising edge of the next CLK P. When AGC is high and SUB is low, addition is performed instead of auotr-ac t i cn . The SUB signal is loaded into the SUB register at the rising edge of either CLK X or CLK Y. The SUB signal ~ust be valid over the same period that the input data is valid. Pre-Load Control (PREL) All output buffers are at high impedance (output disabled) when PREL is high. When 1'SL, TSM, or TSX are also high, the initial contents of their corresponding output register can be pre-set to the Pre Load Data (PD to PD applied to the output pints at the rising edge of eLK P. If TSL, TSM or TSX o J4) is low while PREL is high, the contents of the respective output register remain unchanged while the output drivers remain at high impedance. Three State Least, Most and Extended Control (TSL, T5M, TSX) The :S?, VS? or XTP output buffers are at high impedance (output disabled) when TSL, TSM or TSX is high, respectively. These are direct, non-registered control signals. The output drivers are enabled when TSL, TSM. or TSX are low, and PREL is low. TIMING DIAGRAM OF DMA CONTROL SIGNALS One DMA Cycle .~ .f=':-r~T~TTT-l .: L .,.,. I • • I CKl - ==",""",,,,"","m••__l',",,,,",=•••'"'"""~tm1 r-- ·'l ••••••••• • UlllUIlIlIllmllllllllllUIII X-CK "11I11.·lllIrtlii·~'I. Y-CK ,m[ftlillmlllmtllil••••••._.....• One DMA Cycle CK2 X-CK Y-CK P-CK 110 ,APPENDIX C.1 51I:UUEL ADC-~X12B 12-BIT AID CONVERTER ~ SYSTEMS, INC. -.sv .., OUT :;:,~ ,.1-....---- :,~:.~14 13)o------~ =.14 2'J-o-.....~.....-----... SHO'" •• C'fCU CLOCK CLOCK n ...' t, tt '. ••,••• J l , T ...... " ...... our ~w ,...... , ':'t ~M_UL eMf. our 1. It is recomm~ed that the t15V pow.- input 4. Short cycled operation results in shorter conver· pins both be by~ 10 ground with •.O'~F sion times where the conversion can be truncated ceramic cape;itor in PM"allel with. 1"F etectro to ,.. than 12 bits. This is done bV connecting lytic capKitor and the +5V pow. input pin be pin 14 to the output bit following the 'ut bit bvPMMd to ground with a 10"F electrolytic delired. For eampl. for an 8 bit conversion. pin QlPaCitor 8S shown in the connection diagrams. In 14 is connected to bit 9 output. Maximum con addition, pin 27 should be bypassed to ground version times are given for short-eycled conver· with a .01uF ceramic capacitor. These pre· sions of 8 or 10 bits. In these two cases the cloc k cautions will _sure noise fr.. operation of the rat8 is .Iso speeded up by connecting the clock conwrter. rate adjust (pin 17) to +5V (10 bits) or +15V (8 2. Digital Convnon (pin 1St and Ana'og Common bits). The clock rate should not be arbitrarily (pin 26) .. not connected together int_nally, speeded up to exceed the maximum conversion and th••for. must be connected as directly' as rate at a given reso.ution, however, or milling pOSSible externally. It is recommended that a codes will 'ault. ground plane be run undern.th the case bet.ween 5. Note that outpUt coding il complementary cod· the two commons. Analog ground and t 15V ing. For unipolar operation it is complementary power ground shou'd be run to pin 26 wher..s binary and for bipO"r operation it is compte digita' ground and +5V gtound should be run to mentary offset binary or comptementary 2', com· pin 16. plement. In c..s where bipolar coding of offset binary or comp'ement is required, this Qn be 3. Ext..na' adjustment of zero or offset and glin .re 2'. Khieved by inwning the .nalog input to the con provided for by trimming pOtentiometer. con (using ., op amp connected for gain of nected as shown in the connection diagrams. The wner potentiometer values can be between 10K end -1 .0000). The converter is then calibrated so that ooסס FS analog input gives .. output code of- ,ooסס ooסס lOOK ohms and should be 100ppmrC cermet types (such. Oat.'nt..."-. TP .ries). The lid· and +FS-1 LSB gives 1111 1111 justment range is to.2% of FSR for zero or offset 1111. and to.3% for gain. The trimming pOts should be. located .. close • possible to the convwter to avoid noiN pickup. tn some cases. for example 8 bit short-eycled operation, extern.' "just".nt may not be necessary. III 112 INPUTS ADC-ttX128 I ADC·HZ128 A~ 'nput R u...... • ••••••• o 10 +5V, 0 to +10V FS An.'ot'nPUt R Ia.a. . t2.5V. t6V. t10V FS 'nputl~ ••••••••••••••.•• 2.51< (0 to +5V. t2.5V) II( (0 to .,OV, t6V) 10K h1OV) ',.ut ...... with Buff. • •••••••• lQOMegah... Input 8iasCu".t of BuH. . . 125nA tYP., 250nA max. 'nput Ov-.olt_ ..•...... •...... t15V ~~ . 2V min. to 6.&V mea. PGlitive pul. with • ... tion of 10Qn1ec. min. Ai.... flit• ...... <3OftIIC. Logic ,., .. to "0" transi"on resets conver'er and in.tIat..next conversion. Loeding: 1 TTL loed ----.------J~------.-_t OUTPUTS' , ...... Ou...tDau .•...•.••....••• 12 ...... I.... of ••MId UIItii nut ....-.icIn camftWld. VOUT (Ua') < +O.4V VOUT C",.. ) .. +2.4V Codi,., unipo" CompHtmemwv Binary Codi... bipo&a, CompIementaIV Offtet B"*v CompMment.., Two', Complement Sew.IOuqaut Data •.••••••••••••••• HRZ -..CCIIIiw dectsion put..aut. MS8 fim. CampI. Bi,." or Compl. Offset Binary Cading End of Con.,.'Mon (Status) ••••••••••• Conv.sion ltatus sitNi. OutPUt illogic "1" during...-t and conversion wid 'ogic "0" when conversion comp"te. ClockOu~1 Train of politi. goinv +5V 100nsec. pU'aes. 600 kHz for ADC·HX12B and 1.5MHz for ADC·HZ12B (pin 17 grounded). I '~:.::~~~ . 12 bitS (1 pan in 4(96) Nonlinearity ..••••••••••..••••• t1/2 LSB max. Diff....ntia. Nontm..itv ..••..•...• t 1/2 LSB max. G••n Error, befo -iv-meat . tQ.1" Z.ro Error. unipol., before adj. . •••••• t.05" of FSR J Offset err•• bipoaar, bet..ad" ...... to.'" of FIR' Telftp. Coeff. of Gain .•••••••••••• t2QppmrC max. T..... CoeH. of Zero. uftipo" .•..... t5ppmfC of FSR mex. J Temp. CoeH. of Off..t. bipo.... ••••••• t10ppmrC of FSR max. J I Diff. NonlinearitY Tempco. ••••.•.• • • t2ppmfC of FSR ' I NoM~CodeI .•..••••••••••• av. oper. temp. range J . Con.,.,'" Time , 12 bits ...... • 20 "NC. max. I 8.0 ,,184:. mix. \ 10 bits· ..••...•.. 15~. max. 6.0~. max. I Ibi.· . 10 "sec. max. 4.0 "sec. rNX. I Buffer Senti", Time. 10V __ •.•••••• 3.0~. to .01" Power Supplv Rejection ••••••••••• .002'(, J" SuPP'y max. JOTES: 1. AU d.gic.' outPuu CIft driw 2 TTL loads. 2. WithOut b~t. amQtitier usad. ADC..J04Z128mey require ext""" adiustment of dock rite. 3. FSR iI ""1 scaNt...... il10V for 0 to +1OV !':&V ...., ....20V tot %lOV input. I SHORT CYCLE OPERATION I CONNECTIONS I, 10•• 12 BIT CONVERSION I ~ RESOLUTION '2 BITS 1081TS 8 BITS 01' 17 ·&V , AOC·HX12B CONV. TIME 20 "sec. 15 "sec. 10 "sec.. 0 CLOCK HATE ..... ·,!tv AOC·HZ12B CONV. TIME 8"sec. 6 "sec. 4 ~1eC • CONNECT THESE 17 Ii 15 17 16 & I SttQfcT & 17 28 I CYCLE -.....-.- PINS TOGETHER 14616 146 :2 '.6. 1 r-"--- TO Sfl.ECTELJ PIN 14 CONNECTION iI OAT A OUTPUT 1"'" RES. (BITS) CLOCK RATE VS. VOLTAGE PIN 14 TO RES. (BITSt PIN 14 TO 1 PIN 11 7 PIN 5 I PIN '7 CLOCK RATE 2 P.N 10 8 PIN 4 3 PINg 9 PIN 3 VOLTAGE AOC·HX128 ADC·HZ128 4 PINS 10 PIN 2 I OV 600 kHz 1.5MHz 5 PIN 7 11 PIN 1 +5V 720kHz 1.8MHz 6 PIN6 12 PIN 16 I +-15V 880 kHz 2.2MHz 113 INPUT CONNECTIONS INPUT WITHOUTBUFFER WITH BUFFER VOLT. INPUT CONNECT THESE INPUT CONNECT THESE RANGE PIN PINS TOGETHER "IN PINS TOGETHER OTO+5V 24 22&25 23 & 26 30 22 & 25 23& 26 29& 24 oTO +10V 24 - 23&26 30 - 23&26 29& 24 ±2.5V 24 22 &25 23&22 30 22& 25 23& 22 29& 24 %IV 24 - 23.22 30 - 23&22 29.24 ±10V 25 - 23&22 30 - 23 &22 29& 25 CALIBRATION PROCEDURE 1. Connect conwrter 8S shown in the StarnMrd ConMCtion di...,ams. Use the CALIBRATION TABLE Input Connection Tlble for the desired input voltage r..,ge and inpUt ~tion Impedance. Apply $t.-1 Convert pu'.. of 100 MIC. minimum to pin UNIPOLAR RANGE ADJUST. INPUT VOLTAGE 21. The ..-:ing of ,he should be no ._ NIl the .,.x;mum canveraaon PY'. ZERO +0.6 mV tame. OTO+5V GAIN +4I.9982V 2. Z.o and Off... Adjust...... ZERO +1.2mV OTO +10V ~y a precision YO'~ reference source between the ..1ecUId~ input GAIN +9.9963V and ground. Adjust the outpu ()f the r.f..... IOUfC8 to mevalue snown in BIPOLAR RANGE the Cahbration Te»" for the unipolar z.o adjustment (z.,o +~ L.SB) or the OFFSET -2.4994V biPO" offset adjustmer,. (-FS+~ L.58)' Adiust the trlmmino potentiometer $0 t2.5V GAIN ...2.4982V that the output code flicke" ttq"aUy between 1111 1111 1111 and 1111 1111 OFFSET -4.9988V 11 10. t5V GAIN +4.9963V ~ 3. FuU Adjustment OFFSET -9.9976V t10V Change tne outQl.lt of the pr.,..sion voltage reference source to the va'ue shown GAIN +9.9927V in the Calibration Tab1e for the un'pOlar or blpoa. ptn .diustrnent (+FS-1 % LSSL Adjust the gII'n trimmi", POt...tiometer 10 that the outPUt .ooסס ooסס ooסס oo 0001 andסס ooסס code flickers equallv between CLOCK RATE ADJUSTMENT +5V +15V o-....---..<.2K 17O-.....---_c 5K CLOCK RATE: CL.OCK RATE: 600 kHz to 720 kHz (ADC·HX128) 800 kHz to 880 kHz (AOC·HX128t - 1.5 TO 1.8 MHz (AOC-HZ12B) 1.5 TO 2.2 MHz (ADC·HZ128. 114 TIMING DIAGRAM FOR ADC·HX12B. ADC·HZ12B OUTPUT: 010101010101 EOC .------T, ------_ I I r----o f ,IT 12 I I~'" liT.....1 ••T 1 I" 3 "'17 fL'" INPUT/OUTPUT CONNECTIONS .... FUNCTION PeN FUNCTION TIMING DIAGRAM 1 BIT 12 OUT eLS'. 17 CLOCK RATE OPERATING PERIODS 2 BtT 11 OUT 18 REF. OUT 3 BIT 10 OUT CLOCK OUT ADC-HX12B ADC·HZ12B 4 81TlOUT 20" E.O.C. (STATUS) S I.TIOUT 21 START CONVERT 20 #£sec. 8.0 IAsec. G BIT 1 OUT n COMI'AR. INPUT 1.56 IJsec. 0.56 IAsec. '7 BIT 6 OUT 23 .'POLAR OFFSeT 8 In SOUT 1. 10V.NI'tJT 9 In 4 OUT 2iS 20V INftUT 10 Itt 3 OUT 26 ....ALOG COM 11 Bn lOUT '17 GAIN ADJUST 12 liT 1 OUT eMS•• 21 ·'SV'OWEM 13 lIT 1 OUT tiKI) 29 BUFFER OUTPUT '4 SHORT CYCLE 3D ttuFFER INPUT t!» DIGITAL COM. 31 'SV POWER '6 +ftV POWER 32 SER.AL OUTPUT BIPOLAR OPERATION COMPo COMP. TWO'S INPUT VOLTAGI RANGE OFFSET BINARY COMPLEMENT t10V t5V t2.5V MS8 LIB MSa LSB +9.9951 V .4.9976V +2.4988V 0000 0000 0000 1000 0000 0000 +7.5000 +3.7500 +1.8750 0001 ,,,, 1111 1001 1111 1111 +5.0000 +2.5000 +1.2500 0011 1111 1111 1011 1111 1111 0.0000 0.0000 0.0000 0111 1111 ,',1 ',11 1111 1111 -5.0000 -2.5000 -1,2500 1011 1111 1111 0011 1111 ,," -7.5000 -3.7500 -1.8750 1101 ,',1 1," 0101 t1', 1111 -8.9951 .....9976 -2.4988 ,',1 ',11 1110 01' , , 111 '110 -10.0000 -6.0000 -2.5000 ',1, 1111 111' 011' ,',1 1111 APPENDIX C.2 DAC-UP8BC 8-BIT D/A CONVERTER ~I:UUEL 8-BIT MONOUTHIC OAC ~ SYSTEMS, INC. WITH INPUT REGISTER MAXIMUM RATINGS PERFORMANCE Positive Supply, pin 19 . + 18V Linearity Error . : Y'l LSB max. Negative Supply, pin 17 . -18V Differential Lin••rity Error . : 1,7 LSB max. Digital Input Voltage, pins2-10. • 18V Monotonicity . 8 Bits over oper. temp. Reference Input, pin 14 . ...12V range Summing Junction, pin 20 . ... 12V Gain Error . Adjustable to zero Zero Error . Adjustable to zero Gain Tempco . 20 ppmJ·C INPUTS Zero Tempco, Unipolar . 5 ppmJ·C of FS. Resolution . a bits Otlset Tempco. Bipolar . 10 ppm/·C of FS. Coding, unipolar output. . Straight Binary Reference Tempco . 60 ppml·C Coding, bipolar output . Offset Binary Settling Time to 1,i2 LSBI . 2IJ.sec Input Logic Leve'. bitON ("1" .. ... 2.0V to .5.5V @ 10 IJA Power Supply Rejection . :1mVN Input Logic Level. bitOFF("O"). OV to .O.8V (jl - 5Os,lA Load Input . HI ("1") • Hold Data LO ("0") = Transfer Data POWER REQUIREMENT Load Pul.e Width I ••••••••••• 200 nsec min. Rated Power Supply Voltage .. % 15V DC Reference Input Voltage . ... 5V: 10% Power Supply Voltage Range .. : 12 to : revDC Reference Input Resistance . 5K Supply Current, quiescent.... +7mA, -10mA Refefence Input SaewRate . 25V/IlSec. PHYSICAL-ENVIRONMENTAL OUTPUT Operating Temperatur. Range. O·C to + 70·C (Be) Output Voltage Range. unipolar oto .10V 55·C to .125·C (8M) Output Voltage Range, bipolar. :5V Storage Temperature Range . - 65·C to +lSO·C Output Current . SmA Package Type . 22 pin plastic (8C) Output Resistance . Sohms 22 pin ceramic (8M) Reference Output Voltage . ... SV :t 10% R.f.r.nce Output Current . SmA NOTES: 1. See Timing Diagram 2. For 10V change 115 116 'NPUT/OUTPUT CONNECTIONS PIN FUNCTION PIN FUNCTION 1. It is recommended that the =15V power 1 OIGITAL'GNO 12 REF AOJ Input pins bOthbe bypaasedtoground with 2 BIT 8 IN (LSS) 13 REF OUT 0.1JJfceramic capacitors. This precaution 3 BIT 71N 14 REF IN will assure noise free operation of the con 4 BIT61N 15 BIPOLAR OFFSET verter. 5 BIT51N 16 OAC COMP 6 BIT41N 17 -15V 7 B.T 31N 18 OUTPUT 2. 80th the Output (pin 18) and Reference 8 BIT 2 IN 19 + 15V Output (pin 13) are short circuit protected. 9 BIT 1 IN (MSB) 20 SUM JUNCTION Output short circuit current is typically 40 10 i15Al5 21 AMP COMP mA for the Output and 15 mA for the Refer 11 NC 22 ANALOG GNO ence Output. 3. The "LOAD" control pin .s • level triggered input which causes the register to h~d data with a logic II'" input state and trans fer data to the OAe with a logic "0" input. COOING TABLE 4. A setup Time of 200 nsec. minimum must INPUT CODE OUTPUT RANGES be allowed for the input data before the MSB LSB o to + 10V %5V LOAD input goes from LO to HI. In addition, 1 1 1 1 1 1 1 1 + 9.961V + 4.961V a 50 nsec. minimum Hold Time must be 1 1 1 0 0 0 0 0 + 8.750 + 3.750 allowed for the input data after the LOAD 1 1 0 0 0 0 0 0 + 7.500 + 2.500 input goes from LO 'to HI. The minimum 1 0 0 0 0 0 0 0 + 5.000 0.000 pulse width for the LOAD input is 200 nsec. 0 1 0 0 0 0 0 0 + 2.500 -2.500 The maximum update rate is determined 0 0 0 0 0 0 0 1 + 0.039 - 4.961 by the output settling time. See Timing 0 0 0 0 0 0 0 0 0.000 - 5.000 Diagram. 5. The output settling time may be decreased somewhat by decreasing the value of the 50 pF feedback capacitor from the ampli fier Output (pin 18) to the Summing Junc tion (pin 20). The minimum capacitance value is 10 pF. 6. The gain temperature coefficient of the DAC-UPBB without the internal reference is 20 ppm/·C. By using the internal refer CALI8RAnON PROCEDURE ence, which has a tempco of 60 ppm/·C, a 1. Select the desired output range and co"nect as shown in total tempco of 80 ppm typical results for OUTPUT RANGE SELECTION tab'e. the converter. If greater temperature 2. Apply a logic "0" to LOAD (pin 10). stability is required, a more stable exter na' reference should be used. 3. Zero and Oftset Adjuatmenta For unipolar operation,s.' aUdigital inputs to "0" and adjust ZERO ADJ tor zero output voltage. Fot bipolar operation, set 7. The data inputs (Bits 1 through 8) are high aU digital inputs to "0·' and adjust ZERO ADJ for negative full impedance inputs which give minimal log scale yottaoe. of - 5.000V. ic loading. For an input LO, the current 4. G.in Adjustment that must be sinked is only 50 lolA maxi For eith.r unipolar or bipolar operation, set aUdigital inputs mum, or about 1132 of a standard TTL load. to "1" and ad;ust FULL SCALE AOJ for tne positive fun scale This minimizes the loading of the DAC vottage of + 9.961V (unipolar) or + 4.981V (bipolar). UPSB on a data bus. OUTPUT RANGE SELECTION MODe RANGE CONNECTION Unipolar Oto ~10V Pin 15 open BipOI.r *5V Pin 15 to 20 117 Hotd Transf. I-60 nMC. min. I I_T....' \'------ VOLTAGE OUT INTERFACING TOa 8'T DATA IUS OAC·UP88 81t. U.S8) 8n 7 R 8lte e 8-8IT 8U 5 G I DATA 8it 4 S 81t3 T BUS ~-_.....' 81t 2 e ---_.. R an1 (MS81 This illustrates the connection for loading parane' data into the Input register. The register circuit is a static latch and is controlled by the Q5AD. ae tive low. When the data is stable on the APPUCATIONS data inputs(bitl 1-8), It 4fM be transferred Procell and Control on the poaiUve edge of the ClSAi5 pul.e. Measuring 'nstruments The VOltageleve's on the data bus should TMt Equipment be stab'. for at I••st 200 nsec before Programmable Power SuppUes ~ fOAoHI. The minimum pulse width Computer UO Equipment of the command jl 200 nsec. APPENDIX C.3 SHM-IC-l SiR DEVICE ~cm-EL INTEGRATm CIRCUIT SAMPLE AND HOLD ~ SYSTEMS, INC. • 5~sec. Acquisition to .01% ~ 50 nsec. A_ture • Inverti", or Noninverting • ZMHz BAndwidth • .01% Feedthrough • 14 Pin D' P Pileage GENERAL SPECI FICATIONS. SAMPLE & HOLD, G • +1 Input Voltag_ Range ·. ·.·.·. · . · . ·. ·. tl0V min. Input Impedance . . . · . ·. ·. · . · . ·.·. ... 10"ohms Output Va'tage Range · . ·. ·.·.. . .. ·.. tl0V min. Output Current, S.C. protected ·. ·.. .. t10mA min. Output Impedance .. · . .. . . ·. · . · .. ·. 0.2 ohm Aperture Oelay ...... ·. ·. ·. ·. ·. · ... ·. 50 nsec. Aperture Uncenainty ••• · . ·. ·. ·. ·...... 5 nsec. Gain error, sampling mode · ... ·. .. .01% max. Hold Mode Noise . . · . ·. ·. ·.· . · ... ·. ·. ·... 3501JV RMS Digital 'nput, Sample Mode, DTL/TTL · . ·. .. oto +O.8V O-G.8mA Hold Mode, DTLITTL' • ·. ·..... +2.0 to +5.5V SAMPLe It HOLD, G • +1, CH • .01IJF Acquisition Time, 10V to O.1" ·. ·. ·. · . ·. ·. 10 ~sec. Acquisition Time, 10V to .01% .. .. ·...... 121-1HC. Bandwidth, sma" signal, sampling. ·. ·.·....·. 1.0MHz Slew Rate ...... ·.·.·. ·. ·.·.. 3VIP. sec. Hold Mode VoJtage Droop •• .. · . ·. ·. ·.. ·.. 5mV/sec. max. Hold Mode FeedthrouOh ••• . .. ·.·.·.·.·...... 002% max. Sampl.to-Hold Offset Error, V IN • 0 ·. ·.·.·. ·. 2mV max. Sampl.to-Hold Gain Error, VIN • t10V. ·. ·...... 005% max • SimpC.to-Hold NonlinearitV Error. ·. ·.·...... 001% ..... POWER REQUIREMENT ...... ·. ·. ·.·. ·. :.t:15VDC • SmA max. I INPUT/0UTPUT CONNECTIONS PtN FUNCTION PtN FUNCTION 1 1- IN 8 CASE '} +fN n • 15\10C powER J OFFSET TRIM 10 GUARD 4 OFFSET TRIM tl HOLD CAPACITOR (CHI 5 -15\10C POWER ;, GUARO G NO CONNECTION 13 GROUND ,. DIGITAL CONTROL 1 OUTPUT 118 1~V()C • HaVOC GNO 119 HIGH G_IN DlfF IIliIPUT AMPLIFIER H(CTRONI<; $WIT(,;H -IN , ••'" 2 SAMPLE 8& HOLD. UNITY GAIN, NONINVERTING GAIN:a +1 The lOOK ohm off.t trimming pOtentiometer should be a 100 ppmfc e.met 15 turn type. To zero. ground input (pin 2) and digital control (pin 14) ... adju,t lOOK uffset trim for zero output (pin 7). The most commonly used sample and hold Three error contributions are specified for configuration for the SHM·'C is the noninvert· ."pl.to-ho'd errors: on-t error, gain error, ing unity gain circuit. This gives a high input .,d nonlinurity error. These sanpling errors impedance of 10· ohms, and the output vohaye .. cal'" by • IINU amount of charge being in the sample mode follows the input. Specifi dumped to or from the holding capecitor by cations are given for this configuration for two 'the sempling switch Mel ... reduced by a larger values of CH, .OO1J1F and .01#JF . The .OO l#JF value of CM• It is possible to compensate for capacitor gives exceUent speed (4 IolSOC. acquisi th_ errors by changing the gain and offset tion) with good hold mode voltage drOOJ) (only elsewhere in the externa' circuitry for the SOmV/sec. max). For even'better speed, a 100 non;nverting unity gain case. For the inverting pF c~acito( may be used to give an ac~u'sition case, the gain can be accompiished by adjusting time of only 2 ~sec. The hold mode droop. the external r.istor values and an offset can be however, increases lJy an order 01 magnilucJo to applied to pin 2 of the input amplifier. When 500mVlsec., and the samp'.to-hold errors also this external compensation is used. the outPUt inc.:reaso. For oxceUunt accuracy a .01 I'F will be in error during sampling. but will be C8P8Citor should be used, giving an acquisition accurate in the hold mode. Only the nonlinear time of 10 j.l18C•• and a ho'd mode droop of ity .rror will remain of the sample-ta-hold only 5mV/.-:. max. Even larger values of .rors. The offset adjustment of the input holding cap.citor can e. used with propor ~Iifiers should be used only to zero the tionate incre_ in accur-=v but "ower speed. device in the semple mode. The application graphs show the results for the In the inverting gain of one operating mode. the different valu.. feedbeck Md inpu1 resiston should be carefully For best results, CM should be a good quality matched or trimmed to give the desired gain of c:apIICitor with very high insulation resistance one. In general, the operating parameters are ~ low dielectric absorption. For temperatures the same • in the nonirwerting unity ga.n up to +SSOC polystyrene type capacitors ..e configuration except that the samp'ing~ band recommended. It is .'so recommended for width is reduced bV a fa:IOt of two. Likewise, lOWest h04d mode droop that a gu.rd ring be for higher gain configurations the sampling used around the eH termina' (pin 11) in the bendwidth is proponionately reduced. circuit board layout as shown on the last page. This is done to present leakage to other conductors on the circuit board duo to board leakago and contamination. If a large va'uo polystyrene capacitor is used, such as 1~F, hold mode droop as 'ow as 2o"V/SItC. (typicaU can be achieved with an acquisition time of about 3 mi Uiseconds.