Direct Memory Access Interface of Mc6800 with The

Direct Memory Access Interface of Mc6800 with The

DIRECT MEMORY ACCESS INTERFACE OF MC6800 WITH THE TDCIOIOJ LSI MULTIPLIER AND THE APPLICATION AS A DIGIT.~ FILTER A Thesis Presented to The Faculty of the College of Engineering and Technology Ohio University In Partial Fulfillment of the Requirements for the Degree Master of Science by Hsiao-Chen Hsueh/ March, 1983 ACKNO\~EDGEMENTS I wish to express my gratitude to Dr. Harold F. Klock whose guidance and patience make this work possible. Thanks are also due to my wife Jenny for her patience and understanding throughout the course of the work. ii LIST OF CONTENTS page ACKNOWLEDGMENTS · . ii LIST OF FIGURES · . vi LIST OF TABLES ................................................ viii Chapter 1. INTRODUCTION · . 1 1.1 Objectives ••••••••••••••••••••••••••••••••••••••••••••• 1 1.2 Scope of the Succeeding Chapters ••••••••••••••••••••••• 3 2. REAL-TIME DATA PROCESSING OF THE MICROPROCESSOR SYSTEM 6 2.1 Multiplication ••••••••••••••••••••••••••••••••••••••••• 6 2.2 Multiplication with LSI Fast Multiplier •••••••••••••••• 8 2.3 Multiplication with LSI MPY-16 and DMA Technique ••••••• 12 2.4 DMA Controller ••••••••••••••••••••••••••••••••••••••••• 15 3. CONTROL FUNCTION OF THE MICROCOMPUTER FOR REAL-TIME PROCESSING 16 3.1 Microprocessor ......................................... 16 3.2 Control Function Description - DMA Control •••••••.•.••• 18 3.3 The Maskable Interrupt (IRQ) and WAIT Instruction •••••• 23 4. HARDWARE IMPLEMENTATION OF DMA INTERFACE FOR LSI MULTIPLIER 28 4.1 Introduction ........................................... 28 4.2 The Control Logic of The Multiplier, MPY-16 (TDCIOIOJ) 28 4.3 Initialize and Start The DMA ••••••••••••••••••••••••••• 29 4.4 Address Counter of The DMA Controller 32 iii 4.5 DMA Word Counter and Sequence Control .................. 38 4.6 Accumulation Control and Output Control of The Multiplier 42 4.7 Conclusion ............................................. 45 4.8 Modification and Testing Experiment on Heathkit ET-3400 for DMA Data Transfer Design ........................... 51 5. DIGITAL FILTERING, AN APPLICATION OF A FAST LSI MULTIPLIER AND DMA TECHNIQUE .......................................... 53 5.1 Digital Filtering S3 5.2 Elements of A Digital Filter 56 5.3 A Simple Digital Filter 57 5.4 AID, D/A and SiR Device ................................ 64 5.5 IRQ Configuration ...................................... 69 6. DATA FORMAT AND SIGNAL SCALING 73 6.1 Data Format 73 6.2 Scaling Factor ......................................... 74 6.3 Signal Scaling 75 7. SOME REAL EXAMPLES OF DIGITAL FILTER 81 7.1 Maximum Sampling Rate 81 7.2 Digital Filter Examples 81 7.3 Errors and Accuracy .................................... 100 8. CONCLUSION AND SUGGESTIONS ................................. 101 8.1 Review ................................................ 101 8.2 Further Developments and Studies 102 LIST OF REFERENCES 104 iv APPENDIX A Multiplier-Accumulator Parallel 16-Bit ••••••••••••••••• 105 B Timing Diagram of DMA Control Signals •••••••••••••••••• 110 e.l ADC-HX12B 12-Bit AID Converter ••••••••••••••••••••••••• III C.2 DAC-UP8BC 8-Bit D/A Converter •••••••••••••••••••••••••• 115 C.3 SHM-IC-l SiR Device •••••••••••••••••••••••••••••••••••• 118 v LIST OF FIGURES 1-1 Block Diagram of D!A, AID Converters with the Fast LSI Multiplier and DMA Logic in A Micro-system ••••••••••••••• 4 2-1 The Basic Logic Diagram for TRW 16-Bit MAC Unit •••••••••• 9 2-2 MPY-16 Multiplier Interfaces with 6800 ••••••••.•••.•••••• 10 2-3 A Direct-Memory-Access Interface 13 2-4 A Simple Data Channel for DMA Controlled Multiply •••.•••• 14 3-1 The 6800 Microcomputer System •••••••••••••••••••••••••••• 17 3-2 HALT CPU Signal Timing ••••••••••••••••••••••••••••••••••• 1y 3-3 Block Diagram of Sychronizing HALT and BA ••••••••••.•.••• 21 3-4 Synchronized HALT and BA Timing •••••••••••••••••••••••••• 22 3-5 Flowchart for A Simple Input/Output Interrupt Program 26 4-1 TDCIOIOJ Control Timing Diagram •••••••..••.••••••••••••.• 30 4-2 Address Decoding for Initializing and Starting D}~ ••••••• 31 4-3 Synchronizing HALT and BA, Pulse Width Generated with a One-Shot •••••••••••••••••.•••••••••••••••••••••..•••••.•• 33 4-4 Block Diagram of DMA Address Generator 35 4-5 Timing Diagram of D}~ Address Counter 36 4-6 Hardware Implementation of Address Counter 37 4-7 Interface Between The Data Bus and The Multiplier •••••••• 40 4-8 Timing Diagram for Word Counter •••••••••••••••••••.•••••• 41 4-9. Hardware Implementation of Word Counter and" Sequence Control 43 4-10 The Difference by Using Rip~le Counter or Synchronous Counter for word Counter 44 vi 4-11 The Accumulation Control Signal •••••••••••••••••••••••••• 45 4-12 Control Timing for The Multiplier Output and Interface with The Data Bus •••••••••••••••••••••••••••••••••••••••• 46 4-13 Output Control Logic for The Multiplier •••••••••••••••••• 47 4-14 Timing of Related Control Signals in A DMA Cycle ••••••••• 48 4-15 The Pin Connections between The Multiplier and Data Bus 50 4-16 Modification Being Made on Heathkit ET-3400 to Fit DMA Block Data Transfer •••••••••••••••••••••••••••••••••••••• 52 5-1 Block Representation of A Digital Signal Processing System 54 5-2 The Realization of (a) N-th Order Nonrecursive Filter (b) 2nd Order Recursive Filter •••••••• 58 5-3 A Simple Digital Signal Processing Based on The 6800 with DMA and The MPY-16 ••••••••••••••••••••••••••••••••••••••• 59 5-4 The Processing Flow of A Simple Digital Filter System 61 5-5 The Analog-to-Digital Converter and The Interface with Data Bus ................................................. 65 5-6 The Digital-to-Analog Converter and The Interface with Data Bus ................................................. 67 5-7 The Sample-And-Hold Device and The External Clock •••••••• 68 6-1 Variable Gain,Digital Filter ••••••••••••••••••••••••••••• 77 7-1 Timing Diagram of WAI and IRQ at Optimum Response •••••••• 83 vii LIST OF TABLES 2-1 An 6800 Coded Application Program for The MPY-16 •••••••••• 11 3-1 Memory Maps for 6800 Address Used in Response to Interrupts and Reset ................................................ 23 5-1 Digital-Filter Elements •••••••••••••••••••••••••••••••••• 57 7-1 Mathod of The Maximum Sampling Rate Calculation •••••••••• 82 viii Chapter 1 INTRODUCTION 1.1 Objectives Real-time processing is the act of processing data as it arrives, as opposed to storing it, and processing it at a leisurely pace. In years past, real-time processing tasks were difficult to handle using microprocessors because of the machines' slow speed and small data-word size, especially if complex arithmetic operations are involved. Multiplication and division naturally slow most microprocessors, because few have multiply and divide instructions. At least 16 bits of data are used in any serious arithmetic processing, so double precision mathematics must be performed on 8-bit microprocessors, further hindering processor performance. A more reasonable approach to this problem is the use of an external arithmetic processing unit dedicated to performing double-precision arithmetic at a very high rate. Such a processor can be built out of discrete components, or one of the new monolithic processing units can be interfaced directly to a microcomputer bus. The objective of this thesis is to demonstrat~ how to achieve the multiplications in a micro­ system at high speed with a dedicated hardware multiplier and how to get the data to and from the multiplier fast. For these purposes, high- speed monolithic multipliers such as TRW's MPY-16 (TDCIOIOJ) can be used. The MPY-16 is a 16 x 16 one-chip multiplier that can generate a 32-bit product in 200ns. When interfacing chips such as this to a 1 2 microprocessor, careful analysis must be done beforehand to determine if the vast multiplying power can successfully be utilized by the microprocessor. Interfacing a 200ns multiplier to a 1MHz 6800, for instance, would be overkill, because it takes at least 12us just to move two operands to the multiplier under processor control. Alternatively, a more effective way is to apply the direct-memory- access technique to the data transfer between the memory and the multiplier. However, the DMA data transfer is device-initiated. A program-dependent decision to transfer data requires a programmed instruction to cause a DMA service request. This is hardly worth the trouble for a single-word transfer. Most DMA transfers, whether device or program initiated, involve not single words but blocks of data words. Many forms of processing such as graphics, image, and signal processing require many multiplication operations. For these applications, high-speed DMAblock data transfer is especially suitable. A particular application of the fast multiplier with the AID and D/A converters as a digital filter is discussed in the later chapters. An example is a 2nd order nonrecursive digital filter which is characterized by Equation(l.l): (see also Figure 5-1) (1.1) where n = 0,1,2,3,.... The system has to perform three multiplications, two additions and transfer seven data words to or from 3 the multiplier during each T time increment (T is referred to the sampling period of the system). A block diagram of such a system is depicted in Figure 1-1; it shows that DMA interfacing is applied between the multiplier and the microcomputer system to make fast data transfer. 1.2 Scope of the Succeeding Chapters In chapter 2, the Heathkit 6800 trainer (ET-3400) will be the example used to discuss the advantage of applying a hardware multiplier to the micro-system. The general interfacing and

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