DOCSLIB.ORG

Case Study on Integrated Architecture for In-Memory and In-Storage Computing

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Case Study on Integrated Architecture for In-Memory and In-Storage Computing electronics Article Case Study on Integrated Architecture for In-Memory and In-Storage Computing Manho Kim 1, Sung-Ho Kim 1, Hyuk-Jae Lee 1 and Chae-Eun Rhee 2,* 1 Department of Electrical Engineering, Seoul National University, Seoul 08826, Korea; [email protected] (M.K.); [email protected] (S.-H.K.); [email protected] (H.-J.L.) 2 Department of Information and Communication Engineering, Inha University, Incheon 22212, Korea * Correspondence: [email protected]; Tel.: +82-32-860-7429 Abstract: Since the advent of computers, computing performance has been steadily increasing. Moreover, recent technologies are mostly based on massive data, and the development of artificial intelligence is accelerating it. Accordingly, various studies are being conducted to increase the performance and computing and data access, together reducing energy consumption. In-memory computing (IMC) and in-storage computing (ISC) are currently the most actively studied architectures to deal with the challenges of recent technologies. Since IMC performs operations in memory, there is a chance to overcome the memory bandwidth limit. ISC can reduce energy by using a low power processor inside storage without an expensive IO interface. To integrate the host CPU, IMC and ISC harmoniously, appropriate workload allocation that reflects the characteristics of the target application is required. In this paper, the energy and processing speed are evaluated according to the workload allocation and system conditions. The proof-of-concept prototyping system is implemented for the integrated architecture. The simulation results show that IMC improves the performance by 4.4 times and reduces total energy by 4.6 times over the baseline host CPU. ISC is confirmed to Citation: Kim, M.; Kim, S.-H.; Lee, significantly contribute to energy reduction. H.-J.; Rhee, C.-E. Case Study on Integrated Architecture for Keywords: near data processing; processing in memory; in-storage computing In-Memory and In-Storage Computing. Electronics 2021, 10, 1750. https://doi.org/10.3390/ electronics10151750 1. Introduction Academic Editor: Fabio Grandi Recently, there has been growing interest and demand for artificial intelligence and immersive media. These applications require high performance devices to process massive Received: 15 June 2021 data. However, it is difficult to compute and transfer such large amounts of data in the Accepted: 17 July 2021 traditional von Neumann architecture because it consumes significant power and dissipates Published: 21 July 2021 heat energy as Moore’s Law and Dennard scaling reach physical limits. It is known that data access and movement are the main bottleneck of processing speed, and they consume Publisher’s Note: MDPI stays neutral more energy than computing itself [1]. Thus, many studies about near data processing are with regard to jurisdictional claims in ongoing to overcome these challenges [2,3]. published maps and institutional affil- Near data processing is applicable not only in traditional memory, such as SRAM [4,5] iations. and DRAM [2,6–10], but also in emerging memory, such as PCM [11], STT-MRAM [12], and ReRAM [13]. There are also various attempts to reduce the data movement overhead by computation offloading to storage devices [3,14–16]. However, real-world applications are composed of complex and diverse tasks, and thus, there is a limit to solving the problems Copyright: © 2021 by the authors. with an individual device-level approach. In this paper, the requirements of tasks for Licensee MDPI, Basel, Switzerland. real application scenarios are analyzed in terms of task partition and the data movement This article is an open access article overhead. By providing various options for near data processing in consideration of the distributed under the terms and characteristics of each task that composes an application, opportunities to reduce the data conditions of the Creative Commons movement overhead are explored at the architectural level. Attribution (CC BY) license (https:// • This paper makes the following contributions: creativecommons.org/licenses/by/ • The requirements of the task are analyzed from the memory and storage points of view. 4.0/). Electronics 2021, 10, 1750. https://doi.org/10.3390/electronics10151750 https://www.mdpi.com/journal/electronics Electronics 2021, 10, x FOR PEER REVIEW 2 of 13 • Electronics 2021, 10, 1750 The requirements of the task are analyzed from the memory and storage points2 of of 12 view. • An integrated architecture for in-memory and in-storage computing is proposed, and its implementation is verified on a prototyping system. • An integrated architecture for in-memory and in-storage computing is proposed, • Possible performance improvement is shown in terms of execution time and energy. and its implementation is verified on a prototyping system. • Possible performance improvement is shown in terms of execution time and energy. 2. Background and Related Work 2.1.2. Background In-Memory Computing and Related Work 2.1. In-MemoryIn-memory Computing computing (IMC), also known as processing in-memory (PIM), is a para- digmIn-memory that places computing processing (IMC), elements also knownnear or as inside processing the memory in-memory in (PIM)order, to is aobtain paradigm fast memorythat places access processing and high elements bandwidth. near orAmong inside th thee various memory types in order of memory, to obtain this fast paper memory fo- cusesaccess on and in-memory high bandwidth. computing Among for DRAM, the various which types is most of memory, widely thisused paper and has focuses high on den- in- sity.memory There computing are two forcategories DRAM, of which in-DRAM is most computing widely used depending and has high on density.the package There and are moduletwo categories assembly of in-DRAM of the DRAM computing chip: depending computation on thein packagetwo-dimensional and module (2D) assembly planar DRAM,of the DRAM and computation chip: computation in three-dimensional in two-dimensional (3D) stacked (2D) planar DRAM. DRAM, In 2D and planar computation DRAM, processingin three-dimensional elements (3D)reside stacked in the DRAM. DRAM In die 2D as planar shown DRAM, in Figure processing 1a. Since elements data residetravel throughin the DRAM on-chip die inter-connection as shown in Figure on1 thea. Since DRAM data die, travel it is throughfree from on-chip off-chip inter-connection IO constraints, andon the also DRAM it can die,achieve it is high free fromparallelism off-chip by IO exploiting constraints, the andbit-line also of it the can subarray, achieve highrow buffer,parallelism and byinternal exploiting data theline bit-line [2,6]. However, of the subarray, there are row some buffer, difficulties and internal in computing data line [2 ,6in]. 2DHowever, planar thereDRAM. are someBecause difficulties the DRAM in computing manufacturing in 2D planarprocess DRAM. is optimized Because for the low DRAM cost andmanufacturing low leakage, process only simple is optimized logic can for be low placed, cost anddue low to the leakage, bulky onlyand slow simple transistors. logic can Thebe placed, standard due logic to the process bulky is and optimized slow transistors. to deal with The complex standard logic logic functions, process isbut optimized requires frequentto deal with refresh complex operations, logic functions, due to the but current requires leaky frequent characteristic. refresh operations, This leads due to to high the powercurrent consumption leaky characteristic. and poor This performance. leads to high In power order consumptionto overcome these and poor drawbacks, performance. there haveIn order been to overcomeattempts to these add drawbacks, separate chips there fo haver processing been attempts elements to add over separate the 2D chips planar for DRAMprocessing chip elements in the dual-inline over the 2D memory planar DRAMmodule chip(DIMM) in the [7,8]. dual-inline However, memory additional module as- sembly(DIMM) process [7,8]. However, is required, additional and cost assembly is consequently process is required,increased. and On cost the is consequentlycontrary, 3D stackedincreased. DRAM, On the such contrary, as high 3D stackedbandwidth DRAM, memory such as(HBM) high bandwidthand hybrid memory memory (HBM) cube (HMC),and hybrid can memoryuse the DRAM cube (HMC), process can and use standard the DRAM logicprocess processand together standard because logic they process pile uptogether more than because two they dice. pile Therefore, up more more than complex two dice. processing Therefore, elements more complex can be processinglocated on theelements base die can with be the located standard on the logic base process die with as shown the standard in Figure logic 1b [9,10]. process Even as though shown the in physicalFigure1b interface [ 9,10]. Even(PHY), though through-silicon the physical via interface(TSV), and (PHY), IEEE1500 through-silicon area for test via pins (TSV), and circuitsand IEEE1500 occupy area the base for test die, pins there and is still circuits extra occupy space thethatbase can be die, used there for is other stillextra purposes. space that can be used for other purposes. (a) (b) Figure 1. In-memoryIn-memory computing computing structure examples: ( a) 2D 2D planar planar DRAM, DRAM, such such as as DIMM DIMM type, type, and and ( (bb)) 3D 3D stacked stacked DRAM, DRAM, such as HBM type. 2.2. In-Storage Computing For in-storage computing (ISC), some computations are offloaded to the storage device. There was a study in which a hard disk drive (HDD) used a processor to com- pute offloaded tasks for ISC [14]. However, HDDs were quickly replaced by solid-state drives (SSDs), after SSDs were introduced. The conventional SSDs do not process data, Electronics 2021, 10, 1750 3 of 12 even though they have an embedded processor. The internal structure of the SSD is shown in Figure2 . The SSD consists of non-volatile NAND flash chips that do not lose data re- gardless of power-off, and an embedded processor, such as the ARM processor, to manage the firmware, such as the flash translation layer (FTL).
Load more

Recommended publications
  • Performance Impact of Memory Channels on Sparse and Irregular Algorithms
    Performance Impact of Memory Channels on Sparse and Irregular Algorithms Oded Green1,2, James Fox2, Jeffrey Young2, Jun Shirako2, and David Bader3 1NVIDIA Corporation — 2Georgia Institute of Technology — 3New Jersey Institute of Technology Abstract— Graph processing is typically considered to be a Graph algorithms are typically latency-bound if there is memory-bound rather than compute-bound problem. One com- not enough parallelism to saturate the memory subsystem. mon line of thought is that more available memory bandwidth However, the growth in parallelism for shared-memory corresponds to better graph processing performance. However, in this work we demonstrate that the key factor in the utilization systems brings into question whether graph algorithms are of the memory system for graph algorithms is not necessarily still primarily latency-bound. Getting peak or near-peak the raw bandwidth or even the latency of memory requests. bandwidth of current memory subsystems requires highly Instead, we show that performance is proportional to the parallel applications as well as good spatial and temporal number of memory channels available to handle small data memory reuse. The lack of spatial locality in sparse and transfers with limited spatial locality. Using several widely used graph frameworks, including irregular algorithms means that prefetched cache lines have Gunrock (on the GPU) and GAPBS & Ligra (for CPUs), poor data reuse and that the effective bandwidth is fairly low. we evaluate key graph analytics kernels using two unique The introduction of high-bandwidth memories like HBM and memory hierarchies, DDR-based and HBM/MCDRAM. Our HMC have not yet closed this inefficiency gap for latency- results show that the differences in the peak bandwidths sensitive accesses [19].
    [Show full text]
  • ECE 571 – Advanced Microprocessor-Based Design Lecture 17
    ECE 571 { Advanced Microprocessor-Based Design Lecture 17 Vince Weaver http://web.eece.maine.edu/~vweaver [email protected] 3 April 2018 Announcements • HW8 is readings 1 More DRAM 2 ECC Memory • There's debate about how many errors can happen, anywhere from 10−10 error/bit*h (roughly one bit error per hour per gigabyte of memory) to 10−17 error/bit*h (roughly one bit error per millennium per gigabyte of memory • Google did a study and they found more toward the high end • Would you notice if you had a bit flipped? • Scrubbing { only notice a flip once you read out a value 3 Registered Memory • Registered vs Unregistered • Registered has a buffer on board. More expensive but can have more DIMMs on a channel • Registered may be slower (if it buffers for a cycle) • RDIMM/UDIMM 4 Bandwidth/Latency Issues • Truly random access? No, burst speed fast, random speed not. • Is that a problem? Mostly filling cache lines? 5 Memory Controller • Can we have full random access to memory? Why not just pass on CPU mem requests unchanged? • What might have higher priority? • Why might re-ordering the accesses help performance (back and forth between two pages) 6 Reducing Refresh • DRAM Refresh Mechanisms, Penalties, and Trade-Offs by Bhati et al. • Refresh hurts performance: ◦ Memory controller stalls access to memory being refreshed ◦ Refresh takes energy (read/write) On 32Gb device, up to 20% of energy consumption and 30% of performance 7 Async vs Sync Refresh • Traditional refresh rates ◦ Async Standard (15.6us) ◦ Async Extended (125us) ◦ SDRAM -
    [Show full text]
  • Adm-Pcie-9H3 V1.5
    ADM-PCIE-9H3 10th September 2019 Datasheet Revision: 1.5 AD01365 Applications Board Features • High-Performance Network Accelerator • 1x OpenCAPI Interface • Data CenterData Processor • 1x QSFP-DD Cages • High Performance Computing (HPC) • Shrouded heatsink with passive and fan cooling • System Modelling options • Market Analysis FPGA Features • 2x 4GB HBM Gen2 memory (32 AXI Ports provide 460GB/s Access Bandwidth) • 3x 100G Ethernet MACs (incl. KR4 RS-FEC) • 3x 150G Interlaken cores • 2x PCI Express x16 Gen3 / x8 Gen4 cores Summary The ADM-PCIE-9H3 is a high-performance FPGA processing card intended for data center applications using Virtex UltraScale+ High Bandwidth Memory FPGAs from Xilinx. The ADM-PCIE-9H3 utilises the Xilinx Virtex Ultrascale Plus FPGA family that includes on substrate High Bandwidth Memory (HBM Gen2). This provides exceptional memory Read/Write performance while reducing the overall power consumption of the board by negating the need for external SDRAM devices. There are also a number of high speed interface options available including 100G Ethernet MACs and OpenCAPI connectivity, to make the most of these interfaces the ADM-PCIE-9H3 is fitted with a QSFP-DD Cage (8x28Gbps lanes) and one OpenCAPI interface for ultra low latency communications. Target Device Host Interface Xilinx Virtex UltraScale Plus: XCVU33P-2E 1x PCI Express Gen3 x16 or 1x/2x* PCI Express (FSVH2104) Gen4 x8 or OpenCAPI LUTs = 440k(872k) Board Format FFs = 879k(1743k) DSPs = 2880(5952) 1/2 Length low profile x16 PCIe form Factor BRAM = 23.6Mb(47.3Mb) WxHxD = 19.7mm x 80.1mm x 181.5mm URAM = 90.0Mb(180.0Mb) Weight = TBCg 2x 4GB HBM Gen2 memory (32 AXI Ports Communications Interfaces provide 460GB/s Access Bandwidth) 1x QSFP-DD 8x28Gbps - 10/25/40/100G 3x 100G Ethernet MACs (incl.
    [Show full text]
  • High Bandwidth Memory for Graphics Applications Contents
    High Bandwidth Memory for Graphics Applications Contents • Differences in Requirements: System Memory vs. Graphics Memory • Timeline of Graphics Memory Standards • GDDR2 • GDDR3 • GDDR4 • GDDR5 SGRAM • Problems with GDDR • Solution ‐ Introduction to HBM • Performance comparisons with GDDR5 • Benchmarks • Hybrid Memory Cube Differences in Requirements System Memory Graphics Memory • Optimized for low latency • Optimized for high bandwidth • Short burst vector loads • Long burst vector loads • Equal read/write latency ratio • Low read/write latency ratio • Very general solutions and designs • Designs can be very haphazard Brief History of Graphics Memory Types • Ancient History: VRAM, WRAM, MDRAM, SGRAM • Bridge to modern times: GDDR2 • The first modern standard: GDDR4 • Rapidly outclassed: GDDR4 • Current state: GDDR5 GDDR2 • First implemented with Nvidia GeForce FX 5800 (2003) • Midway point between DDR and ‘true’ DDR2 • Stepping stone towards DDR‐based graphics memory • Second‐generation GDDR2 based on DDR2 GDDR3 • Designed by ATI Technologies , first used by Nvidia GeForce FX 5700 (2004) • Based off of the same technological base as DDR2 • Lower heat and power consumption • Uses internal terminators and a 32‐bit bus GDDR4 • Based on DDR3, designed by Samsung from 2005‐2007 • Introduced Data Bus Inversion (DBI) • Doubled prefetch size to 8n • Used on ATI Radeon 2xxx and 3xxx, never became commercially viable GDDR5 SGRAM • Based on DDR3 SDRAM memory • Inherits benefits of GDDR4 • First used in AMD Radeon HD 4870 video cards (2008) • Current
    [Show full text]
  • Architectures for High Performance Computing and Data Systems Using Byte-Addressable Persistent Memory
    Architectures for High Performance Computing and Data Systems using Byte-Addressable Persistent Memory Adrian Jackson∗, Mark Parsonsy, Michele` Weilandz EPCC, The University of Edinburgh Edinburgh, United Kingdom ∗[email protected], [email protected], [email protected] Bernhard Homolle¨ x SVA System Vertrieb Alexander GmbH Paderborn, Germany x [email protected] Abstract—Non-volatile, byte addressable, memory technology example of such hardware, used for data storage. More re- with performance close to main memory promises to revolutionise cently, flash memory has been used for high performance I/O computing systems in the near future. Such memory technology in the form of Solid State Disk (SSD) drives, providing higher provides the potential for extremely large memory regions (i.e. > 3TB per server), very high performance I/O, and new ways bandwidth and lower latency than traditional Hard Disk Drives of storing and sharing data for applications and workflows. (HDD). This paper outlines an architecture that has been designed to Whilst flash memory can provide fast input/output (I/O) exploit such memory for High Performance Computing and High performance for computer systems, there are some draw backs. Performance Data Analytics systems, along with descriptions of It has limited endurance when compare to HDD technology, how applications could benefit from such hardware. Index Terms—Non-volatile memory, persistent memory, stor- restricted by the number of modifications a memory cell age class memory, system architecture, systemware, NVRAM, can undertake and thus the effective lifetime of the flash SCM, B-APM storage [29]. It is often also more expensive than other storage technologies.
    [Show full text]
  • How to Manage High-Bandwidth Memory Automatically
    How to Manage High-Bandwidth Memory Automatically Rathish Das Kunal Agrawal Michael A. Bender Stony Brook University Washington University in St. Louis Stony Brook University [email protected] [email protected] [email protected] Jonathan Berry Benjamin Moseley Cynthia A. Phillips Sandia National Laboratories Carnegie Mellon University Sandia National Laboratories [email protected] [email protected] [email protected] ABSTRACT paging algorithms; Parallel algorithms; Shared memory al- This paper develops an algorithmic foundation for automated man- gorithms; • Computer systems organization ! Parallel ar- agement of the multilevel-memory systems common to new super- chitectures; Multicore architectures. computers. In particular, the High-Bandwidth Memory (HBM) of these systems has a similar latency to that of DRAM and a smaller KEYWORDS capacity, but it has much larger bandwidth. Systems equipped with Paging, High-bandwidth memory, Scheduling, Multicore paging, HBM do not fit in classic memory-hierarchy models due to HBM’s Online algorithms, Approximation algorithms. atypical characteristics. ACM Reference Format: Unlike caches, which are generally managed automatically by Rathish Das, Kunal Agrawal, Michael A. Bender, Jonathan Berry, Benjamin the hardware, programmers of some current HBM-equipped super- Moseley, and Cynthia A. Phillips. 2020. How to Manage High-Bandwidth computers can choose to explicitly manage HBM themselves. This Memory Automatically. In Proceedings of the 32nd ACM Symposium on process is problem specific and resource intensive. Vendors offer Parallelism in Algorithms and Architectures (SPAA ’20), July 15–17, 2020, this option because there is no consensus on how to automatically Virtual Event, USA. ACM, New York, NY, USA, 13 pages. https://doi.org/10.
    [Show full text]
  • Exploring New Features of High- Bandwidth Memory for Gpus
    This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.*, No.*, 1{11 Exploring new features of high- bandwidth memory for GPUs Bingchao Li1, Choungki Song2, Jizeng Wei1, Jung Ho Ahn3a) and Nam Sung Kim4b) 1 School of Computer Science and Technology, Tianjin University 2 Department of Electrical and Computer Engineering, University of Wisconsin- Madison 3 Graduate School of Convergence Science and Technology, Seoul National University 4 Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign a) [email protected] b) [email protected] Abstract: Due to the off-chip I/O pin and power constraints of GDDR5, HBM has been proposed to provide higher bandwidth and lower power consumption for GPUs. In this paper, we first provide de- tailed comparison between HBM and GDDR5 and expose two unique features of HBM: dual-command and pseudo channel mode. Second, we analyze the effectiveness of these two features and show that neither notably contributes to performance. However, by combining pseudo channel mode with cache architecture supporting fine-grained cache- line management such as Amoeba cache, we achieve high efficiency for applications with irregular memory requests. Our experiment demon- strates that compared with Amoeba caches with legacy mode, Amoeba cache with pseudo channel mode improves GPU performance by 25% and reduces HBM energy consumption by 15%. Keywords: GPU, HBM, DRAM, Amoeba cache, Energy Classification: Integrated circuits References [1] JEDEC: Graphic Double Data Rate 5 (GDDR5) Specification (2009) https://www.jedec.org/standards- documents/results/taxonomy%3A4229.
    [Show full text]
  • AXI High Bandwidth Memory Controller V1.0 Logicore IP
    AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide Vivado Design Suite PG276 (v1.0) August 6, 2021 Table of Contents Chapter 1: Introduction.............................................................................................. 4 Features........................................................................................................................................4 IP Facts..........................................................................................................................................6 Chapter 2: Overview......................................................................................................7 Unsupported Features................................................................................................................8 Licensing and Ordering.............................................................................................................. 8 Chapter 3: Product Specification........................................................................... 9 Standards..................................................................................................................................... 9 Performance.............................................................................................................................. 10 Lateral AXI Switch Access Throughput Loss.......................................................................... 11 Resource Use............................................................................................................................
    [Show full text]
  • Arxiv:1905.04767V1 [Cs.DB] 12 May 2019 Ing Amounts of Data Into Their Complex Computational Data Locality, Limiting Data Reuse Through Caching [121]
    Moving Processing to Data On the Influence of Processing in Memory on Data Management Tobias Vin¸con · Andreas Koch · Ilia Petrov Abstract Near-Data Processing refers to an architec- models, on the other hand database applications exe- tural hardware and software paradigm, based on the cute computationally-intensive ML and analytics-style co-location of storage and compute units. Ideally, it will workloads on increasingly large datasets. Such modern allow to execute application-defined data- or compute- workloads and systems are memory intensive. And even intensive operations in-situ, i.e. within (or close to) the though the DRAM-capacity per server is constantly physical data storage. Thus, Near-Data Processing seeks growing, the main memory is becoming a performance to minimize expensive data movement, improving per- bottleneck. formance, scalability, and resource-efficiency. Processing- Due to DRAM's and storage's inability to perform in-Memory is a sub-class of Near-Data processing that computation, modern workloads result in massive data targets data processing directly within memory (DRAM) transfers: from the physical storage location of the data, chips. The effective use of Near-Data Processing man- across the memory hierarchy to the CPU. These trans- dates new architectures, algorithms, interfaces, and de- fers are resource intensive, block the CPU, causing un- velopment toolchains. necessary CPU waits and thus impair performance and scalability. The root cause for this phenomenon lies in Keywords Processing-in-Memory · Near-Data the generally low data locality as well as in the tradi- Processing · Database Systems tional system architectures and data processing algo- rithms, which operate on the data-to-code principle.
    [Show full text]
  • Breaking the Memory-Wall for AI: In-Memory Compute, Hbms Or Both?
    Breaking the memory-wall for AI: In-memory compute, HBMs or both? Presented By: Kailash Prasad PhD Electrical Engineering nanoDC Lab 9th Dec 2019 Outline ● Motivation ● HBM - High Bandwidth Memory ● IMC - In Memory Computing ● In-memory compute, HBMs or both? ● Conclusion nanoDC Lab 2/48 Von - Neumann Architecture nanoDC Lab Source: https://en.wikipedia.org/wiki/Von_Neumann_architecture#/media/File:Von_Neumann_Architecture.svg 3/48 Moore’s Law nanoDC Lab Source: https://www.researchgate.net/figure/Evolution-of-electronic-CMOS-characteristics-over-time-41-Transistor-counts-orange_fig2_325420752 4/48 Power Wall nanoDC Lab Source: https://medium.com/artis-ventures/omicia-moores-law-the-coming-genomics-revolution-2cd31c8e5cd0 5/48 Hwang’s Law Hwang’s Law: Chip capacity will double every year nanoDC Lab Source: K. C. Smith, A. Wang and L. C. Fujino, "Through the Looking Glass: Trend Tracking for ISSCC 2012," in IEEE Solid-State Circuits Magazine 6/48 Memory Wall nanoDC Lab Source: http://on-demand.gputechconf.com/gtc/2018/presentation/s8949 7/48 Why this is Important? nanoDC Lab Source: https://hackernoon.com/the-most-promising-internet-of-things-trends-for-2018-10a852ccd189 8/48 Deep Neural Network nanoDC Lab Source: http://on-demand.gputechconf.com/gtc/2018/presentation/s8949 9/48 Data Movement vs. Computation Energy ● Data movement is a major system energy bottleneck ○ Comprises 41% of mobile system energy during web browsing [2] ○ Costs ~115 times as much energy as an ADD operation [1, 2] [1]: Reducing data Movement Energy via Online Data Clustering and Encoding (MICRO’16) [2]: Quantifying the energy cost of data movement for emerging smart phone workloads on mobile platforms (IISWC’14) nanoDC Lab Source: Mutlu, O.
    [Show full text]
  • High Performance Memory
    High Performance Memory Jacob Lowe and Lydia Hays ● DDR SDRAM and Problems ● Solutions ● HMC o History o How it works o Specifications ● Comparisons ● Future ● DDR3: ○ Norm for average user ● DDR4: ○ Expensive ○ Less power (15W) ○ Around only 5% faster ○ Mostly for server farms ● GDDR5: (based on DDR2) ○ Expensive ○ Twice the bandwidth ○ Only in graphics cards ● Decreasing operating voltage Conclusion: Reaching limit of current technology ● Increasing # of banks ● Increase Frequency ● Wide I/O ● High-Bandwidth Memory (HBM) ● Hybrid Memory Cube (HMC) ● Layered Dram controlled with a logic layer ● Layers are linked with TSV ● Each Rank is a separate channel ● Each Channel contains a number of banks of data ● Hard to dissipate heat from DRAM layers ● Due to it’s 2.5D design, has great use in devices where size is important ● HBM: High Bandwidth Memory ● Is like the ‘mid point’ between HMC and Wide I/O ● Four DRAM layers each divided into two channels ● TSV linked layers ● Hard to implement structure as currently proposed ● Samsung and Micron decide that memory needed a new standard, away from DDR ● In order to make things easier to access, a vertical design is needed with excellent data accessibility ● In order to help the process, Micron and Samsung have started the Hybrid Memory Cube Consortium, a group comprised of over 100 companies ● First draft of the specifications was released August 14, 2012. Since then a revision 1.1 and 2.0 has been released. ● HBM, the Intel solution, is directly competing with HMC, the AMD solution Through-Silicon
    [Show full text]
  • High-Performance Architectures for Embedded Memory Systems
    High-Performance Architectures for Embedded Memory Systems Christoforos E. Kozyrakis Computer Science Division University of California, Berkeley [email protected] http://iram.cs.berkeley.edu/ Embedded DRAM systems roadmap This presentation Previous talks Desktop Laptop 32 MB Network Computer Camera/Phone 8 MB Video Games Graphics/Disks 2 MB Christoforos E. Kozyrakis ICCAD’98, Embedded Memory Tutorial Page 2 U.C. Berkeley Outline • Overview of general-purpose processors today • Future processor applications & requirements • Advantages and challenges of processor-DRAM integration • Future microprocessor architectures – characteristics and features – compatibility and interaction with embedded DRAM technology • Comparisons and conclusions Christoforos E. Kozyrakis ICCAD’98, Embedded Memory Tutorial Page 3 U.C. Berkeley Current state-of-the-art processors (1) • High performance processors – 64-bit operands, wide instruction issue (3-4) – dynamic scheduling, out-of-order execution, speculation – large multi-level caches – support for parallel systems – optimized for technical and/or commercial workloads – SIMD multimedia extensions (VIS, MAX, MMX, MDMX, Altivec) – 200 to 600 MHz, 20 to 80 Watts, 200 to 300 sq. mm – e.g. MIPS R10K, Pentium II, Alpha 21264, Sparc III Christoforos E. Kozyrakis ICCAD’98, Embedded Memory Tutorial Page 4 U.C. Berkeley Current state-of-the-art processors (2) • Embedded processors – 32/64-bit, single/dual issue, in-order execution – single-level (small) caches – code density improvements (Thump/MIPS16) – DSP/SIMD support – integrated I/O and memory controllers – some on-chip DRAM (up to 4MB) – optimized for low power, price/performance, MIPS/Watt – 50 to 250MHz, 0.3 to 4 Watts, 10 to 100 sq. mm – e.g.
    [Show full text]