DOCSLIB.ORG

FR FAMILY TM ASSEMBLER MANUAL for V6

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
FR FAMILY TM ASSEMBLER MANUAL for V6 FUJITSU SEMICONDUCTOR CM71-00203-3E CONTROLLER MANUAL FR FAMILY SOFTUNETM ASSEMBLER MANUAL for V6 FR FAMILY SOFTUNETM ASSEMBLER MANUAL for V6 FUJITSU LIMITED PREFACE ■ Purpose of this manual and target readers This manual describes the functions and operations of the Fujitsu SOFTUNE Assembler operating on Windows 98, Windows Me, Windows 2000, and Windows XP. This manual is intended for engineers who are developing application programs using the FR family microprocessor. Read this manual thoroughly. ■ Trademarks SOFTUNE is a trademark of FUJITSU LIMITED. Microsoft and Windows are registered trademarks of Microsoft Corporation in the U.S. and other countries. The names of products and systems appearing in this manual are trademarks or registered trademarks of their respective companies. However, TM mark or ® mark may not be specified. ■ Configuration of This Manual This manual consists of two parts and an appendix. PART 1 OPERATION This part explains how to use the SOFTUNE assembler. PART 2 SYNTAX This part describes the syntax and format for writing assembly source programs. APPENDIX The appendix explains error messages and note restrictions that must be observed. ■ Product name abbreviation In this manual, product names are designated as follows: The MicrosoftTM WindowsTM 98 operating system is abbreviated to Windows 98. The MicrosoftTM WindowsTM Millennium Edition operating system is abbreviated to Windows Me. The MicrosoftTM WindowsTM 2000 Professional operating system is abbreviated to Windows 2000. The MicrosoftTM WindowsTM XP Professional operating system is abbreviated to Windows XP. i • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. • The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information. • Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. • The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. • Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. • If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Copyright© 2002-2006 FUJITSU LIMITED All rights reserved ii CONTENTS PART1 OPERATION ......................................................................................................... 1 CHAPTER 1 OVERVIEW ................................................................................................... 3 1.1 SOFTUNE Assembler ......................................................................................................................... 4 1.2 Assembler Syntax ............................................................................................................................... 5 CHAPTER 2 ENVIRONMENT VARIABLES AND DIRECTORY STRUCTURE OF THE DEVELOPMENT ENVIRONMENT ............................................................... 7 2.1 FETOOL ............................................................................................................................................. 8 2.2 FELANG ............................................................................................................................................. 9 2.3 TMP .................................................................................................................................................. 10 2.4 INC911 .............................................................................................................................................. 11 2.5 OPT911 ............................................................................................................................................ 12 2.6 Directory Structure of the Development Environment ...................................................................... 13 CHAPTER 3 STARTUP METHOD .................................................................................. 15 3.1 fasm911s Commands ....................................................................................................................... 16 3.2 Specifying a File ............................................................................................................................... 17 3.3 Handling of File Names .................................................................................................................... 18 3.3.1 Format for Specifying a File Name .............................................................................................. 19 3.3.2 Specifying a File Name with File Name Components Omitted .................................................... 20 3.4 Option File ........................................................................................................................................ 21 3.5 Comments Allowed in an Option File ................................................................................................ 22 3.6 Default Option File ............................................................................................................................ 23 3.7 Termination Code ............................................................................................................................. 24 CHAPTER 4 STARTUP OPTIONS .................................................................................. 25 4.1 Rules for Startup Options ................................................................................................................. 26 4.2 Startup Option List ............................................................................................................................ 27 4.3 Details of the Startup Options ........................................................................................................... 29 4.4 Options Related to Objects and Debugging ..................................................................................... 30 4.4.1 -o, -Xo .......................................................................................................................................... 31 4.4.2 -g, -Xg .......................................................................................................................................... 32 4.5 Options Related to Listing ................................................................................................................. 33 4.5.1 -l, -lf, -Xl ....................................................................................................................................... 34 4.5.2 -pl, -pw ......................................................................................................................................... 35 4.5.3 -linf, -lsrc, -lsec, -lcros .................................................................................................................. 36 4.5.4 -linc, -lexp .................................................................................................................................... 38 4.5.5 -tab .............................................................................................................................................. 39 4.6 Options Related to the Preprocessor ...............................................................................................
Load more

Recommended publications
  • E0C88 CORE CPU MANUAL NOTICE No Part of This Material May Be Reproduced Or Duplicated in Any Form Or by Any Means Without the Written Permission of Seiko Epson
    MF658-04 CMOS 8-BIT SINGLE CHIP MICROCOMPUTER E0C88 Family E0C88 CORE CPU MANUAL NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. Please note that "E0C" is the new name for the old product "SMC". If "SMC" appears in other manuals understand that it now reads "E0C". © SEIKO EPSON CORPORATION 1999 All rights reserved. CONTENTS E0C88 Core CPU Manual PREFACE This manual explains the architecture, operation and instruction of the core CPU E0C88 of the CMOS 8-bit single chip microcomputer E0C88 Family. Also, since the memory configuration and the peripheral circuit configuration is different for each device of the E0C88 Family, you should refer to the respective manuals for specific details other than the basic functions.
    [Show full text]
  • Cmp Instruction in Assembly Language
    Cmp Instruction In Assembly Language booby-trapsDamien pedaling sound. conjointly? Untidiest SupposableGraham precools, and uncleansed his ilexes geologisesNate shrouds globed her chokos contemptuously. espied or It works because when a short jump if the stack to fill out over an implied subtraction of assembly language is the arithmetic operation of using our point Jump if actual assembler or of assembly is correct results in sequence will stay organized. If you want to prove that will you there is cmp instruction in assembly language, sp can also accept one, it takes quite useful sample programs in game reports to. Acts as the instruction pointer should be checked for? Please switch your skills, cmp instruction cmp in assembly language. To double word register onto the next step process in assembly language equivalent to collect great quiz. The comparisons and the ip value becomes a row! Subsequent generations became new game code starts in main program plays a few different memory locations declared with. Want to switch, many commands to thumb instructions will not examine the difference between filtration and in assembly language are used as conditional jumps are calls to the call. Note that was no difference in memory operands and its corresponding comparison yielded an explicit, xor is running but also uses a perennial study guide can exit? Each question before you want to see the control flow and play this instruction cmp in assembly language? This value off this for assembly language, cmp instruction in assembly language? But shl can explicitly directed as efficient ways to compare values stored anywhere in terms indicated by cmp instruction in assembly language calling convention rules.
    [Show full text]
  • X86 Assembly Language Syllabus for Subject: Assembly (Machine) Language
    VŠB - Technical University of Ostrava Department of Computer Science, FEECS x86 Assembly Language Syllabus for Subject: Assembly (Machine) Language Ing. Petr Olivka, Ph.D. 2021 e-mail: [email protected] http://poli.cs.vsb.cz Contents 1 Processor Intel i486 and Higher – 32-bit Mode3 1.1 Registers of i486.........................3 1.2 Addressing............................6 1.3 Assembly Language, Machine Code...............6 1.4 Data Types............................6 2 Linking Assembly and C Language Programs7 2.1 Linking C and C Module....................7 2.2 Linking C and ASM Module................... 10 2.3 Variables in Assembly Language................ 11 3 Instruction Set 14 3.1 Moving Instruction........................ 14 3.2 Logical and Bitwise Instruction................. 16 3.3 Arithmetical Instruction..................... 18 3.4 Jump Instructions........................ 20 3.5 String Instructions........................ 21 3.6 Control and Auxiliary Instructions............... 23 3.7 Multiplication and Division Instructions............ 24 4 32-bit Interfacing to C Language 25 4.1 Return Values from Functions.................. 25 4.2 Rules of Registers Usage..................... 25 4.3 Calling Function with Arguments................ 26 4.3.1 Order of Passed Arguments............... 26 4.3.2 Calling the Function and Set Register EBP...... 27 4.3.3 Access to Arguments and Local Variables....... 28 4.3.4 Return from Function, the Stack Cleanup....... 28 4.3.5 Function Example.................... 29 4.4 Typical Examples of Arguments Passed to Functions..... 30 4.5 The Example of Using String Instructions........... 34 5 AMD and Intel x86 Processors – 64-bit Mode 36 5.1 Registers.............................. 36 5.2 Addressing in 64-bit Mode.................... 37 6 64-bit Interfacing to C Language 37 6.1 Return Values..........................
    [Show full text]
  • (PSW). Seven Bits Remain Unused While the Rest Nine Are Used
    8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI The Flags Register It is a 16-bit register, also called Program Status Word (PSW). Seven bits remain unused while the rest nine are used. Six are status flags and three are control flags. The control flags can be set/reset by the programmer. 1. DF (Direction Flag) : controls the direction of operation of string instructions. (DF=0 Ascending order DF=1 Descending order) 2. IF (Interrupt Flag): controls the interrupt operation in 8086µP. (IF=0 Disable interrupt IF=1 Enable interrupt) 3. TF (Trap Flag): controls the operation of the microprocessor. (TF=0 Normal operation TF=1 Single Step operation) The status flags are set/reset depending on the results of some arithmetic or logical operations during program execution. 1. CF (Carry Flag) is set (CF=1) if there is a carry out of the MSB position resulting from an addition operation or subtraction. 2. AF (Auxiliary Carry Flag) AF is set if there is a carry out of bit 3 resulting from an addition operation. 3. SF (Sign Flag) set to 1 when result is negative. When result is positive it is set to 0. 4. ZF (Zero Flag) is set (ZF=1) when result of an arithmetic or logical operation is zero. For non-zero result this flag is reset (ZF=0). 5. PF (Parity Flag) this flag is set to 1 when there is even number of one bits in result, and to 0 when there is odd number of one bits. 6. OF (Overflow Flag) set to 1 when there is a signed overflow.
    [Show full text]
  • AVR Control Transfer -AVR Branching
    1 | P a g e AVR Control Transfer -AVR Branching Reading The AVR Microcontroller and Embedded Systems using Assembly and C) by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi Chapter 3: Branch, Call, and Time Delay Loop Section 3.1: Branching and Looping (Branch Only) Additional Reading Introduction to AVR assembler programming for beginners, controlling sequential execution of the program http://www.avr-asm-tutorial.net/avr_en/beginner/JUMP.html AVR Assembler User Guide http://www.atmel.com/dyn/resources/prod documents/doc1022.pdf 2 | P a g e TABLE OF CONTENTS Instruction Set Architecture (Review) ...................................................................................................................... 4 Instruction Set (Review) ........................................................................................................................................... 5 Jump Instructions..................................................................................................................................................... 6 How the Direct Unconditional Control Transfer Instructions jmp and call Work ...................................................... 7 How the Relative Unconditional Control Transfer Instructions rjmp and rcall Work ................................................ 8 Branch Instructions .................................................................................................................................................. 9 How the Relative Conditional Control Transfer Instruction
    [Show full text]
  • Overview of IA-32 Assembly Programming
    Overview of IA-32 assembly programming Lars Ailo Bongo University of Tromsø Contents 1 Introduction ...................................................................................................................... 2 2 IA-32 assembly programming.......................................................................................... 3 2.1 Assembly Language Statements................................................................................ 3 2.1 Modes........................................................................................................................4 2.2 Registers....................................................................................................................4 2.2.3 Data Registers .................................................................................................... 4 2.2.4 Pointer and Index Registers................................................................................ 4 2.2.5 Control Registers................................................................................................ 5 2.2.6 Segment registers ............................................................................................... 7 2.3 Addressing................................................................................................................. 7 2.3.1 Bit and Byte Order ............................................................................................. 7 2.3.2 Data Types.........................................................................................................
    [Show full text]
  • Optimizing Subroutines in Assembly Language an Optimization Guide for X86 Platforms
    2. Optimizing subroutines in assembly language An optimization guide for x86 platforms By Agner Fog. Copenhagen University College of Engineering. Copyright © 1996 - 2012. Last updated 2012-02-29. Contents 1 Introduction ....................................................................................................................... 4 1.1 Reasons for using assembly code .............................................................................. 5 1.2 Reasons for not using assembly code ........................................................................ 5 1.3 Microprocessors covered by this manual .................................................................... 6 1.4 Operating systems covered by this manual................................................................. 7 2 Before you start................................................................................................................. 7 2.1 Things to decide before you start programming .......................................................... 7 2.2 Make a test strategy.................................................................................................... 9 2.3 Common coding pitfalls............................................................................................. 10 3 The basics of assembly coding........................................................................................ 12 3.1 Assemblers available ................................................................................................ 12 3.2 Register set
    [Show full text]
  • Assembly Language: IA-X86
    Assembly Language for x86 Processors X86 Processor Architecture CS 271 Computer Architecture Purdue University Fort Wayne 1 Outline Basic IA Computer Organization IA-32 Registers Instruction Execution Cycle Basic IA Computer Organization Since the 1940's, the Von Neumann computers contains three key components: Processor, called also the CPU (Central Processing Unit) Memory and Storage Devices I/O Devices Interconnected with one or more buses Data Bus Address Bus data bus Control Bus registers Processor I/O I/O IA: Intel Architecture Memory Device Device (CPU) #1 #2 32-bit (or i386) ALU CU clock control bus address bus Processor The processor consists of Datapath ALU Registers Control unit ALU (Arithmetic logic unit) Performs arithmetic and logic operations Control unit (CU) Generates the control signals required to execute instructions Memory Address Space Address Space is the set of memory locations (bytes) that are addressable Next ... Basic Computer Organization IA-32 Registers Instruction Execution Cycle Registers Registers are high speed memory inside the CPU Eight 32-bit general-purpose registers Six 16-bit segment registers Processor Status Flags (EFLAGS) and Instruction Pointer (EIP) 32-bit General-Purpose Registers EAX EBP EBX ESP ECX ESI EDX EDI 16-bit Segment Registers EFLAGS CS ES SS FS EIP DS GS General-Purpose Registers Used primarily for arithmetic and data movement mov eax 10 ;move constant integer 10 into register eax Specialized uses of Registers eax – Accumulator register Automatically
    [Show full text]
  • Arithmetic Flags and Instructions
    Arithmetic Flags and Instructions Chapter 6 S. Dandamudi Outline • Status flags • Application examples ∗ Zero flag ∗ PutInt8 ∗ Carry flag ∗ GetInt8 ∗ Overflow flag • Multiword arithmetic ∗ Sign flag ∗ Addition ∗ Auxiliary flag ∗ Subtraction ∗ Parity flag ∗ Multiplication • Arithmetic instructions ∗ Division ∗ Addition instructions • Performance: Multiword ∗ Subtraction instructions multiplication ∗ Multiplication instructions ∗ Division instructions 1998 S. Dandamudi Arithmetic: Page 2 To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Springer-Verlag, 1998. Status Flags • Six status flags monitor the outcome of arithmetic, logical, and related operations Flags Register FLAGS 3 2 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 0 9 8 7 6 5 4 3 2 109 8 7 6 5 4 3 2 1 0 V V I I I A V R N IO O D I T S Z 0 A 0 P 1 C EFLAGS 0 000 000000D P F C M F 0 T PL F F F F F F F F F Status Flags Control Flags System Flags CF = Carry Flag DF = Direction Flag TF = Trap Flag PF = Parity Flag IF = Interrupt Flag AF = Auxiliary Carry Flag IOPL = I/O Privilege Level ZF = Zero Flag NT = Nested Task SF = Sign Flag RF = Resume Flag OF = Overflow Flag VM = Virtual 8086 Mode AC = Alignment Check VIF = Virtual Interrupt Flag VIP = Virtual Interrupt Pending ID = ID Flag Instruction Pointer 31 16 15 0 EIP IP 1998 S. Dandamudi Arithmetic: Page 3 To be used with S. Dandamudi, “Introduction to Assembly Language Programming,” Springer-Verlag, 1998. Status Flags (cont’d) • Status flags are updated to indicate certain properties of the result ∗ Example: If the result is zero, zero flag is set • Once a flag is set, it remains in that state until another instruction that affects the flags is executed • Not all instructions affect all status flags ∗ add and sub affect all six flags ∗ inc and dec affect all but the carry flag ∗ mov, push, and pop do not affect any flags 1998 S.
    [Show full text]
  • CS221 Booleans, Comparison, Jump Instructions Chapter 6 Assembly Language Is a Great Choice When It Comes to Working on Individu
    CS221 Booleans, Comparison, Jump Instructions Chapter 6 Assembly language is a great choice when it comes to working on individual bits of data. While some languages like C and C++ include bitwise operators, several high-level languages are missing these operations entirely (e.g. Visual Basic 6.0). At times these operations can be quite useful. First we will describe some common bit operations, and then discuss conditional jumps. AND Instruction The AND instruction performs a Boolean AND between all bits of the two operands. For example: mov al, 00111011b and al, 00001111b The result is that AL contains 00001011. We have “multiplied” each corresponding bit. We have used AND for a common operation in this case, to clear out the high nibble. Sometimes the operand we are AND’ing something with is called a bit mask because wherever there is a zero the result is zero (masking out the original data), and wherever we have a one, we copy the original data through the mask. For example, consider an ASCII character. “Low” ASCII ignores the high bit; we only need the low 7 bits and we might use the high bit for either special characters or perhaps as a parity bit. Given an arbitrary 8 bits for a character, we could apply a mask that removes the high bit and only retains the low bits: and al, 01111111b OR Instruction The OR instruction performs a Boolean OR between all bits of the two operands. For example: mov al, 00111011b or al, 00001111b As a result AL contains 00111111. We have “Added” each corresponding bit, throwing away the carry.
    [Show full text]
  • Introduction to Assembly a User’S View of Computer Systems
    Introduction to Assembly A User’s View of Computer Systems 2 Courtesy: Guide to Assembly Language Programming in Linux, Sivarama P. Dandamudi, 2005 What is Assembly Language ? • Low-level programming language • Influenced by: • The architecture of the processor • The instruction set • Two basic types of processors • CISC (Complex Instruction Set Computers) • RISC (Reduced Instruction Set Computers) • Pentium is an example of a CISC processor • Assembler translates assembly to machine code • NASM is a popular assembler for x86 architecture 3 Advantage of High-Level Languages • Program development is faster • Programs are easier to maintain • Programs are portable so, why to program in the Assembly language ? 4 Why to program in Assembly ? • Efficiency • Time efficiency • Space efficiency • Direct hardware control 5 When is it Useful? • Practical purposes (embedded systems) • Cracking Personal Satisfaction 6 Example _start: mov ecx, [var1] cmp ecx, [var2] ; Data section begins jg check_third_var section .data mov ecx, [var2] var1 dd 40 var2 dd 20 check_third_var: var3 dd 30 cmp ecx, [var3] jg _exit section .text mov ecx, [var3] global _start _exit: mov ebx, ecx mov eax, 1 int 80h 7 IA – 32 Architecture (IA - Intel Architecture, i386) • 32 bit Registers • Logical and Arithmetic instructions (instruction set) • Fetch-decode-execute cycle • Addressing Modes • Registers • Immediate • Direct • Indirect 8 Fetch-decode-execute Fetch Execute Decode 9 Registers 32-bit, 16-bit, and 8-bit registers: . General registers . Control registers . Segment
    [Show full text]
  • CS107, Lecture 13 Assembly: Control Flow and the Runtime Stack
    CS107, Lecture 13 Assembly: Control Flow and The Runtime Stack Reading: B&O 3.6 This document is copyright (C) Stanford Computer Science and Nick Troccoli, licensed under Creative Commons Attribution 2.5 License. All rights reserved. Based on slides created by Marty Stepp, Cynthia Lee, Chris Gregg, and others. 1 Learning Goals • Learn how assembly implements loops and control flow • Learn how assembly calls functions. 2 Plan For Today • Control Flow • Condition Codes • Assembly Instructions • Break: Announcements • Function Calls and the Stack 3 mov Variants • mov only updates the specific register bytes or memory locations indicated. • Exception: movl writing to a register will also set high order 4 bytes to 0. • Suffix sometimes optional if size can be inferred. 4 No-Op • The nop/nopl instructions are “no-op” instructions – they do nothing! • No-op instructions do nothing except increment %rip • Why? To make functions align on nice multiple-of-8 address boundaries. “Sometimes, doing nothing is the way to be most productive.” – Philosopher Nick 5 Mov • Sometimes, you’ll see the following: mov %ebx, %ebx • What does this do? It zeros out the top 32 register bits, because when mov is performed on an e- register, the rest of the 64 bits are zeroed out. 6 xor • Sometimes, you’ll see the following: xor %ebx, %ebx • What does this do? It sets %ebx to zero! May be more efficient than using mov. 7 Plan For Today • Control Flow • Condition Codes • Assembly Instructions • Break: Announcements • Function Calls and the Stack 8 Control • In C, we have control flow statements like if, else, while, for, etc.
    [Show full text]