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Paul's Dissertation Adapting Hardware Systems by Means of Multi-Objective Evolution Dissertation A thesis submitted to the Faculty of Computer Science, Electrical Engineering and Mathematics of the University of Paderborn in partial fulfillment of the requirements for the degree of Dr. rer. nat. by Paul Kaufmann Paderborn, Germany Date of submission: 21.05.2013 Supervisor: Prof. Dr. Marco Platzner Reviewers: Prof. Dr. Marco Platzner Prof. Dr. Jim Tørresen Prof. Dr. Franz Rammig Additional members of the oral examination committee: Prof. Dr. Christian Plessl Dr. Theodor Lettmann Date of submission: 21.05.2013 Date of public examination: 08.07.2013 ii Acknowledgment I would like to thank my advisor, Prof. Dr. Marco Platzner, for his guidance, support, and advice. I have greatly benefited from working with him and I am highly appreciative the opportunities I have had at his research group. I also would like to thank: • Prof. Jim Torresen, for the fruitful collaboration, the opportunities to visit his research group, and for serving as a reviewer for my dissertation. • Prof. Franz Rammig, for serving as a reviewer for my dissertation. • Prof. Christian Plessl, for the many inspiring discussions and for serving as a reviewer for my dissertation. • Dr. Theodor Lettmann for serving as a reviewer for my dissertation. • Prof. Kyrre Glette, for the excellent joint work we have done together and for the continued collaboration. • Prof. Bernhard Sick, for the support and patient introduction to the world of data mining. • My colleagues Andreas Agne, Tobias Beisel, Alexander Boschmann, Klaus Danne, Stephanie Drzevitzky, Heiner Giefers, Mariusz Grad, Marcus Happe, Tobias Kenter, Enno Lübbers, Sebastian Meisner, Lars Schäfers, and Tobias Schumacher for discussions, and for valuable and constructive suggestions. • My student assistants Tobias Knieper, Sven Kurras, Daniel Breitlauch, Bertrand Defo, and Jens Lischka, as well as the Bachelor, Master, and Diploma students I have supervised, for helping me implement and evaluate the manifold aspects of hardware evolution. • The Deutsche Forschungsgemeinschaft (DFG), for funding the priority program “Organic Com- puting” (SPP1183) and the Allianz Industrieforschung, for funding projects on novel prostheses and prosthesis control (KF2071402-KM9, KF2071403-KM9, KF2071414-KM1). Finally, I would like to thank my parents and my sisters Anna and Helene for their support, and my wife Monika, for her continuous care and encouragement. iii Abstract Reconfigurable circuits have opened up a fundamentally new way of creating adaptable electronic systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as “Evolvable Hardware” (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles which have not yet been seen in conventional engineering. In this thesis, we present new and fundamental work on a holistic Evolvable Hardware approach, motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. Adaptation to gradual changes, such as variations in the distribution of the input data, can be handled by simulated evolution, but adaptation to radical changes, such as fluctu- ations in resource requirements, needs almost a complete re-evolution. To solve the challenge of different adaptation speeds, we propose a unified approach based on multi-objective evolution. In our method, we evolve and propagate candidate solutions that are diverse in objectives that may experience radical changes. In case of a radical event, a candidate solution that comes closest to meeting the new requirements will be instantiated. Afterwards, the evolutionary algorithm proceeds with the continuous optimization and evolution of diverse solutions. In our work, we focus on the algorithmic challenges of multi-objective hardware evolution. Em- ploying the Cartesian Genetic Programming (CGP) model for circuit encoding, we introduce a meaningful recombination operator. This recombination operator enables the use of Pareto based multi-objective evolutionary algorithms (MOEA) for hardware design. As scalability becomes chal- lenging with multi-objective hardware design, we introduce techniques such as objective scaling and global- and local-search periodization to achieve a better computation time. Additionally, we en- hance the evolution of structured functions by the automatic acquisition and reuse of subfunctions and investigate age- and cone-based subfunction acquisition. We demonstrate our methods on hardware classifier adaptation, compensation for the impact of architecture reconfiguration on classification accuracy, and the optimization of processor execution time and energy consumption. v Zusammenfassung Rekonfigurierbare Logikbausteine eröffnen neue Perspektiven für autonome Systeme. Kombiniert mit den Methoden der künstlichen Intelligenz, können rekonfigurierbare Logikbausteine auf ele- gante Weise dazu benutzt werden, Veränderungen in der Verteilung der Eingabedaten und der Anforderung an die Systemressourcen sowie Fehler in der Hardware zu kompensieren. Bekannt unter dem Begriff Evolvable Hardware, hat dieses Prinzip auf eindrucksvolle Weise das Entdecken neuer Entwurfsprinzipien und neuartiger sowie leistungsfähiger Lösungen für bestehende Ingenieur- saufgaben aufgezeigt. In dieser Arbeit präsentieren wir einen ganzheitlichen Ansatz für Evolvable Hardware. Unsere Moti- vation gründet in der Einsicht, dass es mehrere Zeitebenen geben kann in denen sich ein autonomes System anpassen soll. Während kontinuierliche Veränderungen mit niedrigen Veränderungsraten– wie sie häufig in der Natur vorkommen–durch kontinuierliche Optimierung kompensiert werden können, bedürfen rasche Veränderungen im Voraus berechneter Lösungen, wie etwa Veränderungen in den Systemressourcen. Um die Herausforderung der verschiedenen Veränderungs- und Adapta- tionsraten aufzulösen, setzen wir auf einen einheitlichen Mechanismus basierend auf multikriterieller Optimierung. Der multikriterielle Optimierer verbessert kontinuierlich die bestehende Lösung und kompensiert damit Variationen mit niedriger Veränderungsrate. Gleichzeitig evolviert der Algo- rithmus für Zielfunktionen, die raschen Veränderungen ausgesetzt sind, verschiedenartige Lösun- gen. Somit kann im Falle einer schnellen Änderung, z. B. der benutzbaren Rechenressourcen, eine geeignetere und bisher inaktive Lösung die aktive Lösung ersetzen. Anschließend fährt der Algorithmus mit der kontinuierlichen Verbesserung und Optimierung fort. In unserer Arbeit konzentrieren wir uns hauptsächlich auf die algorithmischen Aspekte der Evo- lution von rekonfigurierbaren Schaltungen. Dazu erweitern wir das populäre Modell für digitale Schaltungen, die Kartesische Genetische Programmierung, um einen strukturbasierten Rekombina- tionsoperator. Dies erlaubt uns den Einsatz globaler Optimierer und damit auch der modernen Pareto-basierten evolutionären Algorithmen für den Schaltungsentwurf. Zur Kompensation der dabei auftretenden langsameren Konvergenz führen wir die Skalierung von Optimierungskriterien und ein Periodisierungsschema ein, das die Konvergenzperformance lokaler Optimierer mit den Eigenschaften globaler Optimierer verbindet. Weiterhin beschleunigen wir den Schaltungsentwurf durch die automatische Identifikation und Wiederverwendung von Substrukturen. Dabei unter- suchen wir struktur- und zeitbehaftete Identifikationsmechanismen. Die Performance unserer Verfahren und Methoden verifizieren wir zum einen im Bereich der Mus- tererkennung. Hier evolvieren wir Hardwareklassifizierer und vergleichen ihre Erkennungsraten mit einer repräsentativen Auswahl an leistungsfähigen Mustererkennungsalgorithmen. Mit der Auswer- tung gesammelter statistischer Daten können wir weiterhin die Erkennungsraten während der Rekon- figuration eines Hardwareklassifizierers verbessern. Zum anderen benutzen wir unsere Methoden, um die Ausführungszeiten und den Energieverbrauch eines Prozessors zu minimieren, indem wir die Adressumsetzungsfunktion eines Prozessorcaches evolvieren. vii Contents List of Figures xi List of Tables xiii 1 Introduction 1 1.1 The Evolvable Hardware Principle ............................ 1 1.2 Challenges of Evolvable Hardware............................. 3 1.3 Thesis Contributions ................................... 6 1.4 Thesis Organization .................................... 8 2 Evolutionary Algorithms 11 2.1 Historical overview..................................... 14 2.1.1 Evolutionary Programming ............................ 15 2.1.2 Evolutionary Strategies .............................. 15 2.1.3 Genetic Algorithms................................. 16 2.1.4 Genetic Programming ............................... 17 2.2 Multi-objective Evolutionary Algorithms......................... 18 2.2.1 Multi-objective Optimization Terminology.................... 18 2.2.2 Non-Dominated Sorting Genetic Algorithm II.................. 20 2.2.3 Strength Pareto Evolutionary Algorithm 2.................... 22 2.3 Variants of Specialized Evolutionary Algorithms..................... 23 2.3.1 Parallel Evolutionary Algorithms......................... 23 2.3.2 Hybrid Evolutionary Algorithms ......................... 23 2.4 Performance Analysis ................................... 24 2.4.1 The Computational Effort............................. 24 2.4.2 Comparing
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