CX28500 Multichannel Synchronous Communications Controller Data Sheet
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CX28500 Multichannel Synchronous Communications Controller Data Sheet ® 28500-DSH-002-C Mindspeed Technologies October 2006 Mindspeed Proprietary and Confidential Ordering Information Model Number Package Operating Temperature CX28500EBG 35 mm TBGA –40 – 85 °C CX28500G-12* 35 mm TBGA –40 – 85 °C (RoHS compliant) *The G in the part number indicates that this is an RoHS compliant package. Refer to www.mindspeed.com for additional information. Revision History Revision Level Date Description 500052A — July 2001 Created. 500052B — February 2002 Updated to Revision B. 500052C — July 2002 Updated to Revision C. 28500-DSH-002-A — November 2002 Formerly document number 500052D. 28500-DSH-002-B — June 2004 Updated and made various corrections. 28500-DSH-002-C — October 2006 Added RoHS information. Updated format. ® 28500-DSH-002-C Mindspeed Technologies ii Mindspeed Proprietary and Confidential CX28500 Multichannel Synchronous Communications Controller The CX28500 is an advanced Multichannel Synchronous Distinguishing Features Communications Controller. It formats and deformats up to 1024 High- 1024-channel HDLC controller level Data Link Control (HDLC) channels in a CMOS integrated circuit. OSI Layer 2 protocol support CX28500 operates at Layer 2 of the Open Systems Interconnection (OSI) General purpose HDLC (ISO 3309) protocol reference model. It provides a comprehensive, high-density X.25 (LAPB) solution for processing of HDLC channels for internetworking applications Frame relay (LAPF/ANSI T1.618) such as Frame Relay, Integrated Services Digital Network (ISDN), D- ISDN D-channel (LAPD/Q.921) channel signaling, X.25, Signaling System 7 (SS7), Data Exchange ISLP support Interface (DXI), Inter System Link Protocol (ISLP), and LAN/WAN data 32 Independent serial interfaces, which transport. Under minimal Host supervision, CX28500 manages table-like support: data structures of channel data buffers in Host memory by performing Mixed Data Rates (combination of T1/E1/ Direct Memory Access (DMA) of up to 1024 channels. T3/E3, etc.) as long as they do not exceed each port’s respective bandwidth CX28500 interfaces to 32 independent serial data streams, such as T1/E1 limitation and the overall device bandwidth of 390 Mbps per direction signals. It then transfers data across the popular 32-bit or 64-bit Peripheral 32 T1/E1 data streams Component Interface (PCI) bus to system memory at a rate up to 66 MHz. 6 HSSI interfaces (52 Mbps) The CX28500 has an aggregate data throughput of 390 Mbps. Each serial DC to 13.0 Mbps serial interfaces interface can be operated up to 13.0 MHz. Six Serial Interfaces can be 32 x 8.192 MHz TDM busses operated at rates up to 52 MHz. Logical channels can be mapped as any Configurable logical channels combination of Digital Signal Level 0 (DS0) time slots to support ISDN Standard DS0 (56, 64 Kbps) hyperchannels (N x 64 Kbps). Additionally, logical channels can operate in Subchanneling (N x 8 Kbps) subchanneling mode (N x 8 Kbps) by mapping a combination of DS0 time Hyperchannel (N x 64 Kbps) slots and/or the individual bits of a DS0 time slot (8 bits). For example, a Unchannelized mode 56 Kbps channel can be achieved by mapping 7 bits out of 8 possible bits Per-channel protocol mode selection in a time slot (7 x 8 Kbps = 56 Kbps). CX28500 also includes a 32-bit Non-FCS mode expansion port for bridging the PCI bus to local microprocessors or 16-bit FCS mode peripherals. A Joint Test Action Group (JTAG) port enables boundary- 32-bit FCS mode scan testing to replace bed-of-nails board testing. Transparent mode (unformatted data) Hardware Flow Control (CTS) Functional Block Diagram Selectable Endian configuration on data Per-channel DMA buffer management Table-like data structures HOST Variable size transmit/receive FIFO 0 Interface Rx Line Per-channel message length check (PCI) Processor RSLP Select no length checking Device Select from three 14-bit registers to Configuration Registers compare message length RxDMA Serial TSBUS and Interface or Direct PCI bus interface PCI TxDMA Unit PCM 32/64-bit, 33/66 MHz operation Interface (SIU) Highway Bus master and slave operation Tx Line Processor PCI Version 2.1 PCI BUS PCI TSLP Host back-to-back transaction over the PCI Configuration Interface Physical Space HSSI interfaces (52 Mbps) (Function 0) 31 Local expansion bus interface (EBUS) 32-bit multiplexed address/data bus TSBUS Test Support of 64-bit ECC host memory EXP BUS JTAG Access Low power, 3.3 V CMOS operation JTAG boundary scan access port 35 mm x 35 mm 580-pin BGA Local BUS Available in Green (RoHS compliant) as well as standard version ® 28500-DSH-002-C Mindspeed Technologies iii Mindspeed Proprietary and Confidential Table of Contents Table of Contents. .iv List of Figures . .xi List of Tables . xiii 1.0 Introduction . 1 1.1 CX28500’s Operational Modes . .2 1.2 CX28500 Serial Port Throughput Limits . .3 1.3 CX28500’s Bus Interfaces . .5 1.3.1 PCI—Peripheral Components Interface . .5 1.3.2 EBUS—Local Expansion Bus . .5 1.3.3 TSBUS—Time Slot Bus . .5 1.4 CX28500 Layering Model . .6 1.5 CX28500’s Applications. .7 1.6 CX28500 Applications Examples . .8 1.6.1 T1/T3 WAN Access. .8 1.6.2 T3/E3 Frame Relay Switch . .9 1.6.3 128 Port DSL Access Concentrator . .11 1.6.4 SONET/SDH Mapper. .11 1.6.5 Line Card SONET/ATM SAR . .13 1.7 Feature Summary . .14 1.8 System Overview. .16 1.9 Block Diagram. .18 1.10 Receive Data Path . .19 1.11 Transmit Data Path . .19 1.12 Pin Configuration. .21 1.13 CX28500 Hardware Signals Description . .28 2.0 Internal Architecture . 36 2.1 Serial Interface Unit (SIU) . .37 2.2 Serial Line Processor (SLP) . .38 2.3 Direct Memory Access Controller . .39 2.3.1 General Feature List . .39 2.4 Interrupt Controller . .40 3.0 Host Interface . 41 3.1 PCI Interface . .42 ® 28500-DSH-002-C Mindspeed Technologies iv Mindspeed Proprietary and Confidential Table of Contents 3.1.1 PCI Initialization . .42 3.1.2 PCI Bus Operations . .42 3.1.3 Fast Back-to-Back Transactions . .43 3.1.3.1 Operation Mode . .43 3.1.3.2 Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-Back Transactions . .43 3.1.4 PCI Configuration Space . .43 3.2 PCI Configuration Registers . .45 3.2.1 PCI Master and Slave . .45 3.2.1.1 Register 0, Address 00h. ..