DOCSLIB.ORG

Introduction to High-Level Synthesis ECE 699: Lecture 12

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

ECE 699: Lecture 12 Introduction to High-Level Synthesis Required Reading The ZYNQ Book • Chapter 14: Spotlight on High-Level Synthesis • Chapter 15: Vivado HLS: A Closer Look S. Neuendorffer and F. Martinez-Vallina, Building Zynq Accelerators with Vivado High Level Synthesis, FPGA 2013 Tutorial Recommended Reading G. Martin and G. Smith, “High-Level Synthesis: Past, Present, and Future,” IEEE Design & Test of Computers, IEEE, vol. 26, no. 4, pp. 18–25, July 2009. Vivado Design Suite Tutorial, High-Level Synthesis, UG871, Nov. 2014 Vivado Design Suite User Guide, High-Level Synthesis, UG902, Oct. 2014 Introduction to FPGA Design with Vivado High-Level Synthesis, UG998, Jul. 2013. Behavioral Synthesis I/O Target Behavior Library Algorithm Behavioral Synthesis RTL Design Logic Classic RTL Synthesis Design Flow Gate level Netlist 4 Need for High-Level Design • Higher level of abstraction • Modeling complex designs • Reduce design efforts • Fast turnaround time • Technology independence • Ease of HW/SW partitioning 5 Platform Mapping SW/HW Partitioning Program Hardware Software (executed in (executed in the reconfigurable the microprocessor processor system) system) ECE 448 – FPGA and ASIC Design with VHDL 6 SW/HW Partitioning & Coding Traditional Approach Specification SW/HW Partitioning SW Coding HW Coding SW Compilation HW Compilation SW Profiling HW Profiling ECE 448 – FPGA and ASIC Design with VHDL 7 SW/HW Partitioning & Coding New Approach Specification SW/HW Coding SW/HW Partitioning SW Compilation HW Compilation SW Profiling HW Profiling ECE 448 – FPGA and ASIC Design with VHDL 8 Advantages of Behavioral Synthesis • Easy to model higher level of complexities • Smaller in size source compared to RTL code • Generates RTL much faster than manual method • Multi-cycle functionality • Loops • Memory Access 9 Short History of High-Level Synthesis Generation 1 (1980s-early 1990s): research period Generation 2 (mid 1990s-early 2000s): • Commercial tools from Synopsys, Cadence, Mentor Graphics, etc. • Input languages: behavioral HDLs Target: ASIC Outcome: Commercial failure Generation 3 (from early 2000s): • Domain oriented commercial tools: in particular for DSP • Input languages: C, C++, C-like languages (Impulse C, Handel C, etc.), Matlab + Simulink, Bluespec • Target: FPGA, ASIC, or both Outcome: First success stories 10 Hardware-Oriented High-Level Languages • C-Based System level languages • Commercial • Handel C -- Celoxica Ltd. • Impulse C -- Impulse Accelerated Technologies • Carte C – SRC Computers • SystemC -- The Open SystemC Initiative • Research • Streams-C -- Los Alamos National Laboratory • SA-C -- Colorado State University, University of California, Riverside, Khoral Research, Inc. • SpecC – University of California, Irvine and SpecC Technology Open Consortium 11 Other High-Level Design Flows • Matlab-based • AccelChip DSP Synthesis -- AccelChip • System Generator for DSP -- Xilinx • GUI Data-Flow based • Corefire -- Annapolis Microsystems • Java-based • Commercial • Forge -- Xilinx • Research • JHDL – Brigham Young University 12 Handel-C Overview • High-level language based on ISO/ANSI-C for the implementation of algorithms in hardware • Allows software engineers to design hardware without retraining • Clean extensions for hardware design including flexible data widths, parallelism and communications • Well defined timing model • Each statement takes a single clock cycle • Includes extended operators for bit manipulation, and high-level mathematical macros (including floating point) 13 Handel-C/ANSI-C Comparisons ANSI-C HANDEL-C Handel-C Standard Library ANSI-C Standard Preprocessors Library i.e. #define Parallelism Pointers Structures Arbitrary width Recursion ANSI-C Constructs variables for, while, if, switch Arrays Bitwise logical operators Enhanced bit Floang Point Logical operators manipulaon Arithme=c operators RAM, ROM Funcons Signals Interfaces 14 Handel-C Design Flow Executable Specificaon Handel-C VHDL Synthesis EDIF EDIF Place & Route 15 Different Levels of C/C++ Synthesis Abstraction + More abstract, less + implementation- C Untimed C Domain / specific C (Non-implementation-specific) e r u P d e t + n C + Timed C Domain e m C / m (Implementation-specific) e t g C s u y A S L D g o H l RTL Domain i r Less abstract, more V (Implementation-specific) e d implementation- V n specific a The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) 16 Pure Untimed C/C++ Design Flow Verilog / RTL Gate-level User interaction VHDL RTL Synthesis netlist and guidence ASIC target Pure C/C++ Pure C/C++ Auto-generated, Synthesis implementation-specific FPGA target - Non-implementation-specific - Easy to create Verilog / RTL LUT/CLB- - Fast to simulate VHDL RTL Synthesis level netlist - Easy to modify The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) 17 Catapult C (2004-2011) Calypto Design Systems (2011-2015) (2015-present) 18 Catapult C • Catapult C automatically converts un-timed C/C++ descriptions into synthesizable RTL. ECE 448 – FPGA and ASIC Design with VHDL 19 SystemC -based design-flow alternatives Implementation specific, relatively slow to simulate, relatively difficult to modify Auto-RTL Verilog / RTL Translation VHDL RTL Synthesis Gate-level SystemC netlist SystemC Synthesis Alternative SystemC flows 20 SystemC Evolution System Untimed Algorithmic 0 . 2 C Behavioral/ m e Transaction- t s level y S Timed C m 0 e . RTL t 1 s y S The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) 21 Reconfigurable Supercomputers ECE 448 – FPGA and ASIC Design with VHDL 22 What is a Reconfigurable Computer? Microprocessor system Reconfigurable system . µP µP FPGA . FPGA µP µP . FPGA . FPGA memory memory memory memory I/O Interface Interface I/O ECE 448 – FPGA and ASIC Design with VHDL 23 Reconfigurable Supercomputers Machine Released SRC 6 from 2002 SRC Computers Cray XD1 from 2005 from Cray SGI Altix from 2005 SGI SRC 7 from 2006 SRC Computers, Inc, 24 Pros and cons of reconfigurable computers + can be programmed using high-level programming languages, such as C, by mathematicians & scientist themselves + facilitates hardware/software co-design + shortens development time, encourages experimentation and complex optimizations + allows sharing costs among users of various applications - high entry cost (~$100,000) - hardware aware programming - limited portability - limited availability of libraries - limited maturity of tools 25 SRC Programming Model Microprocessor FPGA Libraries of macros function_1 main.c macro_1 macro_2 macro_1(a, b, c) macro_3 macro_4 ………………………. function_1() macro_2(b, d) VHDL macro_2(c, e) function_2() FPGA function_2 I/O a macro_3(s, t) Macro_1 ANSI C macro_1(n, b) b c macro_4(t, k) Macro_2 Macro_2 MAP C (subset of ANSI C) d e I/O 26 SRC Compilation Process Application sources Macro sources .c or .f files .mc or .mf files . vhd or .v files HDL sources .v files Logic synthesis µP Compiler MAP Compiler Netlists . ngo files Object .o files .o files files Place & Route Linker .bin files Configuration Application bitstreams executable 27 Library Development - SRC LLL HLL HLL (ASM) (C, Fortran) (C, Fortran) µP system FPGA system HDL HLL HLL (VHDL, (C, Fortran) (C, Fortran) Verilog) Library Application Developer Programmer 28 SRC Programming Environment + very easy to learn and use + standard ANSI C + hides implementation details + very well integrated environment + mature - subset of C - legacy C code requires rewriting - C limitations in describing HW (paralellism, data types) - closed environment, limited portability of code to HW platforms other than SRC 29 Application Development for Reconfigurable Computers Program Entry Platform mapping Debugging & Verification Compilation Execution 30 Ideal Program Entry Function Program Entry ECE 448 – FPGA and ASIC Design with VHDL 31 Actual Program Entry Function Preferred SW/HW Architectures Partitioning Use of FPGA FPGA Resources Program Mapping (multipliers, Entry µP cores) Data Transfers Sequence of Run-time & Synchronization Reconfigurations Use of Internal SW/HW Interface and External Memories 32 Cinderella Story AutoESL Design Technologies, Inc. (25 employees) Flagship product: AutoPilot, translating C/C++/System C to VHDL or Verilog • Acquired by the biggest FPGA company, Xilinx Inc., in 2011 • AutoPilot integrated into the primary Xilinx toolset, Vivado, as Vivado HLS, released in 2012 “High-Level Synthesis for the Masses” 33 Vivado HLS High Level Language C, C++, System C Vivado HLS Hardware Description Language VHDL or Verilog HLS-Based Development and Benchmarking Flow Reference ImplementaAon in C Manual Modifications (pragmas, tweaks) Test Vectors HLS-ready C code High-Level Synthesis Functional HDL Code Verification Post Physical Implementation Place & Route FPGA Tools Results Timing Netlist Verification LegUp – Academic Tool for HLS – Open-source HLS Tool • Developed at the University of Toronto • Faculty supervisors: Jason H. Anderson and Stephen Brown • FPL Community Award 2014 – High-Level Synthesis from C to Verilog – Targets Altera FPGAs (extension to Xilinx relatively simple) – Two flows • Pure Hardware • Hardware/Software Hybrid = Tiger MIPS + hardware accelerator(s) + Avalon bus + shared on-chip and off-chip memory 36 Cryptol – New Language for Cryptology – Domain specific language for cryptology: Cryptol
Recommended publications
  • An Introduction to High-Level Synthesis

    An Introduction to High-Level Synthesis

    High-Level Synthesis An Introduction to High-Level Synthesis Philippe Coussy Michael Meredith Universite´ de Bretagne-Sud, Lab-STICC Forte Design Systems Daniel D. Gajski Andres Takach University of California, Irvine Mentor Graphics today would even think of program- Editor’s note: ming a complex software application High-level synthesis raises the design abstraction level and allows rapid gener- solely by using an assembly language. ation of optimized RTL hardware for performance, area, and power require- In the hardware domain, specification ments. This article gives an overview of state-of-the-art HLS techniques and languages and design methodologies tools. 1,2 ÀÀTim Cheng, Editor in Chief have evolved similarly. For this reason, until the late 1960s, ICs were designed, optimized, and laid out by hand. Simula- THE GROWING CAPABILITIES of silicon technology tion at the gate level appeared in the early 1970s, and and the increasing complexity of applications in re- cycle-based simulation became available by 1979. Tech- cent decades have forced design methodologies niques introduced during the 1980s included place-and- and tools to move to higher abstraction levels. Raising route, schematic circuit capture, formal verification, the abstraction levels and accelerating automation of and static timing analysis. Hardware description lan- both the synthesis and the verification processes have guages (HDLs), such as Verilog (1986) and VHDL for this reason always been key factors in the evolu- (1987), have enabled wide adoption of simulation tion of the design process, which in turn has allowed tools. These HDLs have also served as inputs to logic designers to explore the design space efficiently and synthesis tools leading to the definition of their synthe- rapidly.
  • Automatic Generation of Hardware for Custom Instructions

    Automatic Generation of Hardware for Custom Instructions

    Automatic Generation of Hardware for Custom Instructions by Philip Ioan Necsulescu Thesis submitted to the Faculty of Graduate and Postdoctoral Studies in partial fulfillment of the requirements for the degree of Master of Science in Systems Science Interdisciplinary studies Faculty of Graduate and Postdoctoral Studies © Philip Ioan Necsulescu, Ottawa, Canada, 2011 Table of Contents List of Figures ................................................................................................................................................ 3 Acknowledgements ....................................................................................................................................... 4 Abstract ......................................................................................................................................................... 5 Glossary ......................................................................................................................................................... 6 1 - Introduction ............................................................................................................................................. 8 2 - Background (Literature Review) ............................................................................................................ 12 2.1 – Applications of Custom Instructions .............................................................................................. 12 2.2 – Comparison of Automated HDL Generation Porjects ...................................................................
  • Xcell Journal Issue 50, Fall 2004

    Xcell Journal Issue 50, Fall 2004

    ISSUE 50, FALL 2004ISSUE 50, FALL XCELL JOURNAL XILINX, INC. Issue 50 Fall 2004 XcellXcelljournaljournal THETHE AUTHORITATIVEAUTHORITATIVE JOURNALJOURNAL FORFOR PROGRAMMABLEPROGRAMMABLE LOGICLOGIC USERSUSERS MEMORYMEMORY DESIGNDESIGN Streaming Data at 10 Gbps Control Your QDR Designs PARTNERSHIP 20 Years of Partnership Author! Author! Programmable WorldWorld 20042004 SOFTWARE Algorithmic C Synthesis The Need for Speed MANUFACTURING Lower PCB Mfg. Costs Optimize PCB Routability R COVER STORY FPGAs on Mars The New SPARTAN™-3 Make It You r ASIC The world’s lowest-cost FPGAs Spartan-3 Platform FPGAs deliver everything you need at the price you want. Leading the way in 90nm process technology, the new Spartan-3 devices are driving down costs in a huge range of high-capability, cost-sensitive applications. With the industry’s widest density range in its class — 50K to 5 Million gates — the Spartan-3 family gives you unbeatable value and flexibility. Lots of features … without compromising on price Check it out. You get 18x18 embedded multipliers for XtremeDSP™ processing in a low-cost FPGA. Our unique staggered pad technology delivers a ton of I/Os for total connectivity solutions. Plus our XCITE technology improves signal integrity, while eliminating hundreds of resistors to simplify board layout and reduce your bill of materials. With the lowest cost per I/O and lowest cost per logic cell, Spartan-3 Platform FPGAs are the perfect fit for any design … and any budget. MAKE IT YOUR ASIC The Programmable Logic CompanySM For more information visit www.xilinx.com/spartan3 Pb-free devices available now ©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
  • Catapult DS 1-10 2PG Datasheet US.Qxd

    Catapult DS 1-10 2PG Datasheet US.Qxd

    C-B ase d D e s i g n Catapult C Synthesis D ATASHEET Major product features: • Mixed datapath and control logic synthesis from both pure ANSI C++ and SystemC • Multi-abstraction synthesis supports untimed, transaction-level, and cycle-accurate modeling styles • Full-chip synthesis capabilities including pipelined multi-block subsystems and SoC interconnects • Power, performance, and area exploration and optimization • Push button generation of RTL verification infrastructure • Advanced top-down and bottom-up hierarchical design management Catapult C Synthesis produces high-quality RTL implementations from abstract • Full and accurate control over design specifications written in C++ or SystemC, dramatically reducing design and interfaces with Interface Synthesis verification efforts. technology and Modular IO • Interactive and incremental design Tackle Complexity, Accelerate Time to RTL, Reduce Verification Effort methodology achieves fastest path to optimal hardware Traditional hardware design methods that require manual RTL development and debugging are too time consuming and error prone for today’s complex designs. • Fine-grain control for superior The Catapult® C Synthesis tool empowers designers to use industry standard ANSI quality of results C++ and SystemC to describe functional intent, and move up to a more productive • Built-in analysis tools including abstraction level. From these high-level descriptions Catapult generates production Gantt charts, critical path viewer, and quality RTL. With this approach, full hierarchical systems comprised of both cross-probing control blocks and algorithmic units are implemented automatically, eliminating the typical coding errors and bugs introduced by manual flows. By speeding time • Silicon vendor certified synthesis to RTL and automating the generation of bug free RTL, the Catapult C Synthesis libraries and integration with RTL tool significantly reduces the time to verified RTL.
  • Embedded Processing Using Fpgas Agenda

    Embedded Processing Using Fpgas Agenda

    Embedded Processing Using FPGAs Agenda • Why FPGA Platform Based Embedded Processing • Embedded Use Models And Their FPGA Based Solutions • Architecture/Topology Choices • A Reoccurring Question: Hardware Or Software • Reconfigurable Hardware • Tool Flows For FPGA Based Embedded Systems 2 - Embedded Processing using FPGAs www.xilinx.com Agenda • Why FPGA Platform Based Embedded Processing • Embedded Use Models And Their FPGA Based Solutions • Architecture/Topology Choices • A Reoccurring Question: Hardware Or Software • Reconfigurable Hardware • Tool Flows For FPGA Based Embedded Systems 3 - Embedded Processing using FPGAs www.xilinx.com Why Use Processors In the First Place • Microcontrollers (µC) and Microprocessors (µP) Provide a Higher Level of Design Abstraction – Most µC functions can be implemented using VHDL or Verilog - downsides are parallelism & complexity – Using C/C++ abstraction & serial execution make certain functions much easier to implement in a µC • Discrete µCs are Inexpensive and Widely Used – µCs have years of momentum and software designers have vast experience using them 4 - Embedded Processing using FPGAs www.xilinx.com Why Embedded Design using FPGAs In Addition To The Universal Drive Towards Smaller Cheaper Faster With Less Power…. 1 Difficult to Find the Required Mix of Peripherals in Off the Shelf (OTS) Microcontroller Solutions •2 Selecting a Single Processor Core with Long Term Solution Viability is Difficult at Best •3 Without Direct Ownership of the Processing Solution, Obsolescence is Always a Concern
  • An Introduction to High-Level Synthesis

    An Introduction to High-Level Synthesis

    [3B2-8] mdt2009040008.3d 17/7/09 13:24 Page 8 High-Level Synthesis An Introduction to High-Level Synthesis Philippe Coussy Michael Meredith Universite´ de Bretagne-Sud, Lab-STICC Forte Design Systems Daniel D. Gajski Andres Takach University of California, Irvine Mentor Graphics today would even think of program- Editor’s note: ming a complex software application High-level synthesis raises the design abstraction level and allows rapid gener- solely by using an assembly language. ation of optimized RTL hardware for performance, area, and power require- In the hardware domain, specification ments. This article gives an overview of state-of-the-art HLS techniques and languages and design methodologies tools. 1,2 Tim Cheng, Editor in Chief have evolved similarly. For this reason, ÀÀ until the late 1960s, ICs were designed, optimized, and laid out by hand. Simula- THE GROWING CAPABILITIES of silicon technology tion at the gate level appeared in the early 1970s, and and the increasing complexity of applications in re- cycle-based simulation became available by 1979. Tech- cent decades have forced design methodologies niques introducedduring the 1980s included place-and- and tools to move to higher abstraction levels. Raising route, schematic circuit capture, formal verification, the abstraction levels and accelerating automation of and static timing analysis. Hardware description lan- both the synthesis and the verification processes have guages (HDLs), such as Verilog (1986) and VHDL for this reason always been key factors in the evolu- (1987), have enabled wide adoption of simulation tion of the design process, which in turn has allowed tools. These HDLs have also served as inputs to logic designers to explore the design space efficiently and synthesis tools leading to the definition of their synthe- rapidly.
  • High Level Synthesis with Catapult

    High Level Synthesis with Catapult

    High Level Synthesis with Catapult 8.0 Richard Langridge European AE Manager 21 st January 2015 Calypto Overview • Background – Founded in 2002 – SLEC released 2005 & PowerPro 2006 – Acquired Mentor’s Catapult HLS technology and team in 2011 • Operations – Headquarters in San Jose with R&D in California, Oregon, NOIDA India – Sales and support worldwide, with new support office opened in Korea • Technology – Patented Deep Sequential Analysis Technology for verification and power optimization – Industry leading High-Level Synthesis technology – 30 patents granted; 17 pending • Customers – Over 130 customers worldwide • FY14 Results - Record revenue 2 Calypto Design Systems Calypto Design Systems’ Platforms Catapult HL Design & Verification Platform PowerPro RTL Low Power Platform 3 Calypto Design Systems Why Teams Want to Adopt HLS • Accelerate design time by working at higher level of void func (short a[N], abstraction for (int i=0; i<N; i++) { if (cond) – z+=a[i]*b[i]; New features added in days not weeks else – Address complexity through abstraction • Cut verification costs with 1000x speedup vs RTL – Faster design simulation in higher level languages – Easier functional verification and debug • Determine optimal microarchitecture – Rapidly explore multiple options for optimal Power Performance Area (PPA) • Facilitate collaboration, reuse and creation of derivatives – Technology and architectural neutral design descriptions RTL are easily shared, modified and retargeted – HLS becoming an IP enabler 4 Calypto Design Systems Catapult Delivers
  • HDL and Programming Languages ■ 6 Languages ■ 6.1 Analogue Circuit Design ■ 6.2 Digital Circuit Design ■ 6.3 Printed Circuit Board Design ■ 7 See Also

    HDL and Programming Languages ■ 6 Languages ■ 6.1 Analogue Circuit Design ■ 6.2 Digital Circuit Design ■ 6.3 Printed Circuit Board Design ■ 7 See Also

    Hardware description language - Wikipedia, the free encyclopedia 페이지 1 / 11 Hardware description language From Wikipedia, the free encyclopedia In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.[citation needed] HDLs are standard text-based expressions of the spatial and temporal structure and behaviour of electronic systems. Like concurrent programming languages, HDL syntax and semantics includes explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as netlist languages used on electric computer-aided design (CAD). HDLs are used to write executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of being programming languages, when they are more-precisely classed as specification languages or modeling languages. Simulators capable of supporting discrete-event (digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are available. It is certainly possible to represent hardware semantics using traditional programming languages such as C++, although to function such programs must be augmented with extensive and unwieldy class libraries.
  • Automatic Instruction-Set Architecture Synthesis for VLIW Processor Cores in the ASAM Project

    Automatic Instruction-Set Architecture Synthesis for VLIW Processor Cores in the ASAM Project

    Automatic Instruction-set Architecture Synthesis for VLIW Processor Cores in the ASAM Project Roel Jordansa,∗, Lech J´o´zwiaka, Henk Corporaala, Rosilde Corvinob aEindhoven University of Technology, Postbus 513, 5600MB Eindhoven, The Netherlands bIntel Benelux B.V., Capronilaan 37, 1119NG Schiphol-Rijk Abstract The design of high-performance application-specific multi-core processor systems still is a time consuming task which involves many manual steps and decisions that need to be performed by experienced design engineers. The ASAM project sought to change this by proposing an auto- matic architecture synthesis and mapping flow aimed at the design of such application specific instruction-set processor (ASIP) systems. The ASAM flow separated the design problem into two cooperating exploration levels, known as the macro-level and micro-level exploration. This paper presents an overview of the micro-level exploration level, which is concerned with the anal- ysis and design of individual processors within the overall multi-core design starting at the initial exploration stages but continuing up to the selection of the final design of the individual proces- sors within the system. The designed processors use a combination of very-long instruction-word (VLIW), single-instruction multiple-data (SIMD), and complex custom DSP-like operations in or- der to provide an area- and energy-efficient and high-performance execution of the program parts assigned to the processor node. In this paper we present an overview of how the micro-level design space exploration interacts with the macro-level, how early performance estimates are used within the ASAM flow to determine the tasks executed by each processor node, and how an initial processor design is then proposed and refined into a highly specialized VLIW ASIP.
  • Advances in Architectures and Tools for Fpgas and Their Impact on the Design of Complex Systems for Particle Physics

    Advances in Architectures and Tools for Fpgas and Their Impact on the Design of Complex Systems for Particle Physics

    Advances in Architectures and Tools for FPGAs and their Impact on the Design of Complex Systems for Particle Physics Anthony Gregersona, Amin Farmahini-Farahania, William Plishkerb, Zaipeng Xiea, Katherine Comptona, Shuvra Bhattacharyyab, Michael Schultea a University of Wisconsin - Madison b University of Maryland - College Park fagregerson, farmahinifar, [email protected] fplishker, [email protected] fcompton, [email protected] Abstract these trends has been a rapid adoption of FPGAs in HEP elec- tronics. A large proportion of the electronics in the Compact The continual improvement of semiconductor technology has Muon Solenoid Level-1 Trigger, for example, are based on FP- provided rapid advancements in device frequency and density. GAs, and many of the remaining ASICs are scheduled to be Designers of electronics systems for high-energy physics (HEP) replaced with FPGAs in proposed upgrades [1]. have benefited from these advancements, transitioning many de- signs from fixed-function ASICs to more flexible FPGA-based Improvements in FPGA technology are not likely to end platforms. Today’s FPGA devices provide a significantly higher soon. Today’s high-density FPGAs are based on a 40-nm sil- amount of resources than those available during the initial Large icon process and already contain an order of magnitude more Hadron Collider design phase. To take advantage of the ca- logic than the FPGAs available at planning stage of the Large pabilities of future FPGAs in the next generation of HEP ex- Hadron Collider’s electronics. 32 and 22 nm silicon process periments, designers must not only anticipate further improve- technologies have already been demonstrated to be feasible; ments in FPGA hardware, but must also adopt design tools and as FPGAs migrate to these improved technologies their logic methodologies that can scale along with that hardware.
  • An Automated Flow to Generate Hardware Computing Nodes from C for an FPGA-Based MPI Computing Network

    An Automated Flow to Generate Hardware Computing Nodes from C for an FPGA-Based MPI Computing Network

    An Automated Flow to Generate Hardware Computing Nodes from C for an FPGA-Based MPI Computing Network by D.Y. Wang A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF BACHELOR OF APPLIED SCIENCE DIVISION OF ENGINEERING SCIENCE FACULTY OF APPLIED SCIENCE AND ENGINEERING UNIVERSITY OF TORONTO Supervisor: Paul Chow April 2008 Abstract Recently there have been initiatives from both the industry and academia to explore the use of FPGA-based application-specific hardware acceleration in high-performance computing platforms as traditional supercomputers based on clusters of generic CPUs fail to scale to meet the growing demand of computation-intensive applications due to limitations in power consumption and costs. Research has shown that a heteroge- neous system built on FPGAs exclusively that uses a combination of different types of computing nodes including embedded processors and application-specific hardware accelerators is a scalable way to use FPGAs for high-performance computing. An ex- ample of such a system is the TMD [11], which also uses a message-passing network to connect the computing nodes. However, the difficulty in designing high-speed hardware modules efficiently from software descriptions is preventing FPGA-based systems from being widely adopted by software developers. In this project, an auto- mated tool flow is proposed to fill this gap. The AUTO flow is developed to auto- matically generate a hardware computing node from a C program that can be used directly in the TMD system. As an example application, a Jacobi heat-equation solver is implemented in a TMD system where a soft processor is replaced by a hardware computing node generated using the AUTO flow.
  • Advances in Architectures and Tools for Fpgas and Their Impact on the Design of Complex Systems for Particle Physics

    Advances in Architectures and Tools for Fpgas and Their Impact on the Design of Complex Systems for Particle Physics

    Advances in Architectures and Tools for FPGAs and their Impact on the Design of Complex Systems for Particle Physics Anthony Gregersona, Amin Farmahini-Farahania, William Plishkerb, Zaipeng Xiea, Katherine Comptona, Shuvra Bhattacharyyab, Michael Schultea a University of Wisconsin - Madison b University of Maryland - College Park fagregerson, farmahinifar, [email protected] fplishker, [email protected] fcompton, [email protected] Abstract these trends has been a rapid adoption of FPGAs in HEP elec- tronics. A large proportion of the electronics in the Compact The continual improvement of semiconductor technology has Muon Solenoid Level-1 Trigger, for example, are based on FP- provided rapid advancements in device frequency and density. GAs, and many of the remaining ASICs are scheduled to be Designers of electronics systems for high-energy physics (HEP) replaced with FPGAs in proposed upgrades [1]. have benefited from these advancements, transitioning many de- signs from fixed-function ASICs to more flexible FPGA-based Improvements in FPGA technology are not likely to end platforms. Today’s FPGA devices provide a significantly higher soon. Today’s high-density FPGAs are based on a 40-nm sil- amount of resources than those available during the initial Large icon process and already contain an order of magnitude more Hadron Collider design phase. To take advantage of the ca- logic than the FPGAs available at planning stage of the Large pabilities of future FPGAs in the next generation of HEP ex- Hadron Collider’s electronics. 32 and 22 nm silicon process periments, designers must not only anticipate further improve- technologies have already been demonstrated to be feasible; ments in FPGA hardware, but must also adopt design tools and as FPGAs migrate to these improved technologies their logic methodologies that can scale along with that hardware.