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Resettable High-Speed Fuse Uses FET As a Sense Resistor Giovanni Romeo CIRCLE 520 Instituto Nazionale Di Geofisica E Vulcanologia, Rome, Italy

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Resettable High-Speed Fuse Uses FET As a Sense Resistor Giovanni Romeo CIRCLE 520 Instituto Nazionale Di Geofisica E Vulcanologia, Rome, Italy ideas for design INNOVATIVE DESIGNS FROM READERS Resettable High-Speed Fuse Uses FET As A Sense Resistor Giovanni Romeo CIRCLE 520 Instituto Nazionale di Geofisica e Vulcanologia, Rome, Italy his design idea describes a reset- table high-speed fuse that uses R1 Load T only a few off-the-shelf parts, 100k R2 resets itself after blowing, and doesn’t U1A require a special current-sense resistor. CD4069UB R1 + While the circuit has been designed to 12 10k V1 switch on a negative current from C1 Q1 30 V ground, it can easily be modified for 0.1 nF IRF640 use in a floating arrangement. CD4069UB +5 V The circuit shown in Fig. 1 uses a U1B U1C U1E power FET as a switch and, when satu- D1 34 5 6 9 811 10 1N4148 rated, as a sense resistor. When an D2 U1D excessive current flows through the FET, 1N4148 C2 the source-drain voltage increases and R3 10 F R4 U1F 1M 1M is sensed by inverter U1A. This decreas- CD4069UB R5 C3 es the gate potential, causing the drain 100k 1.5 nF 12 13 voltage to go even higher and the cir- cuit to drop out in a stable state. In this R6 state, almost no current flows through 100k the load. The speed of the fuse can be tuned by modifying capacitor C1, which low- 1. This resettable fuse uses the on-resistance of FET Q1 as the current-sense element. pass filters the signal from Q1’s drain. The fuse’s firing current can be made speed will decrease due to the FET’s gate roughly 1 µs when changing load resis- adjustable by inserting a resistive volt- capacitance, it should be compensated tor R2 from 10 to 1 Ω (Fig. 2). age divider between the inverter output with a capacitor. With the values shown Prior to the activation of the fuse, the and the transistor gate. Since the fuse in the schematic, the fuse blows in three-gate oscillator (U1C-E) is disabled 15 4 4 10 2 2 Current (A) Current (A) Current (A) 5 0 0 0 024 50.00 100.00 150.00 200.00 0.0 50.0 100.00 150.00 Time ( s) Time ( s) Time ( s) 3. If the overload condition is still present 4. During a successful fuse reset, the Ω 2. When the load is stepped from 10 to 1 , when the fuse attempts to reset itself, the current rises to its normal operating level µ the electronic fuse trips in roughly 1 s. load current rises to the trip point in 25 µs. in 25 µs. November 5, 2001 • ELECTRONIC DESIGN 85 IDEAS FOR DESIGN by gate U1B and diode D1. When the tenths of a second) sends a pulse to the blows again; this process takes 25 µs fuse “blows,” the oscillator begins oscil- inverter U1A input, attempting to reset (Fig. 3). If the short does not persist, the lating. This periodically (every few the fuse. If the short persists, the fuse current rises in 25 µs (Fig. 4). Spread-Spectrum DC-DC Converter Combats EMI Ken Yang CIRCLE 521 Maxim Integrated Products, 120 San Gabriel Dr., Sunnyvale, CA 94086 lectromagnetic radiation (called 4.7 H electromagnetic interference or 3.6 V input E EMI when unwanted) is emitted + by almost all electronic systems, 100 F 14 including switching regulators. The LXP MBR0520L From PN 9 11 conventional approach to suppressing generator CLK/SEL LXN 5V 13,15 0.5 A EMI is to block the radiation at its 1 POUT REF U1 source with a metallic or magnetic MAX1703 10 + + shield, or both. For switching regula- 4 1 F 220 220 0.22 F 16 OUT tors, you can further enhance suppres- ON Cer F F sion by adopting a spread-spectrum FB GND PGND 0.22 F pulse-width-modulation (SSPWM) 2 5 10,12 control scheme. In Fig. 1, the switching regulator IC (U1) has an external clock input. Dri- 1. To reduce EMI, this conventional step-up dc-dc converter employs spread-spectrum pulse- ving this input with a digital signal of width modulation (SSPWM) produced by the pseudorandom noise at the clock input. pseudorandom noise (PN) provides the regulator with a spread-spectrum 4 clock that reduces EMI. By spreading 3 1 A QA 3 1 A 1 6 2 4 2 QA 4 3 5 interference frequencies over a wide B QB B QB 5 5 2 range, this technique lowers the EMI QC QC U4B 2 Q 5 6 6 D 6 power density that is otherwise concen- J1 QD QD U4A 74HC86 Q BNC QE 10 QE 10 3 11 8 11 74HC86 CLK To pin 9 of U1 trated at a single clock frequency. 650-kHz 8 CLK QF CLK QF square 12 12 1 The PN generator spreads interfer- QG QG CLR wave 9 13 9 13 4 ence over a wide spectrum. Its key ele- CLR QH CLR QH PRE U2 U3 14 ment is a 16-bit shift register formed by VCC the series connection of two 8-bit shift 74HC164 74HC164 VCC U5A registers (U2 and U3), with feedback 100k 74HC74A from the XOR gate U4A (Fig. 2). The result is an almost random (pseudo- 2. This generator of pseudorandom noise (PN) produces a nominal 325-kHz clock signal for random) output, consisting of a repeat- the step-up dc-dc converter circuit in Figure 1. 3. The output-noise spectrum produced by the Fig. 1 circuit operating with a fixed-frequency control scheme contains strong peaks at the 4. An SSPWM control scheme produces less output noise in the Fig. 1 clock harmonics. circuit than the conventional fixed-frequency approach. 86 ELECTRONIC DESIGN • November 5, 2001 IDEAS FOR DESIGN ing sequence of ones and zeroes at a dB reduction in peak power density ple amplitude in the time domain nominal frequency of 650 kHz. The D- at about 300 kHz. Except for 9 mA of also remains unchanged. Output type flip-flop (U5) divides this frequen- extra current drawn by the PN gener- spectra demonstrate that a conven- cy by two, producing a nominal 325- ator, the regulator’s efficiency tional fixed-frequency clock (Fig. 3) kHz spread-spectrum clock signal to remains unchanged. (The efficiency produces considerably more noise the switching regulator. is 94% while delivering 0.5 A with a than does the spread-spectrum tech- Bench measurements show a 15- 3.6-V input and a 5-V output.) Rip- nique (Fig. 4). Low-Cost Programmable Key Lock Uses A PC-Hardware Monitor IC Sean Gilmour CIRCLE 522 Analog Devices, One Technology Way, Norwood, MA 02062 implicity is the key to a good ply voltages and a 5-bit VID code. It also dividers are embedded in a key that can security system design. The fol- includes a 10-bit digital-to-analog con- be inserted into the lock, as shown in S lowing is a simple yet powerful verter (DAC). In this application, the the figure. For simplicity, only details security system employing an ADM- ADM1024 is used to monitor seven relating to the ADM1024 and the key 1024 PC-hardware monitor as the key’s voltages provided by a digital key as are given in this diagram. decoder. well as to open a lock if the correct key The seven voltage-input channels are The ADM1024 was designed to mon- is inserted. each capable of measuring a voltage itor the local temperature, the die tem- The basic principle of this lock with 10-bit resolution. However, only perature of up to two Pentium proces- decoder is the division of a voltage into eight bits of data are available on the sors, and the speed of up to two fans. seven specific levels that can be mea- serial bus. Hence, the theoretical maxi- This device monitors up to seven sup- sured by the ADM1024. The voltage mum number of key combinations is READER SERVICE 85 88 ELECTRONIC DESIGN • November 5, 2001 IDEAS FOR DESIGN 7.2 × 1016! The number of different keys is limited to 4.4 × 1012 by practical Microcontroller Lock/unlock concerns, the given standard 1% resis- NMI mechanism tor values, and the allowance of a 16- DO Key inserted 2 +5 V LSB measurement span for each key I C/SMBus Lock/unlock combination. This is still a very secure 12 V system. 1 24 NTEST_OUT/ADD VIDO In production, keys could be created 2 23 2k 2k THERM VID1 by vapor deposition of resistive materi- 3 22 SDA VID2 al directly onto a circuit board. 4 21 SCL ADM1024 VID3 Absolute accuracy is not critical since 5 20 FAN1/AIN1 VID4 the resistors are used in a voltage 6 19 FAN2/AIN2 +VCCP1 divider. Resistors created in a batch will 7 18 CI +2.5VIN/D2+ match well, so their ratios can be pre- 8 17 GND VCCP2/D2– cisely defined. 9 16 VCC +5VIN The on-board temperature sensor 10 15 INT +12VIN can be used to measure the ambient 11 14 NTEST_IN/AOUT D1+ 12 13 temperature. This enables the calcula- RESET D1– tion of voltage changes caused by resis- tor-temperature drift if desired. This system has several advan- tages. Only two signal wires are The ADM1024 finds an unusual use for its power-supply-monitor inputs in the detection of required to communicate with the the seven analog voltages produced by the low-cost key. lock. The first enables the lock to tell the microcontroller that a key has can easily process all of the combi- can be authenticated in millisec- been inserted.
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