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Analog Devices' ADSP-Bf5xx Blackfin A BDTI Analysis of the Analog Devices ADSP-BF5xx by the staff of Berkeley Design Technology, Inc. Contents of this summary include: oped by Analog Devices and Intel. There as the ADSP-BF5xx throughout this text. • Introduction are two generations of Blackfin proces- However, because the ADSP-BF561 • Architecture sors which have slightly different contains two processor cores, some of • Memory System • Pipeline instruction sets and microarchitectures. the following analysis does not apply to • Addressing Due to these architectural differences, this dual-core family member. • Instruction Set the two generations are only partly As of late 2004, prices for ADSP- • Peripherals assembly-code compatible. BF5xx family members range from $5 to • BDTI Benchmark™ Performance: • Sample Execution Time Results As of late 2004, the ADSP-BF5xx $40 in 10,000-unit quantities. All five • Sample Cost-Performance Results family included five family members. ADSP-BF5xx family members are cur- • Sample Energy Efficiency Results The sole first-generation Blackfin pro- rently in full production. • Sample Memory Use Results cessor, the ADSP-BF535, achieves a • Conclusion clock speed of 350 MHz at 1.6 volts. Second-generation Blackfin processors Architecture Introduction include the ADSP-BF531, ADSP- The ADSP-BF5xx contains two The ADSP-BF5xx (Blackfin) is a BF532, ADSP-BF533, and ADSP- fixed-point data paths, two address gen- family of 16-bit fixed-point dual-MAC BF561. The second-generation parts eration units, and a program sequencer. processors from Analog Devices. The operate at up to 750 MHz at 1.45 volts. The ADSP-BF5xx also includes a data ADSP-BF5xx combines features typical ADSP-BF5xx family members are register file of eight 32-bit registers, as of low-power DSPs with features tradi- designed to operate over a range of clock well as two 40-bit accumulators and two tionally associated with general-purpose speeds and operating voltages and are address register files. The ADSP-BF5xx processors, such as privilege modes and able to switch dynamically between uses a load/store architecture: the data memory protection. The ADSP-BF5xx speeds via software. For example, a sin- paths generally take inputs from and targets power-sensitive applications, gle ADSP-BF533 chip can operate at return results to the data register file or such as cell phones; applications that speeds and voltages ranging from 750 the accumulators. require the functionality of both a DSP MHz at 1.45 volts to 100 MHz at 0.8 Collectively, the two ADSP-BF5xx and a general-purpose processor, such as volts. data paths include two multipliers automotive applications; and computa- For the purposes of this analysis, the (MAC0 and MAC1), two ALUs (ALU0 tionally intensive applications, such as Blackfin processor family is referred to and ALU1), and a single barrel shifter. consumer video equipment. One data path includes MAC0, ALU0, The ADSP-BF5xx uses a mixed- and the shifter; the other data path con- About BDTI width 16-/32-bit instruction set. These BDTI provides analysis and advice tains MAC1 and ALU1. The ADSP- instructions can be combined to form 64- to help companies develop, market, BF5xx can issue one SIMD instruction bit VLIW-style “multi-issue” instruc- and use signal processing technol- that uses the two ALUs or the two MAC tions. Multi-issue instructions can ogy. units in parallel, but it does not support include up to one 32-bit arithmetic BDTI is a trusted industry resource instructions that use two dissimilar exe- instruction and up to two 16-bit move for: cution units; for example, one ALU and instructions. The ADSP-BF5xx provides one MAC unit. • Independent benchmarking and single-instruction, multiple-data (SIMD) In addition to instructions that use competitive analysis instructions, including a dual 16 × 16 • Guidance for confident technology both ALUs or both MAC units in paral- multiply-accumulate and a variety of and business decisions lel, the ADSP-BF5xx supports SIMD video-oriented, eight-bit ALU opera- • Expert product development advice operations within each ALU and within tions. • Industry and technology seminars the shifter (but not within the MAC The ADSP-BF5xx is based on the and reports units). These SIMD operations allow an Micro Signal Architecture (MSA) • Advice and analysis that enable execution unit to perform two operations instruction set architecture jointly devel- credible, compelling marketing per cycle. Thus, it is possible to perform © 2004 BDTI (www.BDTI.com). All rights reserved. four operations per clock cycle using sustainable on-chip data bandwidth is 3 The programmer (or compiler) must both ALUs or two operations per clock billion 16-bit words per second at 750 specify the prediction for each branch. cycle using the shifter. However, the MHz for reads, or 1.5 billion 16-bit Instructions generally execute in one SIMD operations within the ALUs are words per second for writes. cycle in the absence of memory access- supported only as part of a SIMD opera- The ADSP-BF5xx address space is related delays and pipeline stalls. The tion across the data paths, so that both byte addressable. However, instructions most significant exceptions are the jump, ALUs must perform the same type of must be aligned on 16-bit boundaries, call, and most return instructions, which SIMD computation (e.g., a 16-bit add/ and loads and stores must maintain the require four or more cycles. subtract). appropriate alignment for the transfer: The ADSP-BF5xx generally pro- 8-, 16-, and 32-bit transfers must be cesses data as 16-bit values. Many aligned on 8-, 16-, and 32-bit boundaries, Instruction Set instructions support 32-bit data, how- respectively. The ADSP-BF5xx assembly lan- ever, and some support 40-bit data. For guage syntax is algebraic. The ADSP- example, a five-cycle 32 × 32 → 32 BF5xx assembly language is not com- multiply is supported. The ADSP-BF5xx Addressing patible with that of earlier Analog also supports a set of video-oriented The ADSP-BF5xx has two address Devices processors. operations that operate exclusively on 8- generation units that can each generate The ADSP-BF5xx uses both 16- and bit data. an independent address in each cycle. 32-bit instructions. Arithmetic instruc- The address generation units access two tions are generally 32 bits wide, but 32-bit register files that contain general- some have 16-bit variants; 16-bit-wide Memory System purpose address registers, stack pointers, arithmetic instructions offer less flexibil- All ADSP-BF5xx memory is orga- and special registers for modulo address- ity than their 32-bit counterparts. Load, nized into a single unified 32-bit address ing. store, and branch instructions are typi- space. However, the ADSP-BF5xx orga- The ADSP-BF5xx supports a variety cally 16 bits wide, but most have 32-bit nizes its level-one (L1) on-chip memory of addressing modes, including: register- variants that support long immediate into separate instruction and data banks. indirect, register-indirect with post- operands. The organization of the L1 memory increment or post-decrement, register- The ADSP-BF5xx instruction set is is a primary differentiator among ADSP- indirect indexed addressing with a short highly orthogonal. Most arithmetic BF5xx family members. Depending on or long immediate offset, register-indi- instructions can take operands from the the family member, the L1 memory is rect addressing with pre-decrement for data registers, the pointer registers, the comprised of up to five separate banks of stack pushes, and register-indirect accumulators, or immediate operands. memory organized as a modified Har- addressing with post-increment for stack Most arithmetic instructions support vard architecture. Up to three of the pops. The register-indirect mode sup- both 16-bit and 32-bit data. Most arith- memory banks are data SRAM banks, ports bit-reversed addressing. metic instructions also support SIMD some of which can be optionally config- The address generation units can also operations. ured as cache. The remaining two banks perform some addition, subtraction, and contain instruction ROM and instruction shifting operations on the address regis- SRAM/cache. ters. Peripherals In addition to level-one memory, the ADSP-BF5xx family members offer ADSP-BF535 includes an on-chip level- a variety of peripherals, including DMA two (L2) memory system. The L2 mem- Pipeline controllers, general-purpose I/O pins, ory of the ADSP-BF535 consists of 256 The first-generation ADSP-BF535 timers with pulse width modulation Kbytes of unified program and data pipeline has eight stages, while the sec- (PWM) and pulse measurement capabil- RAM. The dual-core ADSP-BF561 pro- ond-generation ADSP-BF5xx pipeline ity, real-time clocks, watchdog timers, vides four banks of private L1 memory has ten stages. Both generations feature serial ports, UART ports, and Serial for each core as well as 128 Kbytes of fully interlocked pipelines, so that data Peripheral Interface (SPI) ports. The shared L2 memory. hazards do not cause unexpected results. ADSP-BF531, ADSP-BF532, ADSP- The ADSP-BF5xx core can perform However, some data hazards are BF533, and ADSP-BF561 each have an one instruction read and two data trans- resolved by stalling the processor. Data internal voltage regulator and one or fers in each cycle. Each data transfer can forwarding has been improved in the more parallel ports that support ITU-R be 8, 16, or 32 bits wide. Both data trans- second-generation microarchitecture; 656 video modes. The ADSP-BF535 has fers can access the same data bank if they some stalls that result from data hazards PCI and USB interfaces. use different sub-banks, but only one of on the ADSP-BF535 have been removed the transfers can be a store. If data is by the improved forwarding mecha- arranged as 16-bit pairs in memory, the nisms.
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