9/23/14
CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
Instruc on, number, string, address? Assembling MIPS instruc ons
The binary encoding of an instruc on set is called machine code. 1 instruc on = 1 word add !$t0, $s1, $s2! 1 integer = 1 word 1 address = 1 word 1 character = 1 byte 000000 !10001 !10010 !01000 !00000 !100000! ... ! 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
00000010001100100100000000100000! 32 bits or one word
7-1 Machine code Machine code 7-2
CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
MIPS instruc on format (R-type) add $t0, $s1, $s2
instruc on opera on or instruc on opera on or opcode opcode shi amount shi amount
op ! rs ! rt ! rd !shamt !funct 000000 !10001 !10010 !01000 !00000 !100000! ! 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
func on code func on code first register second register register des na on first register second register register des na on source operand source operand operand source operand source operand operand
R = register Remember those useless numbers we gave each register?
Machine code 2-3 Machine code 7-4
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CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
MIPS Register Conventions addi $t0, $s1, 1024
Name Register Usage Preserve on Number call? instruc on opera on or opcode $zero 0 constant 0 (hardware) n.a. shi amount
$at 1 reserved for assembler n.a. $v0 - $v1 2-3 returned values no 001000 !10001 ! !01000 !00000 !! $a0 - $a3 4-7 arguments yes ! $t0 - $t7 8-15 temporaries no 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits $s0 - $s7 16-23 saved values yes func on code $t8 - $t9 24-25 temporaries no first register second register register des na on $gp 28 global pointer yes source operand source operand operand $sp 29 stack pointer yes $fp 30 frame pointer yes $ra 31 return addr (hardware) yes
Procedures 6-5 Machine code 7-6
CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
Design Principle 4. register 8 register 17 Good design demands good compromises addi $t0, $s1, 1024
immediate value op ! rs ! rt !constant or address! op ! rs ! rt !constant or address! ! ! 6 bits 5 bits 5 bits 16 bits 6 bits 5 bits 5 bits 16 bits
instruc on opera on or s ll 32 bits opcode
001000 !10001 !01000 !0000 0100 0000 0000! I-type instruc on format ! 6 bits 5 bits 5 bits 16 bits
register des na on I = immediate largest immediate value? first source register immediate amount operand operand
Machine code 7-8 Machine code 7-7
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CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
Compile all the way to bits. addi $t0, $s1, 16711685
op ! rs ! rt !constant or address! op ! rs ! rt !constant or address! ! ! 6 bits 5 bits 5 bits 16 bits 6 bits 5 bits 5 bits 16 bits
s ll 32 bits
s ll 32 bits Exercise. First compile and then assemble a[200] = h + a[300],
assuming $t1 already holds the base address of a and $s2 holds h.
*Here’s where that green card in the front of your text comes in handy.
Machine code 7-9 Machine code 6-10
CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
Dealing with larger constants OR immediate to the rescue
lui $t0, 255 # $t0 is register 8 lui $t0, 255 # $t0 is register 8
001111 00000 !01000 ! 0000 0000 1111 1111 001111 00000 !01000 ! 0000 0000 1111 1111
transfers 16-bit transfers 16-bit immediate constant immediate constant register 8 register 8
0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000
OR of these two values goes into lower 16-bits of $t0 ori $t0, $t0, 5 fills lower 16 bits with zeros 001101 01000 !01000 ! 0000 0000 0000 0101
*But what about the lower 16-bits?
Machine code 7-11 Machine code 7-12
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CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
addi $t0, $s1, 16711685 J-type instruc on format J = jump
Finally, the newly constructed binary value of 16711685 is added to the j 1025 # goto address 5000 contents of $s1 and stored in $t0. 000010 00 0000 0000 0000 0010 0000 0001 lui !$t0, 255 !# $t0 is register 8! ori !$t0, $t0, 5 !# or lower half with upper! add !$t0, $t0, $s1 !# $t0 <- $s1 + 16711785! 6 bits 26 bits The original pseudoinstruc on is translated into three actually assembly language instruc ons at assemble me. op jump address Memory What if low order 16 bits part doesn't fit in ori? : jump destination instruction
Program Counter (PC) Assembler does this for us, uses reserved register $at if needed. 26-bit destination is concatenated with upper 4 bits of PC plus 2 zeros below. Machine code 7-13 Machine code 7-14
CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
Condi onal branches are more limited PC-rela ve addressing
bne $s0, $s1, address bne $t0, $s5, Exit op rs rt offset (16 bits) Memory 000101 !10000 !10001 ! address! ! + branch des na on instruc on 6 bits 5 bits 5 bits 16 bits Program Counter
s ll 32 bits
But they only branch within a single procedure...
How big of a loop does this allow? (Trick ques on.) Machine code 7-15 Machine code 7-16
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CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
Compare with base addressing Branching offsets in machine language
bne $t0, $s5,Exit while (save[i] == k)! !i += 1;! op rs rt offset Memory address op rs rt rd shamt funct! branch destination instruction Loop: sll $t1, $s3, 2 !80000 !0 0 19 9 2 0 ! add $t1, $t1, $s6 !80004 !0 9 22 9 0 32! Program Counter lw $t0, 0($t1) !80008 !35 9 8 0! bne $t0, $s5, Exit !80012 !5 8 21 2! addi $s3, $s3, 1 !80016 !8 19 ! 19 ! 1! lw $t0, 12($t1) j Loop ! !80020 !2 20000! op rs rt offset Memory Exit: ! !!!!! address or offset
word or byte operand
base register
Machine code 7-17 Machine code 7-18
CS 240, Fall 2014! WELLESLEY CS! CS 240, Fall 2014! WELLESLEY CS!
1. Immediate addressing op rs rt Immediate 5 addressing modes Disassembly!
2. Register addressing op rs rt rd . . . funct Registers Register
3. Base addressing op rs rt Address Memory
Register + Byte Halfword Word 0x00af8020!
4. PC-relative addressing op rs rt Address Memory
PC + Word
5. Pseudodirect addressing op Address Memory
PC Word
Machine code 7-20 Machine code 7-21
5