Microprocessors and Interfacing 8086, 8051, 8096, and advanced processors
N. Senthil Kumar Professor Department of Electrical and Electronics Engineering Mepco Schlenk Engineering College Sivakasi, Tamil Nadu Press M. Saravanan Professor Department of Electrical and Electronics Engineering Thiagarajar College of Engineering Madurai, Tamil Nadu
S. Jeevananthan UniversityProfessor Department of Electrical and Electronics Engineering Pondicherry Engineering College Puducherry
S.K. Shah OxfordProfessor and Head Department of Electrical Engineering MS University of Baroda Vadodara, Gujarat
© Oxford University Press. All rights reserved. 3
Oxford University Press is a department of the University of Oxford. It furthers the University’s objective of excellence in research, scholarship, and education by publishing worldwide. Oxford is a registered trade mark of Oxford University Press in the UK and in certain other countries.
Published in India by Oxford University Press YMCA Library Building, 1 Jai Singh Road, New Delhi 110001, India
© Oxford University Press 2012
The moral rights of the author/s have been asserted.
First published in 2012
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, without the prior permission in writing of Oxford University Press, or as expressly permitted by law, by licence, or under terms agreed with the appropriate reprographics rights organization. Enquiries concerning reproduction outside the scope of the above should be sent to the Rights Department, Oxford University Press, at the address above. Press You must not circulate this work in any other form and you must impose this same condition on any acquirer.
ISBN-13: 978-0-19-807906-4 ISBN-10: 0-19-807906-0
Typeset in Times New Roman by Trinity Designers & Typesetters, Chennai Printed in India byUniversity Tara Art Printers (P) Ltd, Noida
Oxford
© Oxford University Press. All rights reserved. Brief Contents xi Brief Contents
Features of the Book iv Preface vii 1. Microprocessors—Evolution and Introduction to 8085 1 2. Methods of Data Transfer and Serial Transfer Protocols 47
PART I: INTEL 8086—16-BIT MICROPROCESSORS 3. Intel 8086 Microprocessor Architecture, Features, and Signals 63 4. Addressing Modes, Instruction Set, and Programming of 8086 80 5. 8086 Interrupts 175 6. Memory and I/O Interfacing Press 210 7. Features and Interfacing of Programmable Devices for 8086-based Systems 240 0XOWLSURFHVVRU&RQ¿JXUDWLRQ 9. 8086-based Systems 372
PART II: INTEL 8051—8-BITUniversity MICROCONTROLLERS 10. Introduction to 8051 Microcontrollers 391 11. 8051 Instruction Set and Programming 402 12. Hardware Features of 8051 427 13. 8051 InterfaceOxford Examples 464
PART III: INTEL 8096—16-BIT MICROCONTROLLERS 14. Overview of Intel 8096 Microcontrollers 517 15. 8096 Instruction Set and Programming 530 16. Hardware Features of 8096 549
PART IV: ADVANCED TRENDS 17. Microprocessor System Developments and Recent Trends 591 18. Advanced Microprocessors and Microcontrollers 604 19. Embedded Systems 663 20. Hybrid Programming Techniques Using ASM and C/C++ 736
© Oxford University Press. All rights reserved. xii Brief Contents Appendix A: 8086 Case Studies 752 Appendix B: 8051 Case Studies 758 Appendix C: 8275 CRT Controller Chip 766 Appendix D: Multiple Choice Questions 777 Appendix E: 8086 Instruction Set 797 Appendix F: 8051 Instruction Set 803 Bibliography 811 Index 812
Press
University
Oxford
© Oxford University Press. All rights reserved. Detailed Contents xiii Detailed Contents
Features of the Book iv Preface vii Brief Contents xi 1. Microprocessors—Evolution and Introduction to 8085 1 1.1 Introduction 1 1.2 Explanation of Basic Terms 2 1.3 Microprocessors and Microcontrollers 5 1.4 Microprocessor-based System 6 1.5 Origin of Microprocessors 7 1.5.1 First generation (1971–1973) 8 1.5.2 Second generation (1974–1978) 8 1.5.3 Third generation (1978–1980) 8 1.5.4 Fourth generation (1981–1995) 8 1.5.5 Fifth generation (1995–till date) Press 9 1.5.6 Timeline of microprocessor evolution 9 &ODVVL¿FDWLRQRI0LFURSURFHVVRUV 1.7 Types of Memory 11 1.8 Input and Output Devices 13 1.9 Technology Improvements Adapted to Microprocessors and Computers 14 1.10 Introduction to 8085 ProcessorUniversity 14 1.11 Architecture of 8085 16 1.11.1 Arithmetic and logic unit 16 1.11.2 General-purpose registers 17 1.11.3 Special-purpose registers 17 1.11.4 Instruction register and decoder 19 1.11.5 TimingOxford and control unit 19 1.12 Microprocessor Instructions 23 &ODVVL¿FDWLRQRI,QVWUXFWLRQV 1.13.1 Based on functionality 24 1.13.2 Based on length 26 1.13.3 Addressing modes in instructions 28 1.14 Instruction Set of 8085 30 1.14.1 Format of assembly language instructions and programs 31 1.14.2 Data transfer instructions 31 1.14.3 Arithmetic instructions 34 1.14.4 Logical instructions 36 1.14.5 Branching instructions 38 1.14.6 Machine control instructions 39 1.15 Sample Programs 40 1.16 Instruction Execution 42
© Oxford University Press. All rights reserved. xiv Detailed Contents 2. Methods of Data Transfer and Serial Transfer Protocols 47 2.1 Data Transfer Mechanisms 47 2.2 Memory-mapped and I/O-mapped Data Transfer 47 2.3 Programmed Data Transfer 48 2.4 Direct Memory Access 49 2.5 Parallel Data Transfer 50 2.6 Serial Data Transfer 50 2.6.1 Introduction to RS-232 standard 51 2.6.2 Introduction to RS-485 standard 54 2.6.3 GPIB/IEEE 488 standards 55 2.7 Interrupt Structure of a Microprocessor 57 2.8 Types of Interrupts 57 2.8.1 Vectored and non-vectored interrupts 57 2.8.2 Maskable and non-maskable interrupts 58 2.8.3 Software and hardware interrupts 58 2.9 Interrupt Handling Procedure 58
PART I: INTEL 8086—16-BIT MICROPROCESSORS 3. Intel 8086 Microprocessor Architecture, Features,Press and Signals 63 3.1 Introduction 63 3.2 Architecture of 8086 63 3.2.1 Execution unit 63 3.2.2 Bus interface unit 66 3.2.3 Minimum and maximum mode operations 67 3.3 Accessing Memory Locations 67 3.4 Pin Details of 8086 University 70 3.4.1 Function of pins common to minimum and maximum modes 70 3.4.2 Function of pins used in minimum mode 72 3.4.3 Function of pins used in maximum mode 73 3.5 Differences Between 8086 and 8088 74 4. Addressing Modes,Oxford Instruction Set, and Programming of 8086 80 4.1 Addressing Modes in 8086 80 4.1.1 Register Addressing Mode 80 4.1.2 Immediate Addressing Mode 80 4.1.3 Data Memory Addressing Modes 81 4.1.4 Program Memory Addressing Modes 83 4.1.5 Stack Memory Addressing Mode 85 6HJPHQW2YHUULGH3UH¿[ 4.3 Instruction Format of 8086 87 4.3.1 One-byte instruction 87 4.3.2 Register to register 87 4.3.3 Register to/from memory with no displacement 87 4.3.4 Register to/from memory with displacement 89 4.3.5 Immediate operand to register 89 4.3.6 Immediate operand to memory with 16-bit displacement 89
© Oxford University Press. All rights reserved. Detailed Contents xv 4.4 Instruction Set of 8086 91 4.4.1 Data transfer instructions 91 4.4.2 Arithmetic instructions 94 4.4.3 Logical instructions 102 4.4.4 Flag manipulation instructions 103 4.4.5 Control transfer instructions 103 4.4.6 Shift/rotate instructions 106 4.4.7 String instructions 109 4.4.8 Machine or processor control instructions 110 4.5 8086 Assembly Language Programming 110 4.5.1 Writing programs using line assembler 111 4.5.2 Writing time delay programs 127 4.5.3 8086 Assembler directives 129 4.5.4 Writing assembly language programs using MASM 138 4.6 Program Development Process 162 4.7 Modular Programming 164 4.7.1 CALL instruction 165 4.7.2 RET instruction 166 4.7.3 Macro 167 4.7.4 Illustrative example Press 168 5. 8086 Interrupts 175 5.1 Introduction 175 5.2 Interrupt Types in 8086 175 5.3 Processing of Interrupts by 8086 176 5.4 Dedicated Interrupt Types in 8086 178 5.4.1 Type 00H or divide-by-zero interrupt 178 5.4.2 Type 01H, single step,University or trap interrupt 178 5.4.3 Type 02H or NMI interrupt 178 5.4.4 Type 03H or one-byte INT interrupt 179 5.4.5 T\SH+RURYHUÀRZLQWHUUXSW 5.5 Software Interrupts—Types 00H–FFH 179 5.6 INTR Interrupts—TypesOxford 00H–FFH 180 5.7 Priority Among 8086 Interrupts 182 5.8 Interrupt Service Routines 182 5.9 BIOS Interrupts or Function Calls 189 5.9.1 INT 10H 189 5.9.2 INT 11H 191 5.9.3 INT 12H 192 5.9.4 INT 13H 192 5.9.5 INT 14H 192 5.9.6 INT 15H 192 5.9.7 INT 16H 192 5.9.8 INT 17H 192 5.10 Interrupt Handlers 194 5.11 DOS Services: INT 21H 195 5.12 System Calls—BIOS Services 198 5.12.1 Print screen service: INT 05H 199
© Oxford University Press. All rights reserved. xvi Detailed Contents 5.12.2 Video services: INT 10H 200 5.12.3 Keyboard services: INT 16H 202 5.12.4 Printer services: INT 17H 204 6. Memory and I/O Interfacing 210 6.1 Physical Memory Organization in 8086 210 6.2 Formation of System Bus 211 6.3 Interfacing RAM and EPROM Chips using Only Logic Gates 213 6.4 Interfacing RAM/EPROM Chips using Decoder IC and Logic Gates 217 6.5 I/O Interfacing 220 6.5.1 I/O instructions in 8086 220 6.5.2 I/O-mapped and memory-mapped I/O 220 6.6 Interfacing 8-bit Input Device with 8086 222 6.6.1 Assigning 8-bit address to 8-bit input device using address decoder having only logic gates 222 6.6.2 Assigning 8-bit address to 8-bit input device using address decoder IC 74LS138 222 6.6.3 Assigning 16-bit address to 8-bit DIP switch using address decoder having only logic gates Press 224 6.7 Interfacing 8-bit Output Device with 8086 224 6.8 Interfacing Printer with 8086 225 6.9 Interfacing 8-bit and 16-bit I/O Devices or Ports with 8086 229 6.10 Interfacing CRT Terminal with 8086 233 7. Features and Interfacing of Programmable Devices for 8086-based Systems 240 7.1 Intel 8255 ProgrammableUniversity Peripheral Interface 240 7.1.1 Features of 8255 241 7.1.2 Block diagram of Intel 8255 241 7.1.3 Operating modes and control words of 8255 242 7.1.4 Programming examples 248 7.2 Interfacing Switches and LEDS 249 7.2.1 DebouncingOxford of keys 253 7.3 Interfacing Seven-segment Displays 254 7UDI¿F/LJKW&RQWURO 7.5 Interfacing Analog-to-digital Converters 259 7.5.1 ADC chips and interfacing to microprocessor 260 7.6 Interfacing Digital-to-analog Converters 263 7.6.1 Square wave generation 264 7.6.2 Staircase waveform generation 265 7.6.3 Ramp waveform generation 266 7.6.4 Waveform generation using stored data 267 7.7 Interfacing Stepper Motors 268 7.8 Interfacing Intelligent LCDs 273 7.9 Keyboard and Display Interface IC 8279 278 7.9.1 Matrix keyboard 278 7.9.2 Multiplexed display 283 7.9.3 Features, block diagram, and pin details of 8279 285
© Oxford University Press. All rights reserved. Detailed Contents xvii 7.9.4 Programming of 8279 287 7.9.5 Display interface using 8279 292 7.9.6 Keyboard interface using 8279 293 7.10 Intel Timer IC 8253 295 7.10.1 Features of IC 8253 295 7.10.2 Block diagram of IC 8253 and pin details 295 7.10.3 Operating modes and control word of IC 8253 297 7.10.4 Interfacing of IC 8253 with 8086 302 7.10.5 Application examples 302 7.11 Introduction to Serial Communication 307 7.11.1 Features and details of 8251 USART 309 7.11.2 Control words 312 7.11.3 Interfacing 8251 with 8086 314 7.12 8259 Programmable Interrupt Controller 317 7.12.1 Features and architecture of 8259 318 7.12.2 Pin diagram and details of 8259 320 7.12.3 Initialization of 8259 320 7.12.4 Operation of 8259 324 7.12.5 Interfacing of 8259 to 8086 325 7.13 8237 DMA Controller Press 326 7.13.1 Features, pin details, and architecture of 8237 327 7.13.2 DMA initialization and operation 333 7.13.3 Operation of 8237 with 8086 335 8. Multiprocessor ConÀguration 343 8.1 Introduction 343 8.2 Multiprocessor System—Need and Advantages 344 'LIIHUHQW&RQ¿JXUDWLRQVRI0XOWLSURFHVVRU6\VWHPUniversity &RSURFHVVRUDQGFORVHO\FRXSOHGFRQ¿JXUDWLRQV /RRVHO\FRXSOHGFRQ¿JXUDWLRQ 8.4 Bus Arbitration in Loosely-coupled Multiprocessor System 346 8.4.1 Daisy chaining 347 8.4.2 PollingOxford 347 8.4.3 Independent requesting 348 8.5 Interconnection Topologies in a Multiprocessor System 349 8.5.1 Shared bus architecture 349 8.5.2 Multi-port memory 349 8.5.3 Linked input/output 350 8.5.4 Crossbar switching 350 8.6 Physical Interconnections Between Processors in a Multiprocessor System 351 6WDUFRQ¿JXUDWLRQ 5LQJRUORRSFRQ¿JXUDWLRQ &RPSOHWHO\FRQQHFWHGFRQ¿JXUDWLRQ 8.6.4 Regular topology 352 8.6.5 Irregular topology 352 8.7 Operating System used in a Multiprocessor System 353 8.8 Typical Multiprocessor System having 8086 and 8087 353 8.8.1 Architecture of 8087 354
© Oxford University Press. All rights reserved. xviii Detailed Contents 8.8.2 Pin details of 8087 354 8.8.3 Interconnection of 8087 with 8086 356 8.8.4 Data types of 8087 358 8.9 Typical Multiprocessor System having 8086 and 8089 359 8.9.1 Pin details of 8089 360 8.9.2 Local and remote operation of 8089 362 8.9.3 8089 architecture 364 8.9.4 Communication between CPU (8086) and IOP (8089) 367 9. 8086-based Systems 372 9.1 Introduction 372 LQ0LQLPXP0RGH&RQ¿JXUDWLRQ 9.2.1 Formation of separate address bus and data bus in 8086 372 9.2.2 Formation of buffered address bus and data bus in 8086 374 9.2.3 Connection of 8284A with 8086 375 LQ0D[LPXP0RGH&RQ¿JXUDWLRQ 9.4 8086 System Bus Timings 378 9.4.1 Timing diagrams for general bus operation in minimum mode 378 9.4.2 Timing diagrams for general bus operation in maximum mode 382 9.4.3 Interrupt acknowledgement (INTA) timing Press 383 9.4.4 Bus request and bus grant timing 384 9.5 Design of Minimum Mode 8086-based System 385
PART II: INTEL 8051—8-BIT MICROCONTROLLERS 10. Introduction to 8051 Microcontrollers 391 10.1 Introduction 391 10.2 Intel’s MCS-51 Series MicrocontrollersUniversity 392 10.3 Intel 8051 Architecture 392 10.4 Memory Organization 394 10.5 Internal RAM Structure 395 10.5.1 Special function registers 397 10.5.2 ProcessorOxford status word 397 10.6 Power Control in 8051 399 10.6.1 Idle mode 399 10.6.2 Power down mode 400 10.7 Stack Operation 400 11. 8051 Instruction Set and Programming 402 11.1 Introduction 402 11.2 Addressing Modes of 8051 402 11.2.1 Immediate addressing 402 11.2.2 Register direct addressing 402 11.2.3 Memory direct addressing 403 11.2.4 Memory indirect addressing 403 11.2.5 Indexed addressing 403 11.3 Instruction Set of 8051 404 11.3.1 Data transfer instructions 404 11.3.2 Arithmetic instructions 405
© Oxford University Press. All rights reserved. Detailed Contents xix 11.3.3 Logical instructions 406 11.3.4 Branching instructions 407 11.3.5 Bit manipulation instructions 408 11.4 Some Assembler Directives 410 11.5 Programming Examples using 8051 Instruction Set 410 12. Hardware Features of 8051 427 12.1 Introduction 427 12.2 Parallel Ports in 8051 427 12.2.1 Structure of port 1 428 12.2.2 Structure of ports 0 and 2 429 12.2.3 Structure of port 3 430 12.3 External Memory Interfacing in 8051 432 12.3.1 Program memory interfacing 432 12.3.2 Data memory interfacing 434 12.3.3 Timing diagram for external program and data memory access 435 12.4 8051 Timers 437 12.4.1 Timer SFRs 437 12.4.2 Timer operating modes 439 12.4.3 Timer control and operation Press 442 12.4.4 Using timers as counters 443 12.4.5 Programming examples 443 12.5 8051 Interrupts 445 12.5.1 Interrupt sources and interrupt vector addresses 445 12.5.2 Enabling and disabling of interrupts 446 12.5.3 Interrupt priorities and polling sequence 447 12.5.4 Timing of interrupts 448 12.5.5 Programming examplesUniversity 450 12.6 8051 Serial Ports 453 12.6.1 Serial port control SFRs 453 12.6.2 Operating modes 455 12.6.3 Programming the serial port 457 13. 8051 InterfaceOxford Examples 464 13.1 Interfacing 8255 with 8051 464 13.2 Interfacing of Push Button Switches and LEDs 465 13.3 Interfacing of Seven-segment Displays 467 13.4 Interfacing ADC chip 469 13.5 Interfacing DAC chip 471 13.5.1 Square wave generation 472 13.5.2 Staircase wave generation 472 13.5.3 Ramp wave generation 473 13.5.4 Sine wave generation 474 13.6 Interfacing Matrix Keypad 475 13.7 Interfacing Stepper Motor with 8051 478 13.8 Interfacing LCD with 8051 482 13.9 Interfacing DC Motors/Servomotors 487 13.9.1 Bidirectional DC motor control 488 13.10 Microcontroller Application Example—Stopwatch 489
© Oxford University Press. All rights reserved. xx Detailed Contents 0LFURFRQWUROOHU$SSOLFDWLRQ([DPSOH²7UDI¿F/LJKW&RQWURO 13.12 Microcontroller Application Example—Thermometer 495 13.13 RTC Interfacing using I2C Standard 498 13.13.1 Details of I2C bus 499 13.13.2 8051 Subroutines used to implement I2C bus 503 13.13.3 DS1307—Serial I2C real-time clock IC 505
PART III: INTEL 8096—16-BIT MICROCONTROLLERS
14. Overview of Intel 8096 Microcontrollers 517 14.1 Introduction 517 14.2 Features of Intel 8096 Microcontroller 519 14.3 Functional Block Diagram 519 14.3.1 CPU section 519 14.3.2 8096 CPU buses 521 14.3.3 Register arithmetic and logical unit 521 14.3.4 Temporary register 521 5HJLVWHU¿OH 14.3.6 Program status word 523 14.3.7 Memory controller Press 523 14.3.8 Internal timing 523 14.3.9 I/O section 524 14.4 Memory Structure 525 14.5 Power Down Mode of CPU 528 15. 8096 Instruction Set and Programming 530 15.1 8096 Operand Types 530 15.2 Addressing Modes University 531 15.2.1 Register direct addressing 531 15.2.2 Indirect addressing 531 15.2.3 Indirect addressing with auto increment 532 15.2.4 Immediate addressing 532 15.2.5 Short-indexedOxford addressing 532 15.2.6 Long-indexed addressing 532 15.2.7 Zero register addressing 532 15.2.8 Stack pointer register addressing 533 &ODVVL¿FDWLRQRI,QVWUXFWLRQV 15.3.1 Data transfer instructions 533 15.3.2 Arithmetic and logical instructions 533 15.3.3 Shift/rotate instructions 534 15.3.4 Branching instructions 535 15.4 Complete 8096 Instruction Set 536 15.5 Programming Examples using 8096 Instruction Set 540 16. Hardware Features of 8096 549 16.1 Parallel Ports in 8096 and Their Structure 549 16.1.1 Port 0 549 16.1.2 Port 1 550 16.1.3 Port 2 550
© Oxford University Press. All rights reserved. Detailed Contents xxi 16.1.4 Ports 3 and 4 551 16.2 Control and Status Registers 551 16.2.1 Input/output control register 0 551 16.2.2 Input/output control register 1 552 16.2.3 Input/output status register 0 552 16.2.4 Input/output status register 1 553 16.3 Timers 553 16.3.1 Timer 1 553 16.3.2 Timer 2 554 16.4 Interrupts 556 16.4.1 Interrupt sources 556 16.4.2 Polling routine 557 16.4.3 Vectored interrupt 557 16.4.4 Interrupt control 559 16.4.5 Interrupt pending register 560 16.4.6 Interrupt mask register 561 16.4.7 Global disable 561 16.4.8 Program status word 561 16.5 Serial Ports 562 16.5.1 Operating modes of serial port Press 563 16.5.2 Serial port control/status registers 564 16.5.3 Determining baud rate 564 16.5.4 Program for serial port data reception 565 16.6 Analog-to-digital Converter 566 16.7 Digital-to-analog Converter 569 16.8 High Speed Input Unit 570 16.8.1 HSI interrupts University 573 16.8.2 Programming HSI 573 16.9 High Speed Output Unit 575 16.9.1 HSO status 578 16.10 Memory Expansion 578 16.10.1 Single-chip mode 579 16.10.2 ExpandedOxford mode 579 16.10.3 Choice of bus width 580 16.10.4 Bus control 581 16.10.5 ROM/EPROM lock 583
PART IV: ADVANCED TRENDS 17. Microprocessor System Developments and Recent Trends 591 17.1 Introduction 591 17.2 Microcontroller Features and Developments 591 17.3 Microprocessor Development Systems 593 17.3.1 In-system programming 594 17.3.2 Debugger 594 17.3.3 Emulator 594 17.4 Cross Compiler for 8051 595 17.5 Programming 8051 in C Language 596
© Oxford University Press. All rights reserved. xxii Detailed Contents 18. Advanced Microprocessors and Microcontrollers 604 18.1 Introduction 604 18.2 80186 Microprocessor 605 18.2.1 Architecture 605 18.2.2 Instruction set of 80186 606 18.3 80286 Microprocessor 607 18.3.1 Architecture 607 18.3.2 Register organization and real or protected addressing in 80286 608 18.3.3 Privilege levels in protected mode of operation 611 18.3.4 Descriptor cache or program-invisible registers 613 18.3.5 Accessing memory using GDT and LDT 613 18.3.6 Multitasking in 80286 615 18.3.7 Addressing modes and new instructions in 80286 616 18.3.8 Flag register 617 18.4 80386 Microprocessor 618 18.4.1 Architecture of 80386 618 18.4.2 Register organization in 80386 620 18.4.3 Instruction set of 80386 623 18.4.4 Addressing memory in protected mode Press 624 18.4.5 Physical memory organization in 80386 625 18.4.6 Paging mechanism in 80386 626 18.5 80486 Microprocessor 629 18.6 Pentium Microprocessor 632 18.6.1 Architecture of Pentium 632 18.6.2 Protected mode operation of Pentium 637 18.6.3 Addressing modes inUniversity Pentium 637 18.6.4 Paging mechanism in Pentium 637 18.7 Other Versions of Pentium 637 18.7.1 Pentium Pro processor 637 18.7.2 Pentium II processor 638 18.7.3 Pentium III processor 638 18.7.4 PentiumOxford 4 processor 638 18.8 Operating Modes of Advanced Processors 638 18.9 Mode Transition 639 18.10 Memory Management in Protected Mode 640 18.11 Segment Descriptor 640 18.12 Protection: Purpose 643 18.12.1 Type checking 644 18.12.2 Limit checking/restriction of addressable domain 644 18.12.3 Privilege levels 645 18.13 Protected Mode Instructions 647 18.14 Multitasking 649 19. Embedded Systems 663 19.1 Introduction 663 19.1.1 Characteristics of embedded systems 663 19.1.2 Design metric 665 19.1.3 Evolution of embedded systems 667
© Oxford University Press. All rights reserved. Detailed Contents xxiii 19.1.4 Design technology 667 &ODVVL¿FDWLRQRI(PEHGGHG6\VWHPV 19.3 Embedded Processor Architecture 669 19.3.1 RISC and CISC architectures 671 19.3.2 SISD/SIMD 673 19.3.3 The e200z6 core 673 19.3.4 Cell microprocessor 675 19.3.5 PowerPC architecture 675 19.3.6 PIC16F877 microcontroller 679 19.3.7 ARM processors 695 19.4 SUN SPARC Microprocessor 707 19.4.1 SPARC architecture 707 5HJLVWHU¿OH 19.4.3 Data types in SPARC architecture 712 19.4.4 SPARC instruction format 713 19.4.5 Adressing modes in SPARC microprocessor 714 19.4.6 Instruction set in SPARC microprocessor 714 19.4.7 Load and store instructions 715 19.4.8 Arithmetic and logical instructions 716 19.4.9 Branch instructions Press 717 19.4.10 Special instructions 718 19.5 Software Embedded into System 721 19.5.1 Codesign 722 19.6 Bus Architectures 725 19.6.1 Parallel bus protocols 725 19.6.2 Serial bus protocols 726 19.6.3 Serial wireless protocols 727 19.7 Memory University 727 19.7.1 Memory technologies 728 19.7.2 Memory hierarchy 728 19.7.3 Memory interfacing 729 19.8 I/O Interfacing 729 19.9 Smart CardOxford Design 730 19.9.1 Vertical (concurrent) and horizontal (serial) codesign 731 19.9.2 Security extension 732 20. Hybrid Programming Techniques using ASM and C/C++ 736 20.1 Combining Assembly Language with C/C++ 736 20.2 Calling Conventions 737 20.2.1 CDECL calling convention 738 20.2.2 STDCALL calling convention 739 20.2.3 FASTCALL calling convention 740 20.3 Passing Parameter Techniques 740 20.4 Techniques for 16-bit ALP Microsoft C/C++ for DOS 741 20.4.1 Inline assembly 741 20.4.2 Linked assembly 742 20.5 Using ALP with C/C++ for 32-bit Applications 743 20.5.1 Calling ALP procedure from C 744 20.6 32-bit Windows Programming 744
© Oxford University Press. All rights reserved. xxiv Detailed Contents 20.6.1 Console functions 745 20.6.2 Microsoft Win32 application programming interface 747 20.7 Program Development Methods 749 Appendix A: 8086 Case Studies 752 Appendix B: 8051 Case Studies 758 Appendix C: 8275 CRT Controller Chip 766 Appendix D: Multiple Choice Questions 777 Appendix E: 8086 Instruction Set 797 Appendix F: 8051 Instruction Set 803 Bibliography 811 Index 812
Press
University
Oxford
© Oxford University Press. All rights reserved. 1 Microprocessors—Evolution and Introduction to 8085
LEARNING OUTCOMES After studying this chapter, you will be able to understand the following: ,PSRUWDQFHRIPLFURSURFHVVRUV 2ULJLQDQGHYROXWLRQRIPLFURSURFHVVRUV &ODVVLÀFDWLRQRIPLFURSURFHVVRUVDQGPHPRULHV &RPPRQLQSXWDQGRXWSXWGHYLFHVIRUFRPSXWHUV %XVVWUXFWXUHVXVHGLQFRPSXWHUVDQGWHFKQRORJ\LPSURYHPHQWV PLFURSURFHVVRUDUFKLWHFWXUHDQGLQVWUXFWLRQVHW Press
1.1 INTRODUCTION The microprocessor is an electronic chip that functions as the central processing unit (CPU) of a computer. In other words, the microprocessor is the heart of any computer system. Microprocessor-based systems with limited resources are called microcomputers. Today, microprocessors can be found in almost all consumer electronic devices such as computerUniversity printers, washing machines, microwave ovens, mobile phones, fax machines, and photocopiers and in advanced applications such DVUDGDUVVDWHOOLWHVDQGÀLJKWV$Q\PLGGOHFODVVKRXVHKROGZLOOKDYHDERXWD dozen microprocessors in different forms inside various appliances. The recent developments in the electronics industry and the large-scale integration of devices have led to rapid costOxford reduction and increased application of microprocessors and their derivatives. Typically, basic microprocessor chips have arithmetic and logic functional units DORQJZLWKWKHDVVRFLDWHGFRQWUROORJLFWRSURFHVVWKHLQVWUXFWLRQH[HFXWLRQ$OPRVW all microprocessors use the basic concept of stored-program execution. Programs or instructions to be executed by the microprocessor are stored sequentially in memory locations. The microprocessor, or the processor in general, fetches the instructions one after another and executes them in its arithmetic and logic unit. So all microprocessors have a built-in memory access and management part as well as some amount of memory. $PLFURSURFHVVRUFDQEHSURJUDPPHGWRSHUIRUPDQ\WDVNWKDWFDQEHZULWWHQ and programmed by the user. Without a program, the microprocessor unit is a SLHFH RI XVHOHVV HOHFWURQLF FLUFXLW 7KH SURJUDPPHU PXVW WDNH FDUH RI DOO WKH UHVRXUFHVRIWKHPLFURSURFHVVRUDQGXVHWKHPHI¿FLHQWO\IRULPSOHPHQWLQJWKH UHTXLUHGIXQFWLRQDOLW\6RWRZRUNZLWKWKHPLFURSURFHVVRULWLVQHFHVVDU\IRUWKH SURJUDPPHUWRNQRZDERXWLWVLQWHUQDOUHVRXUFHVDQGIHDWXUHV7KHSURJUDPPHU
© Oxford University Press. All rights reserved. 2 Microprocessors and Interfacing must also understand the instructions that a microprocessor can support. Every microprocessor has its own associated set of instructions; this list is given by all microprocessor manufacturers. The instruction set for microprocessors is in two forms—one in mnemonic, which is comparatively easy to understand and the other LQ ELQDU\ PDFKLQH FRGH ZKLFK WKH PLFURSURFHVVRU ZRUNV ZLWK DQG LV GLI¿FXOW for us to understand. Generally, programs are written using mnemonics called assembly-level language and then converted into binary machine-level language. This conversion can be done manually or using an application called assembler. ,QJHQHUDOSURJUDPVDUHZULWWHQE\WKHXVHUIRUWKHPLFURSURFHVVRUWRZRUNZLWK real world data. Data are available in many forms and from many sources. To input these data to the microprocessor, the microprocessor-based systems need some input interfacing circuits and some electronic processing circuits. These circuits LQFOXGHGDWDFRQYHUWHUVDQGSRUWV$IWHUSURFHVVLQJWKHUHDOZRUOGGDWDWKHRXWSXW IURPWKHPLFURSURFHVVRUPXVWEHWDNHQRXWWRJLYHWRWKHRXWSXWGHYLFHVRUFLUFXLWV This again needs interfacing circuits and ports. So a microprocessor-based system will need a set of memory units and interfacing circuits for inputs and outputs. 7KHFLUFXLWVWRJHWKHUZLWKWKHPLFURSURFHVVRUPDNHWKHmicrocomputer system. The physical components of the microcomputer systemPress are called hardware. The SURJUDPWKDWPDNHVWKLVKDUGZDUHXVHIXOLVFDOOHGsoftware. The semiconductor manufacturing technology for chips has developed from transistor–transistor logic (TTL) to complementary metal-oxide-semiconductor (CMOS). Microprocessor manufacturing also has gone through these technological changes. The other semiconductor manufacturing technology available is emitter- coupled logic (ECL). TTL technology is most commonly used for basic digital integrated circuits; CMOS is favoured for portable computers and other battery- powered devices because of its lowUniversity power consumption.
1.2 EXPLANATION OF BASIC TERMS The terms relevant to the use of microprocessors are explained in this section. These explanations will Oxfordgive the reader an understanding of various microprocessor- related terms, technologies, and topics. Chip $FKLSRUDQLQWHJUDWHGFLUFXLWLVDVPDOOWKLQSLHFHRIVLOLFRQZLWKWKH required circuits and transistors etched on it to perform a particular function. Simpler processors may consist of a few thousand transistors etched onto a silicon base just a few millimeters square. Bit $ELWPHDQVDVLQJOHELQDU\GLJLW7KHELWLVDOVRWKHIXQGDPHQWDOVWRUDJH unit of computer memory. In binary form, a bit can have only two values, 0 or 1, whereas a decimal digit can have 10 values, represented by symbols 0 through 9. Bit size The bit size of a microprocessor refers to the number of bits that can be processed simultaneously by the basic arithmetic circuits of the microprocessor. Word $ ZRUG LV D QXPEHU RI ELWV JURXSHG WRJHWKHU IRU SURFHVVLQJ ,Q microprocessors, a word refers to the basic data size or bit size that can be processed
© Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 3 E\WKHDULWKPHWLFDQGORJLFXQLW $/8 RIWKHSURFHVVRU$ELWELQDU\QXPEHULV FDOOHGDZRUGLQDELWSURFHVVRU Memory word The number of bits that can be stored in a register or memory element is called memory word. Mostly, all memory units use eight bits for their memory word. Byte $QELWZRUGLVUHIHUUHGWRDVDE\WH Nibble $ELWZRUGLVUHIHUUHGWRDVDQLEEOH Kilobyte $FROOHFWLRQRIE\WHVLVFDOOHGDNLORE\WH 10 bytes). Megabyte $FROOHFWLRQRI NLORE\WHVLVFDOOHGDPHJDE\WH bytes). RAM or R/W memory Random access memory or read/write memory is a type of semiconductor memory in which a particular memory location can be erased and written with new data at any time. These memory units are volatile, which means that the contents of the memory are erased when the power to the chip is disrupted. The access of the individual memory location can be done randomly. In PLFURSURFHVVRUVWKH5$0LVXVHGWRVWRUHGDWD Press DRAM Dynamic random access memory is a semiconductor memory in which the stored contents need to be refreshed repeatedly at about thousands of times per second. Without refreshing, the stored data will be lost. These memory chips are preferred in a computer system as these are slower but economical. SRAM Static random access memoryFKLSVNHHSWKHGDWDVWRUHGLQLWDVORQJDV SRZHULVDYDLODEOH7KHUHLVQRQHHGIRUUHIUHVKLQJ,QWHUPVRIVSHHG65$0LV faster. University ROM Read only memory devices are memory devices whose contents are retained even after removing the power supply. Arithmetic and logic unit $/8LVDGLJLWDOFLUFXLWSUHVHQWLQWKHPLFURSURFHVVRU to perform arithmeticOxford and logic operations on digital data. The typical operations SHUIRUPHGE\WKH$/8DUHDGGLWLRQVXEWUDFWLRQORJLFDO$1'ORJLFDO25DQG FRPSDULVRQRIELQDU\GDWD*HQHUDOO\WKHIXQFWLRQVRIWKH$/8RIDPLFURSURFHVVRU will decide the processor’s functionality. Microcontroller $ PLFURFRQWUROOHU LV D FKLS WKDW LQFOXGHV PLFURSURFHVVRU memory, and input/output signal ports. Microcontrollers can be called single-chip microcomputers. Microcomputer The system formed by interfacing the microprocessor with the memory and I/O devices to execute the required programs is called microcomputer. Bus $EXVLV a group of wires/lines that carry similar information. System bus The system bus is a group of wires/lines used for communication between the microprocessor and peripherals.
© Oxford University Press. All rights reserved. 4 Microprocessors and Interfacing Firmware Software written for a microprocessor application without provision IRUFKDQJHVLVFDOOHG¿UPZDUH7KHVHDUHVWRUHGLQWKHSHUPDQHQWVWRUDJHRU520 of the computer system. Input device The devices that are used for providing data and instructions to the microprocessor or microcomputer system are called input devices. Keyboard and mouse are the common input devices. Output device The devices that are used for transferring data out of the microprocessor or microcomputer system are called output devices. Display screen, printer, and other forms of display are the common output devices. Floppy disk $ UHPRYDEOHW\SH PDJQHWLF GLVN XVHG IRU VWRULQJ SURJUDPV DQG GDWDIRUWUDQVIHUULQJIURPDQGWRWKHFRPSXWHULVFDOOHGÀRSS\GLVN Disk drive The hardware component that is used to read or write data to devices VXFKDVÀRSS\GLVNVLVFDOOHGGLVNGULYH Computer architecture 7KHGHVLJQLQWHUQDOFRQ¿JXUDWLRQDQGDFFHVVHVLQD digital computer are together called computer architecture. Von–Neumann architecture The architecture in whichPress the same memory is used for storing programs as well as data. Harvard architecture The architecture in which programs and data are stored in two separate memory units. CISC processor Complex instruction set computer is a processor architecture that supports many machine language instructions. RISC processor Reduced instructionUniversity set computer is a processor architecture that supports limited machine language instructions. RISC processors are expected to execute the programs faster than CISC processors. High-level language $ FRPSXWHU SURJUDPPLQJ ODQJXDJH LQ ZKLFK SURJUDPV DUH ZULWWHQ ZLWKRXW WKH NQRZOHGJH RI WKH SURFHVVRU LQ ZKLFK WKH SURJUDP ZLOO EH H[HFXWHG %$6,&Oxford )RUWUDQ & 3DVFDO DQG -DYD DUH H[DPSOHV RI KLJKOHYHO languages. Assembly language $ SURJUDPPLQJ ODQJXDJH ZULWWHQ XVLQJ WKH PQHPRQLFV or the instruction set of a particular microprocessor is called assembly language. $VVHPEO\ODQJXDJHSURJUDPPLQJLVPLFURSURFHVVRUVSHFL¿F,WLVQRWDVHDVLO\ understood as a high-level language program, but is easier than a machine language program. Machine language Machine language refers to binary code programs that are VSHFL¿FWRWKHSURFHVVRUDQGFDQEHGLUHFWO\H[HFXWHGE\WKHSURFHVVRU0DFKLQH language is the lowest level language and cannot be easily understood. Assembler $FRPSXWHUDSSOLFDWLRQSURJUDPWKDWFRQYHUWVWKHDVVHPEO\ODQJXDJH program into machine-level language program. Compiler $FRPSXWHUSURJUDPWKDWFRQYHUWVWKHKLJKOHYHOODQJXDJHSURJUDP into machine-level language program.
© Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 5 Interpreter $ FRPSXWHU SURJUDP WKDW UHDGV WKH KLJKOHYHO RU DVVHPEO\OHYHO program one line at a time and converts it into machine-level program. Compiler DQGDVVHPEOHUFDQIXQFWLRQRQO\RQWKHHQWLUHSURJUDPLQD¿OH Algorithm $VHTXHQFHRIRSHUDWLRQVRULQVWUXFWLRQVWKDWGH¿QHVKRZWRVROYHD SUREOHPXVLQJDFRPSXWHURUPLFURFRPSXWHU$QDOJRULWKPPXVWEHGH¿QLWHPXVW IROORZDFOHDULQVWUXFWLRQÀRZZLWKRXWDPELJXLW\DQGPXVWKDYHGH¿QLWHVWDUWDQG end points. BIOS Basic input/output system is a set of programs that handles the input and RXWSXWIXQFWLRQVDQGLQWHUDFWVZLWKWKHKDUGZDUHGLUHFWO\$QHZKDUGZDUHLQVWDOOHG must be provided with the corresponding BIOS routines. Clock The circuit in the computer that generates the sequence of evenly spaced pulses to synchronize the activities of the processor and its peripherals is called FORFN7KHFORFNVSHHGGHWHUPLQHVWKHVSHHGRIWKHRSHUDWLRQRIWKHFRPSXWHU7KH FRPSXWHUZLWKDKLJKIUHTXHQF\FORFNZRUNVIDVWHU1RUPDOO\WKHFORFNIUHTXHQF\ is in the range of megahertz (MHz) or gigahertz (GHz). MIPS Million instructions per second is a measure of the speed at which the instructions are executed in a processor. Press Tri-state logic It is the logic used by digital circuits. The three logic levels used are high (1), low (0), and high impedance state (Z). The logic high state of a digital FLUFXLWFDQVRXUFHFXUUHQWDQGWKHORJLFORZFDQVLQNFXUUHQWLQDFRPSXWHUV\VWHP EXWWKHKLJKLPSHGDQFHVWDWHQHLWKHUVRXUFHVQRUVLQNVFXUUHQWDQGVRWKHRWKHU devices connected to it are not affected. Operating system The programUniversity that controls the entire computer and its resources and enables users to access the computer and its resources is called operating system. It is required for any computer system to become operational and user friendly. Under the control of the operating system, the computer recognizes and obeys commands typed by the user. In addition, the operating system provides built-in routines thatOxford allow the user’s program to perform input/output operations ZLWKRXWVSHFLI\LQJWKHH[DFWKDUGZDUHFRQ¿JXUDWLRQRIWKHFRPSXWHU,QORZOHYHO microprocessor-based systems, the program that controls the hardware is called monitor routine or monitor software.
1.3 MICROPROCESSORS AND MICROCONTROLLERS The microprocessor (also called CPU) is the principal element of a computer as it executes lists of instructions. These instruction lists are commonly called programs. This programming language is complex to use since it is machine- or SURFHVVRUVSHFL¿FDQGFRGHGLQWRKH[DGHFLPDODQGELQDU\ Two types of processors are manufactured—the microprocessor and the PLFURFRQWUROOHU$WWKHGDWDSURFHVVLQJOHYHOWKHWZRDUHSUDFWLFDOO\HTXLYDOHQW The distinction comes from the established functionalities. The general-purpose microprocessors give the computers all the necessary computing power. These microprocessors need additional circuitry elements such
© Oxford University Press. All rights reserved. 6 Microprocessors and Interfacing DVPHPRU\GHYLFHVDQG,2SRUWVWRFRQQHFWWKHLQSXWDQGRXWSXWGHYLFHV$OO PLFURSURFHVVRUEDVHG V\VWHPV QHHG WZR W\SHV RI PHPRULHV²5$0 DQG520 5$0 LV XVHG IRU VWRUDJH RI GDWD ZKLOH 520 LV XVHG IRU VWRUDJH RI SURJUDPV especially the start-up program that runs when the microprocessor is powered on. There are numerous microprocessors developed by many companies. The HYROXWLRQRIPLFURSURFHVVRUVIURPELWPLFURSURFHVVRUVWRELWPLFURSURFHVVRUV KDVEHHQGLVFXVVHGODWHULQWKLVFKDSWHU7KLVERRNLVGHYRWHGWRWKHGLVFXVVLRQ RI WZR JURXSV RI PLFURSURFHVVRUV²,QWHO¶V ELW PLFURSURFHVVRU VHULHV LQ EULHIDQGELWVHULHVLQGHWDLO Microcontrollers are microprocessors designed specially for control applications. Microcontrollers contain memory units and I/O ports inside a chip, in addition to the CPU. Microcontrollers are otherwise called embedded controllers; they are generally used to control and operate smart machines. Some of the machines using microcontrollers are microwave ovens, washing machines, sewing machines, automobile ignition systems, computer printers, and fax machines. 1.4 MICROPROCESSOR-BASED SYSTEM $FRPSXWHUV\VWHPGHYHORSHGXVLQJDEDVLFJHQHUDOSXUSRVHPLFURSURFHVVRULV called a microcomputer system. TheUniversity system consists of CPU, memory, and I/O SRUWVDVVKRZQLQ)LJ CPU Memory Input Output Oxford Data bus Control bus $GGUHVVEXV Fig. 1.1 0LFURFRPSXWHUV\VWHP 9RQ²1HXPDQQPRGHO )LJXUHVKRZVDW\SLFDOSHUVRQDOFRPSXWHUV\VWHP7KHLQWHUIDFLQJRIWKH processor with the other parts of the microcomputer system needs a three-bus architecture. The three buses are data bus, address bus, and control bus. (DFKPHPRU\ORFDWLRQRU,2SRUWLVLGHQWL¿HGE\DVSHFL¿FDGGUHVVVLPLODU to a postal address. In microprocessor systems, the addresses are all in binary, and in general, represented in hexadecimal number format. The address is a © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 7 5$0DQG520 unique pattern used to identify a location Output in the memory or an I/O port. The address bus consists of many lines that transport the digital data sent by the SURFHVVRU $Q DGGUHVV EXV RI HLJKW ELWV corresponds to eight lines of addresses Output CPU DQGFDQWKXVDGGUHVVdifferent memory locations. These addresses are written Input in hexadecimal number format as 00H– Input ))+DQGFDQEHXVHGWRIRUGLIIHUHQW Fig. 1.2 3HUVRQDOFRPSXWHU ORFDWLRQV 6LPLODUO\ WKH ELW DGGUHVV EXV FDQ DGGUHVV different addresses. ,WVDGGUHVVUDQJHLV+±))))+7KHJUHDWHUWKHQXPEHURIOLQHVLQWKHDGGUHVV bus, the greater the number of locations the processor is able to manage. 7KHDGGUHVVRQWKHDGGUHVVEXVFDQORFDWHDVSHFL¿FPHPRU\RU,2ORFDWLRQ $IWHUVHOHFWLQJWKHORFDWLRQWKHGDWDWUDQVIHUEHWZHHQWKHPHPRU\DQGSURFHVVRU or between the I/O device and the processor is done through the data bus. The ZLGWKRIWKHGDWDEXVGHWHUPLQHVWKHGDWDVL]HWKDWFDQEHWUDQPressVIHUUHG$QELW SURFHVVRUZLOOJHQHUDOO\KDYHDQELWGDWDEXVDQGDELWSURFHVVRUZLOOKDYH D ELW GDWD EXV 7KH PHPRU\ ORFDWLRQV LQ PLFURSURFHVVRUV DUH DFFHVVHG DV ELWRURQHE\WHXQLWVRQO\6RWKHWUDQVIHURIDELWGDWDIURPPHPRU\QHHGVWZR PHPRU\DGGUHVVHV$.%PHPRU\FKLSZLOOKDYHE\WHVRIPHPRU\ORFDWLRQV $ FRQWURO EXVLV QHHGHG IRU SURSHU GDWD WUDQVIHU EHWZHHQ WKH SURFHVVRU DQG the peripherals. The control bus basically consists of signals for selection of the correct memory or I/O device fromUniversity the address, indication of the direction of data transfer, and synchronization of data transfer between slow devices. Many of the control signals are given by the processor itself because the processor is the master of the computer system. Some control signals such as selection of the correct memory chip can be generated externally by the logic circuits. The timing of the control signal is veryOxford important; the entire timing of the operation is controlled by WKHPLFURSURFHVVRULQV\QFKURQL]DWLRQZLWKWKHFORFNVLJQDOLQSXW 1.5 ORIGIN OF MICROPROCESSORS 7KHPLFURSURFHVVRULVWKHJUHDWHVWLQYHQWLRQRIWKHth century. Its evolution started from the earlier mechanical calculating devices, in the 1930s. These devices used PHFKDQLFDOUHOD\V/DWHULQWKH VWKHVHGHYLFHVZHUHUHSODFHGE\YDFXXP WXEHV7KHYDFXXPWXEHVZHUHTXLFNO\UHSODFHGE\WUDQVLVWRUV7KHEUHDNWKURXJK LQWUDQVLVWRUWHFKQRORJ\OHGWRWKHLQWURGXFWLRQRIPLQLFRPSXWHUVLQWKH VDQG the personal computer revolution in the 1970s. The transistor technology led to the development of complex devices called integrated circuits (ICs). The microprocessor, or microprocessing unit (MPU), later evolved as an IC and was designed to fetch instructions and execute the SUHGH¿QHGDULWKPHWLFDQGORJLFIXQFWLRQV,QWHOZDVWKH¿UVW038SURGXFHUDQG KDVEHHQKROGLQJDODUJHVKDUHRIWKHZRUOGPDUNHWIRUWKLVSURGXFW7KHHYROXWLRQ © Oxford University Press. All rights reserved. 8 Microprocessors and Interfacing RIPLFURSURFHVVRUVLVFDWHJRUL]HGLQWR¿YHJHQHUDWLRQV ¿UVWVHFRQGWKLUGIRXUWK DQG¿IWK 1.5.1 First Generation (1971–1973) The microprocessors that were introduced from 1971 to 1973 were referred to DVWKH¿UVWJHQHUDWLRQV\VWHPV)LUVWJHQHUDWLRQPLFURSURFHVVRUVSURFHVVHGWKHLU instructions serially—they fetched the instruction, decoded it, and then executed LW7KH¿UVWPLFURSURFHVVRUWKHZDVLQWURGXFHGLQ ,WZDVFRGHYHORSHG E\%XVLFRPD-DSDQHVHPDQXIDFWXUHURIFDOFXODWRUVDQG,QWHOD86PDQXIDFWXUHU RIVHPLFRQGXFWRUV7KHELWPLFURSURFHVVRUVUDQDWN+]DQGFRQWDLQHG WUDQVLVWRUV7KH\ZHUHIDEULFDWHGXVLQJSFKDQQHOPHWDOR[LGHVHPLFRQGXFWRU (PMOS) technology, which provided low cost, slow speed, and low output currents. 7KH\ZHUHQRWFRPSDWLEOHZLWK77/,Q ,QWHOPDGHWKHELWDQG microprocessors. 1.5.2 Second Generation (1974–1978) $VWKHWHFKQRORJ\HYROYHGWKHQXPEHURIFLUFXLWVWKDWFRXOGEHIDEULFDWHGRQD chip grew. Very large-scale integration (VLSI) led to chips that had speeds up to KXQGUHGVRIPLOOLRQVRIVZLWFKLQJVSHUVHFRQG7KHVHFRQGJHQHUPressDWLRQPDUNHGWKH EHJLQQLQJRIYHU\HI¿FLHQWELWPLFURSURFHVVRUV6RPHRIWKHSRSXODUSURFHVVRUV ZHUH 0RWRUROD¶V DQG ,QWHO¶V DQG =LORJ¶V = 7KH VHFRQG JHQHUDWLRQGHYLFHVPDUNHGDVKDUSFRQWUDVWZLWKWKHXVHRIQHZHUVHPLFRQGXFWRU technology to fabricate chips. They were manufactured using n-channel metal- R[LGHVHPLFRQGXFWRU 1026 WHFKQRORJ\7KLVWHFKQRORJ\RIIHUHGIDVWHUVSHHG DQGKLJKHUGHQVLW\WKDQ3026,WUHVXOWHGLQD¿YHIROGLQFUHDVHLQLQVWUXFWLRQ execution speed and higher chip densities.University 1.5.3 Third Generation (1978–1980) 7KH WKLUG JHQHUDWLRQ LQWURGXFHG LQ ZDV GRPLQDWHG E\ ,QWHO¶V DQG =LORJ¶V=ZKLFKZHUHELWSURFHVVRUVZLWKPLQLFRPSXWHUOLNHSHUIRUPDQFH 7KHVHSURFHVVRUVKDGWKHWHFKQRORJ\RIELWDULWKPHWLFDQGSLSHOLQHGLQVWUXFWLRQOxford SURFHVVLQJ7KHWKLUGJHQHUDWLRQFDPHZLWK,&WUDQVLVWRUFRXQWVRIDERXW ,Q0RWRUROD¶V0&IRUH[DPSOHDQRQFKLSFDFKHZDVLQFRUSRUDWHGIRUWKH ¿UVWWLPHDQGWKHGHSWKRIWKHSLSHOLQHZDVLQFUHDVHGWR¿YHRUPRUHVWDJHV,W was designed using high density metal-oxide-semiconductor (HMOS) technology. +026SURYLGHVVRPHDGYDQWDJHVRYHU1026 ,WVVSHHG±SRZHUSURGXFWLVIRXU WLPHVEHWWHUWKDQWKDWRI1026 LWFDQDFFRPPRGDWHWZLFHWKHFLUFXLWGHQVLW\RI 1026 1.5.4 Fourth Generation (1981–1995) The microprocessors entered their fourth generation with designs containing more WKDQDPLOOLRQWUDQVLVWRUVLQDVLQJOHSDFNDJH7KLVHUDPDUNHGWKHEHJLQQLQJRI ELWPLFURSURFHVVRUV,QWHOLQWURGXFHGDQG0RWRURODLQWURGXFHG They were fabricated using high density/high speed complementary metal-oxide- semiconductor (HCMOS), a low-power version of the HMOS technology. © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 9 1.5.5 Fifth Generation (1995–till date) 7KH¿IWKJHQHUDWLRQPLFURSURFHVVRUVHPSOR\GHFRXSOHGVXSHUVFDODUSURFHVVLQJ DQGWKHLUGHVLJQFRQWDLQVPRUHWKDQPLOOLRQWUDQVLVWRUV7KLVJHQHUDWLRQPDUNV WKHLQWURGXFWLRQRIGHYLFHVWKDWFDUU\RQFKLSIXQFWLRQDOLWLHV,WKDVDOVRSDYHG WKHZD\IRUKLJKVSHHGPHPRU\,2GHYLFHVDORQJZLWKWKHLQWURGXFWLRQRI ELWPLFURSURFHVVRUV,QWHOOHDGVWKHVKRZKHUHZLWK3HQWLXP&HOHURQDQGYHU\ UHFHQWO\GXDODQGTXDGFRUHSURFHVVRUVZRUNLQJZLWKXSWR*+]VSHHG7KLV JHQHUDWLRQLVFKDUDFWHUL]HGE\DORZPDUJLQVLQJOHPLFURSURFHVVRU3&EXVLQHVV ZKLFKLVFRPSOHPHQWHGE\KLJKYROXPHVDOHV7DEOHJLYHVWKHFRPSDULVRQRI WKHPDMRUSURFHVVRUVEDVHGRQVSHFL¿FSDUDPHWHUVVXFKDVFORFNVSHHGDQGGDWD ZRUGVL]H Table 1.1 Comparison of general-purpose processors General-purpose processors Transistors CPU speed Data length (bits) 0+] 0+] 0+] 0+] Press 0+] 0+] 0+] $WKDORQ;3 *+] &HOHURQ ±*+] 3HQWLXP,, ±0+] 3HQWLXP,,, 0+]±*+] 3HQWLXP,,,;HRQ University 0+]±*+] 3HQWLXP ±*+] ,%03RZHU3&* ±0+] 3RZHU3&* ±0+] 1.5.6 Timeline ofOxford Microprocessor Evolution L ²,QWHOPLFURSURFHVVRUZLWK WUDQVLVWRUVZRUNLQJDWDVSHHG RIN+] LL ²,QWHOWZLFHDVSRZHUIXODVWKHZLWKWUDQVLVWRUVDQG VSHHGRIN+] LLL ²,QWHOSURFHVVRUZLWKWUDQVLVWRUVDQGVSHHGXSWR0+] LY ²,QWHO SURFHVVRU ZLWK DERXW WUDQVLVWRUV DQG VSHHG RI ±0+] FDPH LQWR H[LVWHQFH 7KHUH ZHUH PXOWLSOH YHUVLRQV RI PLFURSURFHVVRUV7KHRULJLQDOYHUVLRQRIWKHPLFURSURFHVVRUZLWKRXW VXI¿[$ZDVPDQXIDFWXUHGE\,QWHO,WZDVTXLFNO\UHSODFHGZLWKWKH$ ZKLFK KDG D EXJ¿[HU$ IHZ \HDUV ODWHU LQ WKH V ,QWHO LQWURGXFHG WKH$+WKH+026YHUVLRQRI$IROORZHGE\WKH&$WKH &026YHUVLRQRIWKH$ © Oxford University Press. All rights reserved. 10 Microprocessors and Interfacing Y ²,QWHO;IDPLOLHVRIPLFURSURFHVVRUV7KH¿UVWJHQHUDWLRQRIWKH ;IDPLOLHVLQFOXGHGWKHDQGWKH,WZDVIROORZHGE\WKH DQG YL ²,QWHO ZKLFK ZDV VLPLODU LQ DUFKLWHFWXUH WR WKH WKH difference was in the available number of data bits of the data bus. 1XPEHU RIWUDQVLVWRUV VSHHG 0+]0+]0+] YLL ²,QWHOWKH¿UVWELWFKLSWKDWFRQWDLQHGWUDQVLVWRUV SURFHVVLQJ ¿YH PLOOLRQ LQVWUXFWLRQV SHU VHFRQG DQG UXQQLQJ DOO SRSXODU operating systems, including Windows. YLLL ²,QWHO ZLWK DQ .% FDFKH PHPRU\ VKDUHG IRU GDWD DQG LQVWUXFWLRQV RSHUDWLQJDWFORFNIUHTXHQFLHVIURPWR0+] L[ ²,QWHO3HQWLXPSURFHVVRUUHWDLQVWKHELWDGGUHVVEXVRIWKH EXWGRXEOHVWKHGDWDEXVWRELWV,WLQFOXGHVWZR.%FDFKHPHPRULHV² one for instructions and the other for data. It was based on dual pipeline PHWKRG NQRZQ DV VXSHUVFDODU DUFKLWHFWXUH DQG FXUUHQWO\ RSHUDWHV ZLWK IUHTXHQFLHV XS WR *+] VWDJH SLSHOLQH DQG WKUHHOHYHO FDFKH memory architectures. Press [ ²,QWHO3HQWLXP,,SURFHVVRUZDVGHVLJQHGVSHFL¿FDOO\WRSURFHVVYLGHR 00;DXGLRDQGJUDSKLFVGDWDHI¿FLHQWO\ZLWKVSHHGVRI0+]0+] 0+]DQG0+] (xi) 1999—Intel Celeron processor and Intel Pentium III processor [LL ²,QWHO3HQWLXPSURFHVVRU 9DULRXV RWKHU FRPSDQLHV VXFKUniversity DV 0RWRUROD 1(& 0LWVXELVKL 6LHPHQV $0'7RVKLEDDQG7H[DV,QVWUXPHQWVDOVRPDQXIDFWXUHSURFHVVRUFKLSV7KHVH companies have their own chips and architectures in addition to the regular Intel- based architectures. 1.6 CLASSIFICATIONOxford OF MICROPROCESSORS 0LFURSURFHVVRUVFDQEHFODVVL¿HGEDVHGRQWKHLUVSHFL¿FDWLRQVDSSOLFDWLRQVDQG architecture. Based on the size of the data that the microprocessors can handle, they are FODVVL¿HGDVELWELWELWELWDQGELWPLFURSURFHVVRUV %DVHGRQWKHDSSOLFDWLRQRIWKHSURFHVVRUVWKH\DUHFODVVL¿HGDVIROORZV (i) General-purpose processors (ii) Microcontrollers (iii) Special-purpose processors General-purpose processors are those that are used in general computer system integration and can be used by the programmer for any application. Common PLFURSURFHVVRUVIURP,QWHOWR,QWHO3HQWLXPDUHH[DPSOHVRIJHQHUDOSXUSRVH processors. Microcontrollers are microprocessor chips with built-in hardware for the memory and ports. These chips can be programmed by the user for any generic control application. Special-purpose processorsDUHGHVLJQHGVSHFL¿FDOO\ © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 11 to handle special functions required for an application. Digital signal processors are examples of special-purpose processors; these have special instructions to KDQGOHVLJQDOSURFHVVLQJ$SSOLFDWLRQVSHFL¿FLQWHJUDWHGFLUFXLW $6,& FKLSVDUH also examples of this category of microprocessors. %DVHGRQWKHDUFKLWHFWXUHDQGKDUGZDUHRIWKHSURFHVVRUVWKH\DUHFODVVL¿HGDV IROORZV (i) RISC processors (ii) CISC processors (iii) VLIW processors (iv) Superscalar processors RISC is a processor architecture that supports limited machine language instructions. RISC processors can execute programs faster than CISC processors. CISC processors have about 70 to a few hundred instructions and are easier to program. However, CISC processors are slower and more expensive than RISC processors. Very long instruction word (VLIW) processors have instructions composed of many machine operations. These instructions can be executed in parallel. This parallel execution is called instruction-level parallelism. VLIW processors also have a large number of registers. SuperscalarPress processors use complex hardware to achieve parallelism. It is possible to have overlapping of instruction execution to increase the speed of execution. 1.7 TYPES OF MEMORY Memory unit is an integral part of any microcomputer system. Its primary purpose is to hold program and data. The main objective of the memory unit design is to enable LWWRRSHUDWHDWDVSHHGFORVHWRWKDWRIWKHSURFHVVRU$OWKRXJKWHFKQRORJ\LVDYDLODEOHUniversity WRGHVLJQVXFKDKLJKVSHHGPHPRU\FRVWLVWKHPDMRUOLPLWLQJIDFWRU7RVWULNHD balance between cost and operating speed, a memory system is usually designed using different materials such as solid state, magnetic, and optical materials. $PLFURFRPSXWHUPHPRU\FDQEHORJLFDOO\GLYLGHGLQWRIRXUJURXSV (i) Processor memory/registerOxford (ii) Cache memory (iii) Primary or main memory (iv) Secondary memory Processor memory refers to a set of CPU registers. Processor registers are the ¿UVWVHWRIVWRUDJHGHYLFHVDYDLODEOHIRUWKHSURJUDPPHUVWRVWRUHDQ\GDWDEXW WKH\DUHJHQHUDOO\IHZLQQXPEHU²XSWRDIHZWHQVRUKXQGUHGV$VWKHVHUHJLVWHUV are available within the processor, they are the fastest memory registers. The main disadvantage is the cost involved, which restricts the number of registers and their bytes. Cache memory is the fastest external memory; it is placed close to the processor. The instructions to be executed are placed in the cache memory for access by WKHSURFHVVRU7KHVHDUHDIHZNLORE\WHVLQVL]H&DFKHPHPRU\FRQWDLQVYRODWLOH VHPLFRQGXFWRU5$0V7KHSURFHVVRUIHWFKHVLQVWUXFWLRQVIURPWKHFDFKHPHPRU\ and if an instruction is not in cache, it refers to the primary memory. © Oxford University Press. All rights reserved. 12 Microprocessors and Interfacing Primary memory is the storage area from which all the programs are executed. $OOWKHSURJUDPVDQGFRUUHVSRQGLQJGDWDIRUH[HFXWLRQPXVWEHZLWKLQWKHSULPDU\ memory. The primary memory is much larger than the processor memory and the cache memory but its operating speed is slower. The primary memory in a system varies from few KB to a few MB. Secondary memoryUHIHUVWRWKHVWRUDJHPHGLXPIRUKXJH¿OHVVXFKDVSURJUDP source codes, compilers, operating systems, etc. These are not accessed directly or very frequently by the microprocessor in a computer system. Secondary memory FRQVLVWVRIVORZGHYLFHVVXFKDVPDJQHWLFWDSHVDQGRSWLFDOGLVNV6RPHWLPHVWKH\ DUHUHIHUUHGWRDVDX[LOLDU\RUEDFNXSVWRUH6WRUHGLQIRUPDWLRQLQDPDJQHWLFWDSH RUPDJQHWLFGLVNLVQRWORVWZKHQSRZHULVWXUQHGRII7KHUHIRUHWKHVHVWRUDJH devices are called non-volatile memories. &ODVVL¿FDWLRQRISULPDU\PHPRU\ Primary memory normally includes ROM DQG5$0ZKLFKDUHIXUWKHUFODVVL¿HGDVVKRZQLQ)LJ0LFURSURFHVVRUEDVHG V\VWHPVKDYHDWOHDVWRQH5$0DQGRQH520FKLS Primary memory Press 6HPLFRQGXFWRU5$0 ROM Static Dynamic University0DVN OTP EPROM EEPROM )ODVK PROM ROM memory Fig. 1.3 &ODVVLÀFDWLRQRISULPDU\PHPRULHV 5$0GHYLFHVDOORZERWKUHDGLQJDQGZULWLQJWRWKHLUPHPRU\FHOOOxford V,QVWDWLF 5$0GHYLFHVELWVDUHVWRUHGDVWKHVWDWXVRIRQRIIVZLWFKHV7KHUHDUHQRFKDUJHV LQYROYHGDQGKHQFHQRFKDUJHVWROHDN+RZHYHUVWDWLF5$0GHYLFHVKDYHFRPSOH[ construction and hence larger size per unit storage. So they are more expensive. 6WDWLF5$0VDUHFRPSDUDWLYHO\IDVWHUDQGDUHXVHGLQFDFKHPHPRULHV ,QG\QDPLF5$0GHYLFHVWKHGDWDELWVDUHVWRUHGDVFKDUJHLQFDSDFLWRUV6LQFH FDSDFLWRUFKDUJHKDVDWHQGHQF\WROHDNWKHVHGHYLFHVQHHGUHIUHVKLQJHYHQZKHQ they are powered. However, they have simpler construction and smaller size per unit storage. These devices are less expensive and comparatively slower. $VWKHQDPHLPSOLHVD520SHUPLWVRQO\UHDGDFFHVV7KHUHDUHPDQ\NLQGV RI520V L 0DVNSURJUDPPDEOH520V 03520V DUHFXVWRPPDGHIRUWKHFXVWRPHU their contents are programmed by the manufacturer. Since they are mass produced, they are inexpensive. The customer cannot erase or program it afterwards. © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 13 LL 3URJUDPPDEOH520V 3520V RURQHWLPHSURJUDPPDEOH 273 520V DUH GHYLFHV WKDW FDQ EH SURJUDPPHG E\ WKH XVHU LQ KLVKHU SODFH XVLQJ VSHFLDOHTXLSPHQWV7KHPDLQGLVDGYDQWDJHRI3520VLVWKDWWKH\FDQQRW EHHUDVHGDQGUHSURJUDPPHG LLL (UDVDEOH DQG SURJUDPPDEOH 520V (3520V DOORZ WKH HUDVXUH DQG UHSURJUDPPLQJRIWKHFRQWHQWE\WKHXVHU,QDQ(3520SURJUDPVDUH HQWHUHGXVLQJHOHFWULFDOLPSXOVHVDQGWKHVWRUHGLQIRUPDWLRQLVHUDVHGXVLQJ XOWUDYLROHWUD\V LY (OHFWULFDOO\HUDVDEOH3520V ((3520V RUHOHFWULFDOO\DOWHUDEOH520V ($520V DOORZWKHXVHUVWRHOHFWULFDOO\HUDVHDQGUHSURJUDPLWVFRQWHQWV ((3520VDUHGLIIHUHQWIURP5$0VLQWKDWHOHFWULFDOVLJQDOVDUHUHTXLUHG WRHUDVHDQGSURJUDPWKHP((3520VUHTXLUHDKLJKHUYROWDJHIRUHUDVLQJ DQGSURJUDPPLQJWKDQWKHQRUPDO9VXSSO\ Y )ODVKPHPRU\GHYLFHVDUHDJURXSRIVLQJOHWUDQVLVWRUFHOO(33520V&HOO VL]HVDUHDERXWKDOIWKHVL]HRIDWZRWUDQVLVWRU((35207KHRSHUDWLRQ UHTXLUHVEXONHUDVXUHRIDODUJHSRUWLRQRIWKHPHPRU\DUUD\ 1.8 INPUT AND OUTPUT DEVICES Press ,QSXWDQGRXWSXW GHYLFHVSHUPLWWKHXVHUWRIHHGGDWDWRWKHFRPSXWHUDQGUHWULHYH WKH FRPSXWHG UHVXOW IURP LW 6RPHWLPHV WKH LQSXW DQG RXWSXW GHYLFHV FDQ FRPPXQLFDWHDPRQJWKHPVHOYHV,QJHQHUDOFRPSXWHUV\VWHPVKDYH,2SRUWV ,2GHYLFHVDUHFRQQHFWHGWRWKHVHSRUWVIRUGDWDWUDQVIHU%DVLFDOO\WKHSRUWVDUH GLJLWDOUHJLVWHUVWKDWDOORZWKHFRPSXWHUWRWUDQVIHUGDWDEHWZHHQWKH,2GHYLFHV XVLQJDGGLWLRQDOFRQWUROVLJQDOV7KHVHFRQWUROVLJQDOVDOORZHUURUIUHHWUDQVIHURI GDWD University 7KH FRPPRQ LQSXW GHYLFH XVHG LQ DOPRVW DOO V\VWHPV LV WKH NH\SDG 0LFURSURFHVVRUEDVHGEDVLFPLFURFRPSXWHUV\VWHPVXVHVLPSOHQXPHULFNH\SDGV +RZHYHUDGYDQFHGFRPSXWHUV\VWHPVXVHNH\ERDUGVZLWKDODUJHQXPEHURINH\V LQYROYLQJ DOSKDEHWV QXPEHUV DQG VSHFLDO FKDUDFWHUV 1RZDGD\V D QXPEHU RI RSWLFDOGHYLFHVDQGVFDQQHUVVXFKDVPRXVHMR\VWLFNDQGEDUFRGHVFDQQHUVDUHOxford DOVREHLQJXVHGDVLQSXWGHYLFHV0LFURFRPSXWHUV\VWHPVDOVRXVHGLIIHUHQWW\SHV RIVHQVRUVIRUGDWDLQSXW7KHVHVHQVRUVQHHGGDWDFRQYHUWHUVVXFKDVDQDORJWR GLJLWDOFRQYHUWHUV$Q\LQWURGXFWRU\FRXUVHRQPLFURSURFHVVRUVVKRXOGFRYHUWKH LQWHUIDFLQJRIGDWDFRQYHUWHUVNH\SDGVDQGVZLWFKHV $QRXWSXWGHYLFHLVDGHYLFHWKURXJKZKLFKWKHXVHUFDQUHFHLYHWKHUHVXOWVIURP WKHFRPSXWHU7KHRXWSXWFDQEHDUDSLGO\FKDQJLQJGLVSOD\RUSULQWHGPDWHULDO 2WKHUIRUPVRIRXWSXWDUHVRXQGVDQGDODUPV7KHVLPSOHVWRXWSXWGHYLFHVXVHGLQ DOPRVWDOOPLFURSURFHVVRUEDVHGV\VWHPVDQGFRPSXWHUV\VWHPVDUH/('VVHYHQ VHJPHQW/('GLVSOD\VDQG/&'GLVSOD\V7KHDGYDQFHGYLGHRGLVSOD\WHUPLQDOV HLWKHUFDWKRGHUD\WXEHVRU/&'V DQGLQNMHWDQGODVHUSULQWHUVDUHWKHFRPPRQ RXWSXWGHYLFHVQRZDGD\V6RPHRXWSXWGHYLFHVFDQEHXVHGWRGLUHFWO\FRQWURO PDFKLQHULHV 6RPH GHYLFHV VXFK DV GLVSOD\ WHUPLQDOV ZLWK WRXFK VFUHHQ PD\ SURYLGHERWKLQSXWDQGRXWSXW0RGHPVDQGRWKHUQHWZRUNLQWHUIDFHFDUGVFDQ DOVREHFDOOHGRXWSXWGHYLFHVDVWKH\HQDEOHWKHWUDQVPLVVLRQDQGUHFHSWLRQRIGDWD EHWZHHQFRPSXWHUV © Oxford University Press. All rights reserved. 14 Microprocessors and Interfacing 1.9 TECHNOLOGY IMPROVEMENTS ADAPTED TO MICROPROCESSORS AND COMPUTERS 7HFKQRORJLFDO LPSURYHPHQWV DUH WDNLQJ SODFH UDSLGO\ LQ PLFURSURFHVVRU PLFURFRPSXWHUDQGSHUVRQDOFRPSXWHUV\VWHPV6RPHRIWKHVHLPSURYHPHQWVDUH OLVWHGKHUH L ,QFUHDVHLQGDWDEXVDGGUHVVEXVZLGWK 7KHSURFHVVLQJFDSDELOLW\RIWKH PLFURSURFHVVRUFDQEHGUDVWLFDOO\LPSURYHGE\LQFUHDVLQJGDWDVL]H7KLV GHYHORSPHQWFDQEHVHHQFOHDUO\IURPWKHDGYDQFHPHQWVLQPLFURSURFHVVRUV 6HFWLRQ LL ,QFUHDVHLQVSHHG $VWKHGDWDWREHSURFHVVHGE\WKHPLFURSURFHVVRUVDQG FRPSXWHUVLQFUHDVHGLQYROXPHLWEHFDPHQHFHVVDU\WRLQFUHDVHWKHVSHHGRI WKHSURFHVVRU:LWKKLJKVSHHGSURFHVVRUVWKHXVHUFDQJHWUHVXOWVTXLFNO\ HYHQZLWKODUJHGDWDYROXPHV LLL 5HGXFWLRQLQVL]HDQGLQFUHDVHLQFDSDELOLW\ 7KHWUHQGLQPLFURSURFHVVRU WHFKQRORJ\LVWRLQFOXGHDODUJHQXPEHURISHULSKHUDOVVXFKDVPHPRU\DQG ,2SRUWVZLWKLQDVLQJOHFKLS0LFURFRQWUROOHUVDUHPDQXIDFWXUHGLQWKLV IDVKLRQ,QDGGLWLRQGHYHORSPHQWVLQODUJHVFDOHLQWHJUDWLRQKDYHOHGWRWKH PDQXIDFWXUHRIVPDOOPLFURSURFHVVRUFKLSVZLWKODUJHEXLOWLQSHULSKHUDOVPress 3URFHVVRUVZLWKDODUJHDPRXQWRIÀDVKPHPRU\DUHQRZDYDLODEOHLQWKH PDUNHW LY 'HYHORSPHQWRIH[WHUQDOSHULSKHUDOV 7KHXVHRIFRPSXWHUVLQDOO¿HOGVKDYH UHVXOWHGLQWKHGHYHORSPHQWRIPDQ\IDVWDQGDGYDQFHGSHULSKHUDOGHYLFHV )RUH[DPSOHWKHDSSOLFDWLRQRIPLFURSURFHVVRUVLQPHGLFLQHKDVUHVXOWHG LQWKHGHYHORSPHQWRIPDQ\KDQGKHOGHOHFWURQLFGHYLFHVZLWKVSHFLDOL]HG LQSXWVHQVRUVRXWSXWSULQWHUVHWF)DVWHUSHULSKHUDOVFDQLQFUHDVHWKHVSHHGUniversity RISURFHVVRUH[HFXWLRQDQGSURYLGHDJRRGXVHULQWHUIDFH Y ,QFUHDVHLQPHPRU\XQLWVL]HDQGVSHHG 7KHGHYHORSPHQWVLQ,&WHFKQRORJ\ KDYHOHGWRDUHGXFWLRQLQWKHVL]HRIWKHPHPRU\XQLWVDQGDQLQFUHDVHLQ PHPRU\VSHHG7KLVUHGXFHVWKHPHPRU\DFFHVVWLPHRIWKHSURFHVVRUDQG UHVXOWVLQKLJKHUVSHHGRIH[HFXWLRQ0RUHDPRXQWRIPHPRU\SHUXQLWDUHDOxford LVSRVVLEOH YL 0LFURSURFHVVRUV DUH ODUJHO\ XVHG LQ KDQGKHOG GHYLFHV RSHUDWHG IURP D EDWWHU\ VRXUFH 7KLV KDV UHVXOWHG LQ UHVHDUFK RQ WKH UHGXFWLRQ RI SRZHU FRQVXPSWLRQLQPLFURSURFHVVRUFKLSV$VSRZHUFRQVXPSWLRQLVUHGXFHG WKHVHGHYLFHVZRUNIRUPRUHWLPHRQFHWKHEDWWHULHVDUHIXOO\FKDUJHG7KHUH DUHPDQ\GHYLFHVRSHUDWLQJDW9RUHYHQORZHUYROWDJHVDQGKDYHORZ SRZHUFRQVXPSWLRQ 1.10 INTRODUCTION TO 8085 PROCESSOR 7KH PLFURSURFHVVRU LV D VHPLFRQGXFWRU GHYLFH FRQVLVWLQJ RI HOHFWURQLF ORJLF FLUFXLWVPDQXIDFWXUHGXVLQJHLWKHUODUJHVFDOHLQWHJUDWLRQ /6, RUYHU\ODUJHVFDOH LQWHJUDWLRQ 9/6, WHFKQLTXH ,W EDVLFDOO\ FRQWDLQV UHJLVWHUV DQ DULWKPHWLF DQG ORJLFXQLWÀLSÀRSVDQGWLPLQJDQGFRQWUROFLUFXLWV$OOPLFURSURFHVVRUVZRUN XVLQJ9RQ±1HXPDQQDUFKLWHFWXUH,QWKLVDUFKLWHFWXUHWKH&38RUWKHSURFHVVRU © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 15 fetches instructions from the memory, decodes it (i.e., interprets the nature of WKHLQVWUXFWLRQFRPPDQGDQGGHYHORSVFORFNV\QFKURQL]HGVWHSVIRUH[HFXWLRQ JHQHUDWHV DSSURSULDWH FRQWURO VLJQDOV DQG ¿QDOO\ H[HFXWHV LW 7KH SURJUDP LV stored in consecutive memory locations. The execution steps are repeated for all the instructions of the program until the execution is terminated by hardware or VRIWZDUH7KHGDWDUHTXLUHGPD\EHWDNHQHLWKHUIURPPHPRU\RUIURPLQSXWSRUWV the results of the program may be either stored in the memory or transferred out through output ports. $SURJUDPLVDOLVWRILQVWUXFWLRQVIRUWKHPLFURSURFHVVRUWRH[HFXWH%HIRUH the start of execution, the complete program must be stored in the memory. Let us DVVXPHWKDWWKHVWDUWLQJDGGUHVVRIWKHVWRUHGSURJUDPLV+:KLOHUXQQLQJ WKHSURJUDPWKHPLFURSURFHVVRUPXVWEHGLUHFWHGWRµJR¶IURP+2QFHLWKDV H[HFXWHGWKHLQVWUXFWLRQLQ+LWJRHVWRWKHQH[WDGGUHVV+ DVVXPLQJ single-byte instructions) and so on until it reaches the end of the program. ,QWHOLVDQELWPLFURSURFHVVRUPDQXIDFWXUHGE\,QWHO&RUSRUDWLRQDQG LVXVXDOO\FDOOHGDJHQHUDOSXUSRVHELWSURFHVVRU,WLVXSZDUGFRPSDWLEOHZLWK PLFURSURFHVVRUZKLFKZDV,QWHO¶VHDUOLHUSURGXFW7KHUHDUHVHYHUDOIDVWHU YHUVLRQVRIWKHPLFURSURFHVVRUVXFKDV$+$+DPress QG$+ $ PLFURSURFHVVRU V\VWHP FRQVLVWV RI WKUHH IXQFWLRQDO EORFNV²FHQWUDO processing unit (CPU), input and output units, and memory units, as shown in )LJ7KH&38FRQWDLQVVHYHUDOUHJLVWHUVDQDULWKPHWLFDQGORJLFXQLW $/8 Memory (ROM) ReadUniversity only memory 5$0 OxfordRandom access memory Processor Control unit Input Output unit unit $/8 Fig. 1.4 $PLFURSURFHVVRUV\VWHP © Oxford University Press. All rights reserved. 16 Microprocessors and Interfacing DQG D FRQWURO XQLW 7KH IXQFWLRQ RI$/8 DV WKH QDPH LPSOLHV LV WR SHUIRUP arithmetic and logical operations. The control unit translates the instructions and H[HFXWHVWKHGHVLUHGWDVN 1.11 ARCHITECTURE OF 8085 7KH EORFN GLDJUDP H[SODLQLQJ WKH DUFKLWHFWXUH RI ,QWHO PLFURSURFHVVRU LV VKRZQLQ)LJ ,WLVJHQHUDOO\DYDLODEOHDVDSLQ,&SDFNDJHDQGXVHV9 IRUSRZHU,WFDQUXQDWDPD[LPXPIUHTXHQF\RI0+]7KHPRGL¿HGYHUVLRQV RI WKH SURFHVVRU KDYH WKHVH PLQLPXP FRPPRQ IHDWXUHV DQG IXQFWLRQDO similarities. 7KHLVFDOOHGDQELWSURFHVVRUVLQFHLWVGDWDOHQJWKDQGGDWDEXVZLGWKLV HLJKWELWV,WKDVDQDGGUHVVLQJFDSDELOLW\RIELWVLHLWFDQDGGUHVV .% RIPHPRU\ .% E\WHV 7KHSURFHVVRUFRQWDLQV¿YHIXQFWLRQDOXQLWV L $ULWKPHWLFDQGORJLFXQLW LL *HQHUDOSXUSRVHUHJLVWHUV (iii) Special-purpose registers (iv) Instruction register and decoder (v) Timing and control unit 1.11.1 Arithmetic and Logic Unit Press $/8LVWKHFLUFXLWU\WKDWSHUIRUPVWKHDFWXDOQXPHULFDODQGORJLFDORSHUDWLRQV $GGLWLRQ $'' VXEWUDFWLRQ 68% LQFUHPHQW ,15 GHFUHPHQW '&5 DQG FRPSDULVRQ &03 DUH WKH DULWKPHWLF RSHUDWLRQV SRVVLEOH LQ WKH ,17$ 567 75$3 ,175 RST RST SID SOD University Interrupt control Serial I/O control ELWLQWHUQDO data bus $FFXPXODWRU Temp reg. Instruction Multiplexer Oxford UHJ : = )ODJÀLS Temp reg. Temp reg. ÀRSV % & Temp reg. Temp reg. Instruction ' ( $ULWKPHWLF decoder Temp reg. Temp reg. and logic and + / Register unit machine Temp reg. Temp reg. array Reg. select $/8 cycle 6WDFNSRLQWHU encoding 3URJUDPFRXQWHU Power 9 Incrementer/Decrementer supply $GGUHVVODWFK } *1' CLK Timing and control ; $GGUHVVEXIIHU 'DWD$GGUHVVEXIIHU ; *(1 Control Status '0$ Reset CLK RD $/( IO/M +/'$ RESET OUT $±$ $'±$' OUT 5($' Fig. 1.5 )XQFWLRQDOEORFNGLDJUDPRI,QWHO © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 17 PLFURSURFHVVRU 7KH SRVVLEOH ORJLFDO RSHUDWLRQV DUH $1' $1' 25 25 H[FOXVLYH25 (;25 FRPSOHPHQW &0$ HWF 7KH$/8RIWKHSURFHVVRULVFDOOHGDFFXPXODWRURULHQWHG$/8DVRQHRI the data used in arithmetic and logic operations must be stored in the accumulator. 7KHRWKHUGDWDLVWDNHQIURPDPHPRU\ORFDWLRQRUUHJLVWHU7KHUHVXOWVRIWKH arithmetic and logical operations are stored in the accumulator. If the operation needs only one data, that data must be stored in the accumulator. 1.11.2 General-purpose Registers $UHJLVWHULVDFROOHFWLRQRIHLJKW'W\SHÀLSÀRSVZLWKSDUDOOHOLQDQGSDUDOOHO RXWRSHUDWLRQ$ÀLSÀRSFDQRQO\VWRUHRQHELWDWDWLPH7KHUHIRUHWRKDQGOH HLJKWELWVDWDWLPHHLJKWÀLSÀRSVDUHUHTXLUHGDQGKHQFHWKHWHUPELWUHJLVWHU Though the registers are all storage areas inside the microprocessor, they differ in the purpose of storage. The general-purpose registers are used to store only the data that is being used by the program under execution and the results obtained from it. These general-purpose registers are user accessible through programs. 5HJLVWHUV%&'(+DQG/DUHWKHJHQHUDOSXUSRVHUHJLVWHUVLQWKH DVVKRZQLQ)LJ7KH\FDQDOVREHFDOOHGVFUDWFKSDGUHJLVWHUV,QDOPRVWDOO arithmetic and logical Press operations, these registers $FFXPXODWRU$ )ODJUHJLVWHU are used as the second % & RSHUDQGVWKH¿UVWRSHUDQG being the accumulator ' ( $ 7KH JHQHUDOSXUSRVH + / UHJLVWHUV DUH DOO ELW 6WDFNSRLQWHU 63 registers but they can be University KDQGOHGDVELWUHJLVWHUV 3URJUDPFRXQWHU 3& as well. This can be Data bus $GGUHVVEXV achieved by combining OLQHV ELGLUHFWLRQDO OLQHV XQLGLUHFWLRQDO the register pairs B and C, D and E, and H andOxford L to SHUIRUPELWRSHUDWLRQV Fig. 1.6 Registers of Intel 8085 They are then named register pairs BC, DE, and HL, respectively. $PRQJ WKHVH SDLUV +/ KDV D VSHFLDO VLJQL¿FDQFH $ IHZ PHPRU\UHODWHG LQVWUXFWLRQVRIWKH UHIHULQVWUXFWLRQVHW XVHWKH+/SDLUDVDPHPRU\SRLQWHU )RU H[DPSOH WKH LQVWUXFWLRQ 029$ 0 WUDQVIHUV WKH FRQWHQW RI WKH PHPRU\ location to which the HL pair is pointing, to the accumulator. The HL pair is pre- loaded with the memory address in which data is available. 1.11.3 Special-purpose Registers 7KHUHDUHDOVRVSHFLDOSXUSRVHUHJLVWHUVWKDWDUHGHGLFDWHGWRDVSHFL¿FIXQFWLRQ 7KH DFFXPXODWRU ÀDJ UHJLVWHU SURJUDP FRXQWHU 3& DQG VWDFN SRLQWHU 63 FRQVWLWXWHWKHVSHFLDOUHJLVWHUVLQWKHPLFURSURFHVVRU 1.11.3.1 Accumulator 7KH DFFXPXODWRU LV DQ ELW UHJLVWHU LW LV D SDUW RI WKH$/8 DQG LV WKH PRVW © Oxford University Press. All rights reserved. 18 Microprocessors and Interfacing LPSRUWDQW UHJLVWHU ,W LV XVHG WR VWRUH ELW GDWD DQG WR SHUIRUP DULWKPHWLF DQG logical operations. The output of an operation is also stored in the accumulator. 7KHDFFXPXODWRULVLGHQWL¿HGDVUHJLVWHU$LQWKHLQVWUXFWLRQVHWRIWKH7KH SURJUDPPHUFDQXVHLWDWDQ\WLPHWRVWRUHDQELWELQDU\QXPEHU%HLQJRQO\ HLJKWELWVORQJLWFDQRQO\KROGRQHE\WHDWDWLPH$Q\SUHYLRXVGDWDVWRUHGLQWKLV UHJLVWHUZLOOEHRYHUZULWWHQDVVRRQDVQHZGDWDLVVWRUHG7KHPLFURSURFHVVRU communicates with input/output devices only through the accumulator. 1.11.3.2 Flag Register 7KLVLVDVSHFLDOELWUHJLVWHU(DFKELWRIWKHÀDJUHJLVWHULVTXLWHLQGHSHQGHQWRIWKH others. In all other registers, each bit is part of a single binary byte value and hence HDFKELWZRXOGKDYHDQXPHULFDOYDOXH7KHÀDJLVDQELWUHJLVWHUXVHGWRLQGLFDWH the status of a recent arithmetic or logical operation. It may be set or reset after an arithmetic or logical operation according to the condition of the processed data. The ¿YHÀDJELWVDUH]HUR = FDUU\ &< VLJQ 6 SDULW\ 3 DQGDX[LOLDU\FDUU\ $& WKHLUELWSRVLWLRQVLQWKHÀDJUHJLVWHUDUHVKRZQLQ)LJJJ7KHUHPDLQLQJWKUHHELWV ''DQG' RIWKHÀDJ register remain unassigned; SZ;$&; P ; CY WKH\DUHPDUNHGZLWKDQ;WR D7 ' ' 'PressD3 ' D1 D0 show that they are not used and are don’t cares. Fig. 1.7 Flag register $Q\ÀDJUHJLVWHUELWLVVDLGWREHµVHW¶ZKHQLWVYDOXHLVDQGµFOHDUHG¶ZKHQLWV YDOXHLV7KHPRVWFRPPRQO\XVHGÀDJVDUH]HURFDUU\DQGVLJQ$&ÀDJFDQQRW be accessed externally. 6LJQÀDJ 6 7KHVLJQÀDJLVMXVWDFRS\RIWKHELW' PRVWVLJQL¿FDQWELW² 06% RI WKH DFFXPXODWRU$ QHJDWLYHUniversity QXPEHU KDV D LQ ELW DQG D SRVLWLYH QXPEHUKDVDLQ¶VFRPSOHPHQWUHSUHVHQWDWLRQ7KLVÀDJLQGLFDWHVWKHVLJQRI the number. (It may be recalled that signed magnitude numbers use 1 to indicate DQHJDWLYHQXPEHUDQGWRLQGLFDWHDSRVLWLYHQXPEHU 7KLVÀDJFDQEHXVHGLQ signed arithmetic operations.Oxford =HURÀDJ = 7KH]HURÀDJLVVHWLIDQDULWKPHWLFRSHUDWLRQUHVXOWVLQD]HUR,W sets, i.e., it changes to binary 1 if the result in the accumulator is zero; if not, it remains reset, i.e., at binary 0. &DUU\ÀDJ & 7KHFDUU\ÀDJLVVHWZKHQDFDUU\LVJHQHUDWHGLQWKHSURFHVV of an arithmetic operation in the accumulator. When addition is carried out, it VRPHWLPHVUHVXOWVLQDQLQWKELWEHLQJFDUULHGRYHUWRWKHQH[WE\WH7KH&ÀDJ FRSLHVWKHYDOXHRIWKHFDUU\ZKLFKLVDQH[WUDELWIURP',WDOVRUHÀHFWVWKH value of the borrow in subtractions. $X[LOLDU\ FDUU\ ÀDJ $& 7KH DX[LOLDU\ FDUU\ ÀDJ LV VHW ZKHQ DQ DX[LOLDU\ carry is generated in the process of an arithmetic operation in the accumulator, LHZKHQDFDUU\UHVXOWVIURPELW'DQGSDVVHVRQWR' IURPWKHORZHUQLEEOH to the higher nibble). This carry is also called half-carry. It may also occur in the SURFHVVRIDVXEWUDFWLRQRSHUDWLRQ,QRWKHUZRUGVWKLVÀDJLVVHWLIWKHVXEWUDFWLRQ operation results in borrowing from the higher nibble. © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 19 3DULW\ÀDJ 3 7KHSDULW\ÀDJLVVHWLIWKHFRQWHQWRIWKHDFFXPXODWRUDIWHUDQ DULWKPHWLFRSHUDWLRQKDVDQHYHQQXPEHURIV2WKHUZLVHWKHSDULW\ÀDJLVUHVHW It is set for operation in the even parity mode. 1.11.3.3 Program Counter 3URJUDPFRXQWHU 3& LVDELWUHJLVWHUWKDWDOZD\VSRLQWVWRWKHDGGUHVVRIWKH next instruction to be executed. In other words, this register is used to sequence the H[HFXWLRQRIWKHLQVWUXFWLRQV$IWHUH[HFXWLRQRIHYHU\LQVWUXFWLRQWKHFRQWHQWRI the memory location indicated by the PC is moved to the instruction register and WKH3&LVORDGHGZLWKWKHQH[WDGGUHVV,WNHHSVWUDFNRIDSURJUDPE\FRXQWLQJWKH memory address from which the next byte is to be fetched, and hence the name program counter. 1.11.3.4 Stack Pointer 6WDFNLV DQ DUUD\RI PHPRU\ORFDWLRQVRUJDQL]HGLQ ODVWLQ¿UVWRXW /,)2 RU ¿UVWLQODVWRXW ),/2 IDVKLRQ,WLVDFFHVVHGXVLQJDELWSRLQWHUUHJLVWHUFDOOHG VWDFNSRLQWHU 63 ZKLFKKROGVWKHDGGUHVVRIWKHPHPRU\ORFDWLRQRIWKHWRSRI WKHVWDFN7KHSURJUDPPHUFDQUHVHUYHDQGDOORFDWHDVHULHVRI5$0ORFDWLRQV WREHXVHGDVDVWDFNDQGDFFRUGLQJO\LQLWLDOL]HWKHVWDFNSRLQWHU7KHUDQJHRIPress VWDFNPHPRU\ORFDWLRQVPXVWEHFKRVHQFDUHIXOO\VRWKDWLWGRHVQRWDIIHFWWKH SURJUDPVSDFH,QDOOPLFURSURFHVVRUEDVHGV\VWHPVWKHVWDFNLVPDLQO\XVHGWR store the return address of the main program when a subroutine is called. While WKHSURJUDPPHUXVHVWKHVWDFNIRUVWRUDJHDQGUHWULHYDORIGDWDWKHPLFURSURFHVVRU XVHVWKHVWDFNGXULQJVXEURXWLQHFDOOV&DUHPXVWEHWDNHQE\WKHSURJUDPPHUWR HQVXUHWKDWWKHGDWDVWRUHGLQWKHVWDFNLVUHWULHYHGSURSHUO\VRWKDWWKHGDWDVWRUHG LQWKHVWDFNE\WKHSURFHVVRULVQRWDIIHFWHGUniversity 1.11.4 Instruction Register and Decoder ,WLVDQELWUHJLVWHUWKDWWHPSRUDULO\VWRUHVWKHLQVWUXFWLRQVGUDZQIURPPHPRU\ locations, before their actual execution. The content of the register is decoded by the decoder circuitry, where the nature of the operation to be performed is decided (interpreted). In addition,Oxford there are two temporary registers W and Z, which are controlled internally and not available for user access. 1.11.5 Timing and Control Unit The timing and control unit gets commands from the instruction decoder and issues signals on the data bus, address bus, and control bus. The following sections explain the operation of the various buses and the timing. $W\SLFDOPLFURSURFHVVRUFRPPXQLFDWHVZLWKPHPRU\DQGLQSXWRXWSXWGHYLFHV using buses. There are three types of buses—the address bus, the data bus, and the control bus. 1.11.5.1 Data Bus 7KHPLFURSURFHVVRUSHUIRUPVLWVIXQFWLRQVXVLQJZLUHVRUOLQHVFDOOHGEXVHV)RU H[DPSOHDQELWPLFURSURFHVVRUQRUPDOO\XVHVHLJKWZLUHVWRFDUU\GDWDEHWZHHQ WKHPLFURSURFHVVRUDQGWKHPHPRU\7RPDNHWKHLUUHSUHVHQWDWLRQVLPSOHWKHGDWD wires with common functions are grouped together and referred to as the data bus. © Oxford University Press. All rights reserved. 20 Microprocessors and Interfacing The data bus (D0–D7) is a two-way bus carrying data around the system. Information going into the microprocessor and results coming out of the microprocessor are through this data bus. It is used for transfer of binary information between the microprocessor, memory, and peripherals. The lower group of eight DGGUHVVOLQHV$±$LVPXOWLSOH[HGZLWKWKHGDWDEXVLQRUGHUWRUHGXFHWKHSLQ count. Therefore, the multiplexed lower group of address lines and data lines is PRUHJHQHUDOO\GHQRWHGDV$'±$' 1.11.5.2 Address Bus The address bus carries addresses and is a one-way bus from the microprocessor to the memory or other devices. It is a group of sixteen unidirectional lines that allows ÀRZRIDGGUHVVIURPWKHSURFHVVRUWRLWVSHULSKHUDOGHYLFHV(DFKSHULSKHUDODQG PHPRU\ORFDWLRQLVLGHQWL¿HGE\DELWELQDU\QXPEHUFDOOHGDGGUHVV,WIROORZV WKDWWKHPD[LPXPQXPEHURIPHPRU\ORFDWLRQVWKDWFDQEHDGGUHVVHGE\WKH SURFHVVRULV bytes .%,WVEDVLFIXQFWLRQLVWRLGHQWLI\DSHULSKHUDORU memory location. 7KHDGGUHVVEXVOLQHVDUHJHQHUDOO\LGHQWL¿HGDV$±$7KHDGGUHVVEXVKDV HLJKWKLJKHURUGHUDGGUHVVOLQHV $±$ ZKLFKDUHXQLGLUHFWLRQDO7KHORZHU RUGHUHLJKWOLQHV $±$ DUHPXOWLSOH[HG WLPHVKDUHG ZLWKWKHHLJKWGDWDELWVPress (D0–D7) and hence, they are bidirectional. When the instruction is executed, these lines carry the address bits during the early part, and the eight data bits during the later part. To separate the address from the data, a latch is used externally to save the address before the function of the bits changes. 1.11.5.3 Control Bus The control bus carries control signalsUniversity that are partly unidirectional and partly ELGLUHFWLRQDO)RUDPLFURSURFHVVRUWRIXQFWLRQFRUUHFWO\WKHVHFRQWUROVLJQDOVDUH vital. The control bus typically consists of a number of single lines that coordinate DQGFRQWUROPLFURSURFHVVRURSHUDWLRQV)RUH[DPSOHDUHDGZULWHFRQWUROVLJQDO will indicate whether memory is being written into or read from. Thus, they are individual lines thatOxford provide a pulse to indicate the operation of the microprocessor. ,QIDFWWKHPLFURSURFHVVRUJHQHUDWHVVSHFL¿FFRQWUROVLJQDOVIRUHYHU\RSHUDWLRQ which in turn are used to identify the type of device the processor intends to communicate with. The following points describe the control and status signals RIWKHSURFHVVRU L $/( RXWSXW $GGUHVV/DWFK(QDEOHLVDSXOVHWKDWLVSURYLGHGZKHQDQ DGGUHVV DSSHDUV RQ WKH$'±$' OLQHV DIWHU ZKLFK LW EHFRPHV 7KLV VLJQDOFDQEHXVHGWRHQDEOHDODWFKWRVDYHWKHDGGUHVVELWVIURPWKH$' lines, thereby de-multiplexing the address bus and data bus. (ii) RD DFWLYHORZRXWSXW 7KH5HDGVLJQDOLQGLFDWHVWKDWGDWDDUHEHLQJUHDG from the selected I/O or memory device and that they are available on the data bus. (iii) WR DFWLYHORZRXWSXW 7KH:ULWHVLJQDOLQGLFDWHVWKDWWKHGDWDRQWKHGDWD bus are to be written into a selected memory or I/O location. (iv) IO/M RXWSXW ,WLVDVLJQDOWKDWGLVWLQJXLVKHVEHWZHHQDPHPRU\RSHUDWLRQ DQGDQ,2RSHUDWLRQ$QDFWLYHORZRQWKLVVLJQDOVKRZVLWLVDPHPRU\ © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 21 operation (IO/M = 0) and a high on this line indicates an I/O operation (IO/M = 1). Table 1.2 Status signals and Y 6 DQG 6 RXWSXW 7KHVH DUH VWDWXV associated operations VLJQDOV XVHG WR VSHFLI\ WKH NLQG RI operation being performed. The status S1 S0 States signals combine with I/O signals to 0 0 Halt govern various operations; they are 0 1 Write OLVWHGLQ7DEOH,IERWK6DQG6 1 0 Read are low, the operation of the processor 1 )HWFK tends to halt. If S0 is low and S1 is high, the processor reads data. If S0 is high and S1 is low, the processor writes data onto a memory or I/O device. If both S0 and S1 are high, the fetch operation is performed. 7KHVFKHPDWLFUHSUHVHQWDWLRQRIWKHEXVVWUXFWXUHVKRZQLQ)LJH[SODLQV how the movement of data within the computer is accomplished by a series of EXVHV$GGUHVVLQIRUPDWLRQGDWDDQGFRQWUROVLJQDOVKDYHWREHFDUULHGDURXQG inside the microprocessor as well as in the external system. Hence, the buses are present both internally and externally. Press YL ,QWHUUXSWV 7KHVHVLJQDOVDUHXVHGWRPDNHWKHPLFURSURFHVVRUUHVSRQGWRKLJK priority externally initiated signals. When an interrupt signal is detected by the processor, it suspends the execution of the current program and executes the SURJUDPFRUUHVSRQGLQJWRWKHLQWHUUXSWVLJQDOLQVWHDG)LYHLQWHUUXSWVLJQDOV ,175567567567DQG7UDS DUHDYDLODEOHWRIDFLOLWDWHWKH SURFHVVRUWRUHFHLYHDQGDFNQRZOHGJHWKHLQWHUUXSWFDOORISHULSKHUDOV7KH SURFHVVRUDFFHSWVWKUHHPRUHH[WHUQDOO\LQLWLDWHGVLJQDOV²University 5(6(7,1, Hold, and Ready as inputs. The following points explain these signals in EULHI D ,175 LQSXW ,WLVDJHQHUDOSXUSRVHLQWHUUXSWUHTXHVWVLJQDO,WLVDQ active high signal. (b) ,17$ RXWSXW ,WLVXVHGWRDFNQRZOHGJHDQLQWHUUXSW,WLVDQDFWLYHORZOxford signal. F 5HVWDUWLQWHUUXSWV LQSXW 7KHVHDUHYHFWRUHGLQWHUUXSWVWKDWWUDQVIHUWKH $ $GGUHVVEXV $ Memory Input Output Real world MPU data D7 Data bus D0 Control bus Fig. 1.8 6FKHPDWLFUHSUHVHQWDWLRQRIWKHEXVVWUXFWXUH © Oxford University Press. All rights reserved. 22 Microprocessors and Interfacing SURJUDPFRQWUROWRVSHFL¿FPHPRU\ORFDWLRQV7KH\KDYHKLJKHUSULRULW\ WKDQ,175LQWHUUXSWV7KHSULRULW\RUGHULV567567DQG567 G 7UDS LQSXW ,WLVDQRQPDVNDEOHLQWHUUXSWLHLWFDQQRWEHVWRSSHGRU RYHUULGGHQE\DQ\FRPPDQG,WKDVWKHKLJKHVWSULRULW\DPRQJDOO interrupts. (e) 5(6(7,1 LQSXW :KHQWKHVLJQDORQWKLVSLQJRHVORZWKHSURJUDP counter is set to zero and the processor is reset. It is an active low signal. I 5(6(7287 RXWSXW 7KLVVLJQDOFDQEHXVHGWRUHVHWRWKHUGHYLFHVWKDW are connected to the processor. It is an active high signal. J +ROG LQSXW 7KLV VLJQDO LQGLFDWHV WKDW D SHULSKHUDO VXFK DV D GLUHFW PHPRU\DFFHVV '0$ FRQWUROOHULVUHTXHVWLQJWKHXVHRIWKHDGGUHVV and data buses. K +/'$ RXWSXW ,WLVDQDFNQRZOHGJHVLJQDOWKDWLVVHQWLQUHVSRQVHWR the Hold request. During the Hold state, the peripheral (I/O) devices get control over the data and address buses for data transfer to and from PHPRU\7KLVRSHUDWLRQLVFDOOHGGLUHFWPHPRU\DFFHVV '0$ '0$ is useful when high-speed peripherals want toPress transfer data to and from memory. The processor does not intervene during this period. L 5HDG\ LQSXW ,W LV D VLJQDO WKDW VHUYHV WR GHOD\ WKH PLFURSURFHVVRU read/write signals until a slow-responding peripheral is ready to send or accept data. If this signal goes low, then the processor is allowed to wait IRUDQLQWHJUDOQXPEHURIFORFNF\FOHVXQWLO5HDG\EHFRPHVKLJK7KH 5HDG\VLJQDOPXVWEHV\QFKURQL]HGZLWKWKHSURFHVVRUFORFN University ; 1 VCC ; 39 HOLD '0$ RESET OUT 3 +/'$ *1' Serial SOD 37 CLK (OUT) V I/O signals SID 5(6(7,1 ;7$/ Higher-order 75$3 Oxford 5($'< ;; VCCVSS address bus 567 7 IO/M $ 567 33 S1 $ 567 9 RD SID Multiplexed lower-order ,175 10 31 WR SOD 75$3 address/data ,17$ 11 30 $/( bus 567 $' $' S0 567 $' 13 $ 567 $' ,175 $/( $' $ ,17$ S1 $' $ 5($'< S0 HOLD IO/M $' $ +/'$ $' 17 $ RESET RD $' $ ,1 WR $' 19 $ VSS $ RESET OUT CLK (OUT) (a) (b) Fig. 2.7 GHWDLOV D 3LQGLDJUDP E 6LJQDOJURXSV © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 23 7KHW\SLFDOSLQOD\RXWDQGVLJQDOJURXSVRIWKHPLFURSURFHVVRUDUHVKRZQ LQ)LJV D DQG E UHVSHFWLYHO\7KHLVDYDLODEOHZLWKSLQVDVD GXDOLQOLQHSDFNDJH ',3 ,QWHOKDVSLQVRSHUDWHVDW 0+]FORFNIUHTXHQF\DQGUHTXLUHV V for power supply. 1.11.5.4 Serial I/O Signals There are two signals to implement serial transmission. They are serial input data (SID) and serial output data (SOD). The data bits are sent over a single line, one bit at a time, in serial transmission. (i) 6,' LQSXW 7KH ELW GDWD RQ WKLV OLQH LV ORDGHG LQ WKH VHYHQWK ELW RI WKH accumulator whenever a RIM instruction is executed. (ii) 62' RXWSXW 7KH RXWSXW 62' LV VHW RU UHVHW DV VSHFL¿HG E\ WKH 6,0 instruction. 5,0DQG6,0LQVWUXFWLRQVKDYHEHHQH[SODLQHGLQGHWDLOLQ&KDSWHU 1.11.5.5 Power Supply and System Clock 7KH IROORZLQJ SLQV DUH DYDLODEOH LQ WKH FKLS WR SURYLGH SRZHU DQG FORFN VLJQDOWRWKHSURFHVVRU Press (i) ; ; LQSXW $ PLFURSURFHVVRU QHHGV D VTXDUH ZDYH FORFN VLJQDO WR HQVXUHWKDWDOOLQWHUQDORSHUDWLRQVDUHV\QFKURQL]HG$FU\VWDORU5±&RU/±& QHWZRUNLVFRQQHFWHGWRWKHVHWZRSLQV7KHFU\VWDOIUHTXHQF\LVLQWHUQDOO\ divided by two to give the operating system frequency. There are three advantages in increasing the frequency of a crystal—as frequency increases, the crystal size becomes smaller, and the crystal becomes lighter and cheaper. 7KHUHIRUHFORFNFLUFXLWVLQFOXGHDGLYLGHE\WZRFLUFXLWVRWKDWDGRXEOHUniversity frequency crystal can be used. So, to run the microprocessor at 3 MHz, a 0+]FU\VWDOVKRXOGEHFRQQHFWHGWRWKH;DQG;SLQV7KHFU\VWDOLV SUHIHUUHG DV D FORFN VRXUFH EHFDXVH RI LWV KLJK VWDELOLW\ ODUJH 4 TXDOLW\ IDFWRU DQGDEVHQFHRIIUHTXHQF\GULIWLQJZLWKDJLQJ:LWKRXWDFORFNVLJQDO the microprocessorOxford cannot execute any program. (ii) &/. RXWSXW 7KLVRXWSXWFORFNSLQLVXVHGWRSURYLGHWKHFORFNVLJQDOWRWKH rest of the system. 3RZHUVXSSOLHV VCC² V supply; VSS—ground reference. 1.12 MICROPROCESSOR INSTRUCTIONS Every microprocessor has its own instruction set. Based on the design of the $/8DQGWKHGHFRGLQJXQLWPLFURSURFHVVRUPDQXIDFWXUHUVJHQHUDOO\OLVWRXWWKH instructions for every microprocessor manufactured. The instruction set consists of both assembly language mnemonics and the corresponding machine code. 7KHSXUSRVHRIWKHLQVWUXFWLRQVHWLVWRIDFLOLWDWHWKHGHYHORSPHQWRIHI¿FLHQW programs by the users. The instruction set is based on the architecture of the processor. So to understand the instruction set of a processor, it is necessary to understand the basic architecture of the microprocessor and the user-accessible © Oxford University Press. All rights reserved. 24 Microprocessors and Interfacing UHJLVWHUVLQLW$Qinstruction is a bit pattern that is decoded inside a microprocessor WRSHUIRUPDVSHFL¿FIXQFWLRQ7KHDVVHPEO\ODQJXDJHPQHPRQLFVDUHWKHFRGHVIRU these binary patterns so that the user can easily understand the functions performed by these instructions. The entire group of instructions that a microprocessor can handle is called its instruction set; this determines the microprocessor’s IXQFWLRQDOLW\7KH,QWHOSURFHVVRUKDVLWVRZQVHWRILQVWUXFWLRQVOLVWHGERWK LQPQHPRQLFVDQGPDFKLQHFRGHDOVRFDOOHGDVREMHFWFRGH$VWKHLVDQ ELWSURFHVVRUWKHPDFKLQHFRGHVIRUWKHLQVWUXFWLRQVDUHDOVRELWVZLGH 7KHV\QWD[IRULQVWUXFWLRQVPD\FRQWDLQRQHRUPRUHRIWKHIROORZLQJ QRWDWLRQV 5 ELWUHJLVWHU $%&'(+DQG/ Rs = Source register 5G 'HVWLQDWLRQUHJLVWHU} $%&'(+DQG/ Rp = Register pair (BC, DE, HL, and SP) 3 3RUWDGGUHVV ELWELQDU\QXPEHURUWZRKH[GLJLWV ELW ELWGDWDRUWZRKH[GLJLWV ELW ELWGDWDDGGUHVVRUIRXUKH[GLJLWV ( ) = Contents of Press 1.13 CLASSIFICATION OF INSTRUCTIONS 0LFURSURFHVVRU LQVWUXFWLRQV FDQ EH FODVVL¿HG EDVHG RQ SDUDPHWHUV VXFK DV functionality, length, and operand addressing. 1.13.1 Based on Functionality %DVHGRQWKHIXQFWLRQDOLW\WKHLQVWUXFWLRQVDUHFODVVL¿HGLQWRWKHIROORZLQJ¿YHUniversity FDWHJRULHV L 'DWDWUDQVIHU FRS\ RSHUDWLRQV LL $ULWKPHWLFRSHUDWLRQV (iii) Logical operations (iv) Branching operations (v) Machine controlOxford operations 1.13.1.1 Data Transfer (Copy) Operations This group of instructions copies data from a location called source register to another location called destination register. Generally, the contents of the source UHJLVWHUDUHQRWPRGL¿HG$OWKRXJKWKHWHUPdata transfer is used for the copy operation, it is misleading because it implies that the contents of the source memory location are destroyed. The various types of data transfer are listed in Table 1.3 along with examples of each type. Table 1.3 Types of data transfer Type Example 7UDQVIHUULQJGDWDEHWZHHQRQHUHJLVWHU 029$'²&RSLHVWKHFRQWHQWRI and another register D to the accumulator 6WRULQJDGDWDE\WHLQDUHJLVWHURU 09,&+²/RDGVUHJLVWHU&ZLWK PHPRU\ORFDWLRQ WKHGDWD+ (Contd) © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 25 Table 1.3 Types of data transfer (Contd) Type Example 7UDQVIHUULQJGDWDEHWZHHQDPHPRU\ /'$+²/RDGVWKHFRQWHQWVRI ORFDWLRQDQGDUHJLVWHU PHPRU\ORFDWLRQ+LQWKHDFFXPXODWRU 7UDQVIHUULQJGDWDEHWZHHQDQ,2GHYLFH ,13257²7UDQVIHUVGDWDIURPDQLQSXW and the accumulator device to the accumulator 1.13.1.2 Arithmetic Operations $ULWKPHWLFRSHUDWLRQVLQFOXGHDGGLWLRQVXEWUDFWLRQLQFUHPHQWDQGGHFUHPHQW$V WKHKDVDQDFFXPXODWRURULHQWHG$/8RQHRIWKHGDWDXVHGLQWKHDULWKPHWLF operations is stored in the accumulator; the result is also stored in the accumulator. $ULWKPHWLFDQGORJLFDORSHUDWLRQVFDQQRWEHH[HFXWHGZLWKRXWWKHDFFXPXODWRU $GGLWLRQ $'' 7KH DGGLWLRQ LQVWUXFWLRQV RI WKH DGG WKH FRQWHQWV RI a register or memory location with the contents of the accumulator. The result LV VWRUHGLQWKHDFFXPXODWRU7KH,QWHO LQVWUXFWLRQVHWVXSSRUWV WZR W\SHV RIDGGLWLRQLQVWUXFWLRQV²ZLWKDQGZLWKRXWDGGLWLRQRIWKHFDUU\ÀDJFRQWHQWWR WKHOHDVWVLJQL¿FDQWELWRIWKHQXPEHUV7KHLQVWUXFWLRQVHWDOPressVRVXSSRUWVELW addition, i.e., the content of the HL register pair can be added to that of another register pair and the result stored in the HL register pair. 6XEWUDFWLRQ 68% 7KH LQVWUXFWLRQ VHW RI WKH VXSSRUWV WZR W\SHV RI VXEWUDFWLRQ²ZLWK ERUURZ DQG ZLWKRXW ERUURZ /LNH DGGLWLRQ WKH VXEWUDFWLRQ operation also uses the accumulator as reference, i.e., it subtracts the content of a register or memory location from that of the accumulator and stores the result in the accumulator. University Increment/Decrement These operations can be used to increment or decrement WKHFRQWHQWVRIDQ\UHJLVWHUUHJLVWHUSDLURUPHPRU\ORFDWLRQ8QOLNHWKHDULWKPHWLF and logical operations, the increment and decrement operations need not be based upon the accumulator.Oxford 1.13.1.3 Logical Operations Logical instructions are also accumulator-oriented, i.e., they require one of the operands to be placed in the accumulator. The other operand can be any register or memory location. The result is stored in the accumulator. The operations that use WZRRSHUDQGVDUHORJLFDO$1'25DQG(;257KHRSHUDWLRQWKDWXVHVDVLQJOH RSHUDQG LHWKHDFFXPXODWRU LVWKHORJLFDOFRPSOHPHQWRU127RSHUDWLRQ 7KHLQVWUXFWLRQVHWRIWKHVXSSRUWVURWDWLRQRIWKHGDWDVWRUHGLQDFFXPXODWRU The data can be rotated left or right, through the carry or without the carry. 7KHPRVWLPSRUWDQWLQVWUXFWLRQLVWKHFRPSDUHLQVWUXFWLRQ7KLVLQVWUXFWLRQ is used to compare register or memory content with the accumulator content. The UHVXOWRIFRPSDULVRQVXFKDVHTXDOWRJUHDWHUWKDQRUOHVVWKDQLVUHÀHFWHGLQWKH ÀDJUHJLVWHUELWV 1.13.1.4 Branching Operations Branching instructions are important for programming a microprocessor. These © Oxford University Press. All rights reserved. 26 Microprocessors and Interfacing instructions can transfer control of execution from one memory location to another, HLWKHUFRQGLWLRQDOO\RUXQFRQGLWLRQDOO\%UDQFKLQJFDQWDNHSODFHLQWKHIROORZLQJ WZRZD\V L ([HFXWLRQFRQWUROFDQQRWUHWXUQWRWKHSRLQWRIEUDQFKLQJ([DPSOH -XPS instructions (ii) Execution control can return to the point of branching, which is stored by the ([DPSOH 6XEURXWLQHFDOOLQVWUXFWLRQV 1.13.1.5 Machine Control Operations These instructions can be used to control the execution of other instructions. They include halting the operation of the microprocessor, interrupting program execution, HWF'HWDLOHGH[SODQDWLRQVIRULQVWUXFWLRQVDUHJLYHQLQ6HFWLRQ 1.13.2 Based on Length %DVHG RQ WKH OHQJWK RI WKH PDFKLQH ODQJXDJH FRGH LQVWUXFWLRQV FDQ EH FODVVL¿HGLQWRWKHIROORZLQJWKUHHW\SHV (i) One-byte instructions (ii) Two-byte instructions (iii) Three-byte instructions $VVHPEO\ ODQJXDJH LQVWUXFWLRQV VKRXOG EH FRQYHUWHGPress LQWR PDFKLQH FRGH IRU storage and execution by the processor. So the length of the machine language code instructions determines the length of the program. This in turn determines the amount of memory required for the program. 1.13.2.1 One-byte Instructions Instructions that require only one byte in machine language are called one-byte instructions. These instructions justUniversity have the machine code or opcode alone to represent the operation to be performed. The common examples are the instructions that have their operands within the processor itself. Some examples of one-byte LQVWUXFWLRQVDUHJLYHQLQ7DEOH(YHQWKRXJKWKHLQVWUXFWLRQ$''0DGGVWKH content of a memory location to that of the accumulator, its machine code requires only one byte. Oxford Table 1.4 2QHE\WHLQVWUXFWLRQV Let us now understand the instruction MOV Rd, Rs. This Opcode Operand Machine code/Opcode/ instruction copies the contents of Hex code source register Rs to destination 029 $% register Rd. (Rd Å Rs) $'' 0 It is coded as 01dddsss. Here, ;5$ $ $) ddd is the binary code of one of the seven general-purpose registers that is the destination of the data and sss is the binary code of the source register. Example: MOV A, B (coded as 01111000 = 78H) 1.13.2.2 Two-byte Instructions Instructions that require two bytes in machine code are called as two-byte LQVWUXFWLRQV 7KH ¿UVW E\WH RI WKH WZRE\WH LQVWUXFWLRQV LV WKH RSFRGH ZKLFK © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 27 VSHFL¿HV WKH RSHUDWLRQ WR EH SHUIRUPHG7KH VHFRQG E\WH LV WKH ELW RSHUDQG ZKLFKLVHLWKHUDQELWQXPEHURUDQDGGUHVV6RPHFRPPRQH[DPSOHVRIWZR E\WHLQVWUXFWLRQVDUHOLVWHGLQ7DEOH Table 1.5 7ZRE\WHLQVWUXFWLRQV Opcode Operand Machine code/Opcode/Hex code Byte description 09, $)+ ( )LUVWE\WH ) 6HFRQGE\WH $', )+ & )LUVWE\WH ) 6HFRQGE\WH ,1 + '% )LUVWE\WH 6HFRQGE\WH The instruction is stored in two consecutive memory locations. MVI R, data—(R data) Example: MVI A, 32H (coded as 3E 32 in two contiguous bytes) This is an example of immediate addressing. Press 7KHIROORZLQJWZRLQVWUXFWLRQVDUHDOVRH[DPSOHVRIWZRE\WHLQVWUXFWLRQV L $',GDWD $ $GDWD LL 287SRUW ZKHUHSRUWLVDQELWGHYLFHDGGUHVV 3RUW $ 6LQFHWKHE\WH is not the data itself, but points directly to where it is located, this is called GLUHFWDGGUHVVLQJ)RUDGHWDLOHGDFFRXQWRIDGGUHVVLQJPRGHVVHH6HFWLRQ 1.13.3. University 1.13.2.3 Three-byte Instructions Instructions that require three bytes in machine code are called three-byte LQVWUXFWLRQV,QPDFKLQHODQJXDJHWKH¿UVWE\WHRIWKHWKUHHE\WHLQVWUXFWLRQV LVWKHRSFRGHZKLFKVSHFL¿HVWKHRSHUDWLRQWREHSHUIRUPHG7KHQH[WWZRE\WHV UHIHUWRWKHELWRSHUDQGZKLFKLVHLWKHUDELWQXPEHURUOxford WKHDGGUHVVRID memory location. Some common examples of three-byte instructions are listed in 7DEOH Table 1.6 7KUHHE\WHLQVWUXFWLRQV Opcode Operand Machine code/Opcode/Hex code Byte description -03 + & )LUVWE\WH 6HFRQGE\WH 90 Third byte /'$ + $ )LUVWE\WH 6HFRQGE\WH 7KLUGE\WH /;, ++ )LUVWE\WH 6HFRQGE\WH 7KLUGE\WH © Oxford University Press. All rights reserved. 28 Microprocessors and Interfacing 7KHLQVWUXFWLRQ/;,5SELWGDWDFDQEHH[SODLQHGDVIROORZV 5SLVRQHRIWKHSDLUVRIUHJLVWHUV%&'(RU+/ZKLFKDUHXVHGDVELW UHJLVWHUV7KHWZRGDWDE\WHVDUHWREHVWRUHGDVDELWQXPEHULQ/DQG+LQ VHTXHQFH/;,++LVFRGHGDV+++LQWKUHHE\WHV 7KLVLVDQ example of immediate addressing.) ,QH[HFXWLQJWKHLQVWUXFWLRQ/'$DGGUWKHDFFXPXODWRULVORDGHGZLWKWKHPHPRU\ FRQWHQWRIWKHDGGUHVVJLYHQLQWKHLQVWUXFWLRQ$GGULVDELWDGGUHVV/'$+ LVFRGHGDV$+++ 7KLVLVDQH[DPSOHRIGLUHFWDGGUHVVLQJ 1.13.3 Addressing Modes in Instructions Every instruction in a program has to operate on data. The process of specifying the data to be operated on by the instruction is called addressing (I¿FLHQW software development for the microprocessor requires complete familiarity with the addressing mode employed for each instruction. )RUH[DPSOHWKHLQVWUXFWLRQV 029%$DQG09,$+DUHXVHGWRFRS\GDWDIURPDVRXUFHWRDGHVWLQDWLRQ ,QWKHVHLQVWUXFWLRQVWKHVRXUFHFDQEHDUHJLVWHURUDQELWQXPEHU +WR))+ the destination is a register. The source and destination are operands. The various formats for specifying operands are called addressing modes7KHKDVWKH IROORZLQJ¿YHW\SHVRIDGGUHVVLQJ Press (i) Immediate addressing (ii) Memory direct addressing (iii) Register direct addressing (iv) Indirect addressing (v) Implied or implicit addressing 1.13.3.1 Immediate Addressing Immediate addressing transfers the Instruction operand given in the instruction—aUniversity byte or word—to the destination register or Opcode Operand memory location. The operand is part of the instruction. The format for immediate Fig. 1.10 )RUPDWRILPPHGLDWH DGGUHVVLQJLVJLYHQLQ)LJ addressing Example: Oxford MVI A, 9AH (a) The operand is part of the instruction. (b) The operand is stored in the register mentioned in the instruction. Example: ADI 05H D $GG+WRWKHFRQWHQWVRIWKHDFFXPXODWRU E +LVWKHRSHUDQG Immediate addressing has no memory reference to fetch data. It executes faster, but has limited data range. 1.13.3.2 Memory Direct Addressing Memory direct addressing moves a byte or word between a memory location and register. The memory location address is given in the instruction. The instruction set does not support memory-to-memory transfer. Memory direct addressing is LOOXVWUDWHGLQ)LJ © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 29 Instruction 2SFRGH0HPRU\DGGUHVV$ Memory $ Operand Fig. 1.11 )RUPDWRIPHPRU\GLUHFWDGGUHVVLQJ Example: LDA 850FH 7KLVLQVWUXFWLRQLVXVHGWRORDGWKHFRQWHQWVRIWKHPHPRU\ORFDWLRQ)+LQWKH accumulator. Example: STA 9001H This instruction is used to store the contents of the accumulatorPress in the memory address 9001H. In these instructions, the memory address of the operand is given in the instruction. Direct addressing is also used for data transfer between the processor and LQSXWRXWSXWGHYLFHV)RUH[DPSOHWKH,1LQVWUXFWLRQLVXVHGWRUHFHLYHGDWDIURP the input port and store it in the accumulator; the OUT instruction is used to send the data from the accumulator to theUniversity output port. Example: IN 00H and OUT 01H 1.13.3.3 Register Direct Addressing Register direct addressingOxford transfers a copy of a byte or word from the source register to the destination register. The operand is in the register named in the instruction. It executes very fast, has very limited register space, and requires good assembly programming. The operand is within in the processor itself; so the H[HFXWLRQLVIDVWHU5HJLVWHUGLUHFWDGGUHVVLQJLVLOOXVWUDWHGLQ)LJ Instruction Opcode Register R Registers R Operand Fig.Fi 11.12 12)ILGLGGL )RUPDWRIUHJLVWHUGLUHFWDGGUHVVLQJ © Oxford University Press. All rights reserved. 30 Microprocessors and Interfacing Example: MOV Rd, Rs MOV B, C It copies the contents of register C to register B. Example: ADD B It adds the contents of register B to the accumulator and saves it in the accumulator. 1.13.3.4 Indirect Addressing Indirect addressing transfers a byte or word between a register and a memory location. The address of a memory location is stored in a register and that register LVVSHFL¿HGLQWKHLQVWUXFWLRQ7KLVLVLOOXVWUDWHGLQ)LJ In indirect addressing, the effective address is calculated by the processor using WKHFRQWHQWVRIWKHUHJLVWHUVSHFL¿HGLQWKHLQVWUXFWLRQ7KLVW\SHRIDGGUHVVLQJ HPSOR\VVHYHUDODFFHVVHV²WZRDFFHVVHVWRUHWULHYHWKHELWDGGUHVVDQGDIXUWKHU access (or accesses) to retrieve the data which is to be loaded in the register. Example: MOV A, M Press Here, the data is in the memory location pointed to by the contents of the HL pair. The data is moved to the accumulator. Instruction Opcode Register address R Memory Registers University Memory address to operand Operand R Oxford Fig. 1.13 )RUPDWRILQGLUHFWDGGUHVVLQJ 1.13.3.5 Implied or Implicit Addressing ,QLPSOLHGDGGUHVVLQJPRGHWKHLQVWUXFWLRQLWVHOIVSHFL¿HVWKHGDWDWREHRSHUDWHG XSRQ )RU H[DPSOH &0$ FRPSOHPHQWV WKH FRQWHQWV RI WKH DFFXPXODWRU 1R VSHFL¿FGDWDRURSHUDQGLVPHQWLRQHGLQWKHLQVWUXFWLRQ 1.14 INSTRUCTION SET OF 8085 7KH PLFURSURFHVVRU LQVWUXFWLRQ VHW KDV RSHUDWLRQ FRGHV DQG LQVWUXFWLRQV ,W LV FRPSDWLEOH ZLWK WKDW RI LWV SUHGHFHVVRU WKH $ EXW KDV WZR DGGLWLRQDO LQVWUXFWLRQV²6,0 VHW LQWHUUXSW PDVN DQG 5,0 UHDG LQWHUUXSW PDVN ²UHODWHGWRVHULDO,27KHFRPSOHWHLQVWUXFWLRQVHWLVOLVWHGLQ$SSHQGL[ ZLWKDGGLWLRQDOLQIRUPDWLRQVXFKDVQXPEHURIFORFNVWDWHVUHTXLUHGIRUH[HFXWLRQ DQGWKHÀDJVDIIHFWHG © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 31 1.14.1 Format of Assembly Language Instructions and Programs $VVHPEO\ ODQJXDJH SURJUDPV DUH ZULWWHQ IRU SHUIRUPLQJ VSHFL¿F IXQFWLRQV converted into machine language code, and then stored in the memory of the microprocessor-based system. The conversion of an assembly language program into machine language code is called assembling; the application that performs this WDVNLVFDOOHGDVVHPEOHU7KLVFRQYHUVLRQRUDVVHPEOLQJFDQDOVREHGRQHPDQXDOO\ by the programmers. To facilitate the process of assembling, the assembly language SURJUDPVDUHZULWWHQLQDVSHFL¿FIRUPDWDVVKRZQLQ)LJ Memory address Machine code/Opcode Label Mnemonics with operands Comments Fig. 1.14 )RUPDWIRUZULWLQJDVVHPEO\ODQJXDJHSURJUDPV In general, the assembly language mnemonics with their operands are written ¿UVW7KHDGGUHVVZKHUHWKHLQVWUXFWLRQVDUHVWRUHGLVJLYHQDGXPP\QDPHFDOOHG label. The purpose of labels is to give the correct branch addresses in instructions. Labels are separated from mnemonics with a colon. The comments column is essential for any program as it helps the programmer understand the logic of the program at any point in time.Press Without comments, it is GLI¿FXOWWRXQGHUVWDQGDQDVVHPEO\ODQJXDJHSURJUDP&RPPHQWVDUHVHSDUDWHG from the mnemonics with a semicolon. 7KH ¿UVW WZR FROXPQV FRUUHVSRQG WR WKH SK\VLFDO PHPRU\ DGGUHVV DQG WKH DFWXDOPDFKLQHFRGH7KHVHWZRFROXPQVDUH¿OOHGLQDIWHUFRPSOHWLQJWKHDVVHPEO\ language programming. These columns must contain only binary numbers, but for HDV\XQGHUVWDQGLQJKH[DGHFLPDOQXPEHUVDUHXVHG)RUPDQXDODVVHPEOLQJWKHVH WZR FROXPQV DUH ¿OOHG LQ E\ WKHUniversity SURJUDPPHU$Q DVVHPEOHU FDQ JHQHUDWH WKHVH columns automatically. $QH[DPSOHRIWKHDVVHPEO\ODQJXDJHSURJUDPIRUPDWLVJLYHQLQ7DEOH Table 1.7 6DPSOHDVVHPEO\ODQJXDJHSURJUDP Memory Machine code/ Label Mnemonics Comments address Opcode Oxford with operands ( 67$57 09,$)+ /RDGGDWDLQWKHDFFXPXODWRU ) $GGUHVVRIWKHQH[WPHPRU\ location 7KHLQVWUXFWLRQLQ7DEOHPRYHVWKHGDWD)+WRWKHDFFXPXODWRU 1.14.2 Data Transfer Instructions Data transfer instructions are used to transfer data between two registers in the microprocessor or between a peripheral device and the microprocessor. Some instructions and their features are given in the following points. The complete list ZLWKH[SODQDWLRQVLVJLYHQLQ7DEOH L 09,LQVWUXFWLRQLVXVHGIRUVWRULQJELWGDWDLQDPLFURSURFHVVRUUHJLVWHU LL /;,LQVWUXFWLRQLVXVHGIRUVWRULQJELWGDWDLQDUHJLVWHUSDLU © Oxford University Press. All rights reserved. 32 Microprocessors and Interfacing (iii) In direct addressing mode, MOV instruction is used for data transfer between registers. In indirect addressing mode, MOV is used for data transfer between DPHPRU\ORFDWLRQDQGDUHJLVWHU,IWKHLQVWUXFWLRQKDV0LQWKHRSHUDQG¿HOG the memory location pointed to by the HL pair is considered for data transfer. Table 1.8 Data transfer instructions Mnemonics Tasks performed on Addressing Instruction Example execution mode length 09,5ELW 0RYHVWKHELWGDWD ,PPHGLDWH 7ZRE\WHV 09,%)+ to the register /;,5SELW /RDGVWKHELWGDWDLQ ,PPHGLDWH 7KUHHE\WHV /;,%$)+ the register pair 0295G5V &RSLHVWKHGDWDIURP 5HJLVWHU 2QHE\WH 029$% the source register to direct the destination register /'$ELW /RDGVWKHDFFXPXODWRU 0HPRU\ 7KUHHE\WHV /'$ )+ with the data from the direct memory location indicated by the Press ELWDGGUHVV /+/'ELW /RDGVWKH+DQG/ 0HPRU\ 7KUHHE\WHV /+/' $+ registers directly from direct the two consecutive memory locations indicated by the ELWDGGUHVV 67$ELW 6WRUHVWKHFRQWHQWVRIUniversity 0HPRU\ 7KUHHE\WHV 67$ + the accumulator in the direct memory location indicated by the ELWDGGUHVV 6+/'ELW 6WRUHVWKHFRQWHQWVRIOxford 0HPRU\ 7KUHHE\WHV 6+/' )+ the H and L registers direct in two consecutive memory locations indicated by the ELWDGGUHVV PUSH Rp Pushes the contents of Register One byte PUSH B the register pair onto direct DVWDFN POP Rp Pops the top two memory Register One byte POP H ORFDWLRQVRIWKHVWDFN GLUHFW onto a register pair 287ELW 2XWSXWVWKHGDWDLQWKH ,2 7ZRE\WHV 287+ accumulator to the port indicated by the ELWDGGUHVV (Contd) © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 33 Table 1.8 Data transfer instructions (Contd) Mnemonics Tasks performed on Addressing Instruction Example execution mode length ,1ELW ,QSXWVWKHGDWDIURPWKH ,2 7ZRE\WHV ,1+ SRUWLQGLFDWHGE\WKH ELWDGGUHVVWRWKH DFFXPXODWRU 0295G0 &RSLHVWKHFRQWHQWVRI ,QGLUHFW 2QHE\WH 029%0 WKHPHPRU\ORFDWLRQ SRLQWHGWRE\WKH+/ UHJLVWHUSDLUWR WKHUHJLVWHU 02905V &RSLHVWKHFRQWHQWVRIWKH,QGLUHFW 2QHE\WH 0290& UHJLVWHUWRWKHPHPRU\ ORFDWLRQSRLQWHGWRE\ WKH+/UHJLVWHUSDLU /'$;5S /RDGVDFFXPXODWRUZLWK ,QGLUHFW 2QHE\WH /'$;% WKHFRQWHQWVRIWKH PHPRU\ORFDWLRQSRLQWHG Press WRE\WKHUHJLVWHUSDLU 67$;5S 6WRUHVWKHFRQWHQWVRIWKH,QGLUHFW 2QHE\WH 67$;' DFFXPXODWRULQWKH PHPRU\ORFDWLRQSRLQWHG WRE\WKHUHJLVWHUSDLU ;&+* ([FKDQJHVWKHFRQWHQWV ,PSOLFLW 2QHE\WH ;&+* RIWKH+/UHJLVWHUSDLU ZLWKWKDWRIWKH'DQG(University UHJLVWHUSDLU 63+/ &RSLHVWKHFRQWHQWVRI ,PSOLFLW 2QHE\WH 63+/ WKH+DQG/UHJLVWHUVWR WKHVWDFNSRLQWHU ;7+/ ([FKDQJHVWKHFRQWHQWVOxford ,PSOLFLW 2QHE\WH ;7+/ RIWKH+/UHJLVWHUSDLU ZLWKWKHWRSRIVWDFN LY /'$DQG67$XVHPHPRU\GLUHFWDGGUHVVLQJPRGHDQGDELWPHPRU\ DGGUHVVDVRSHUDQG Y /'$; DQG 67$; XVH LQGLUHFW DGGUHVVLQJ PRGH IRU GDWD WUDQVIHU 7KH RSHUDQG JLYHQ LQ WKH LQVWUXFWLRQ LV RQH RI WKH UHJLVWHU SDLUV %& RU '( 5HJLVWHU SDLU +/ LV QRW XVHG ZLWK /'$; GXH WR WKH DYDLODELOLW\ RI WKH DOWHUQDWLYHLQVWUXFWLRQ029$0 YL /+/'DQG6+/'DUHWKHLQVWUXFWLRQVXVHGWRWUDQVIHUELWGDWDEHWZHHQ WKH+/UHJLVWHUSDLUDQGWZRFRQVHFXWLYHPHPRU\ORFDWLRQV)RUH[DPSOH H[HFXWLQJ6+/' +LQVWUXFWLRQZLOOVWRUHWKHFRQWHQWVRI/UHJLVWHULQ +DQGWKHFRQWHQWVRI+UHJLVWHULQ + YLL 386+ DQG 323 LQVWUXFWLRQV DUH XVHG IRU GDWD WUDQVIHU EHWZHHQ D UHJLVWHU © Oxford University Press. All rights reserved. 34 Microprocessors and Interfacing SDLUDQGDVWDFN7KHVWDFNLVDVHWRIPHPRU\ORFDWLRQVFRQ¿JXUHGDVDODVW LQ ¿UVWRXW /,)2 RU ¿UVWLQ ODVWRXW ),/2 DUUD\ 7KH WRS RI WKH VWDFN ORFDWLRQVLVSRLQWHGWRE\DVSHFLDOUHJLVWHUWKHVWDFNSRLQWHUZKLFKLVZLWKLQ WKH PLFURSURFHVVRU 386+ LQVWUXFWLRQ ZLOO VWRUH WKH UHJLVWHU SDLU JLYHQ LQ WKHLQVWUXFWLRQWRWKHWRSWZRPHPRU\ORFDWLRQVRIWKHVWDFN6LPLODUO\323 LQVWUXFWLRQZLOOFRS\WKHODVWWZRE\WHVVWRUHGLQWKHVWDFNWRWKHUHJLVWHUSDLU PHQWLRQHGLQWKHLQVWUXFWLRQ&DUHPXVWEHWDNHQLQXVLQJWKHVHLQVWUXFWLRQVDV WKHVWDFNLVFRQ¿JXUHGDVD/,)2DUUD\$QRWKHULQVWUXFWLRQWRVWRUHGDWDLQWKH VWDFNLV;7+/ZKLFKH[FKDQJHVWKHWRSWZRPHPRU\ORFDWLRQVRIWKHVWDFN ZLWKWKHFRQWHQWVRIWKH+/UHJLVWHUSDLU YLLL 6WDFN SRLQWHU FDQ EH LQLWLDOL]HG XVLQJ /;, RU 63+/ LQVWUXFWLRQV 63+/ LQVWUXFWLRQZLOOFRS\WKHFRQWHQWVRIWKH+/UHJLVWHUSDLUWRWKHVWDFNSRLQWHU L[ ,1DQG287LQVWUXFWLRQVXVHELWSRUWDGGUHVVHVDVRSHUDQG,1LQVWUXFWLRQ LVXVHGWRJHWGDWDIURPWKHLQSXWSRUWDQGWKHGDWDREWDLQHGLVVWRUHGLQWKH DFFXPXODWRU287LQVWUXFWLRQLVXVHGWRLVVXHGDWDIURPWKHDFFXPXODWRUWR DQRXWSXWSRUW [ ;&+* LQVWUXFWLRQ LV XVHG WR H[FKDQJH WKH FRQWHQWV RI WKH +/ DQG '( UHJLVWHUSDLUV Press 1.14.3 Arithmetic Instructions 7KHDULWKPHWLFLQVWUXFWLRQVVXSSRUWHGE\WKHDUHDGGLWLRQVXEWUDFWLRQDQG WKHLUYDULDQWV7KHDULWKPHWLFLQVWUXFWLRQVDUHOLVWHGLQ7DEOH Table 1.9 Arithmetic instructions Mnemonics Tasks performed onUniversity Addressing Instruction Example execution mode length $',ELW $GGVWKHELWGDWDWR ,PPHGLDWH 7ZRE\WHV $',+ WKHFRQWHQWVRIWKH DFFXPXODWRU $&,ELW $GGVWKHELWGDWDDQGOxford ,PPHGLDWH 7ZRE\WHV $&,)+ WKHFDUU\ÀDJWRWKH FRQWHQWVRIWKH DFFXPXODWRU 68,ELW 6XEWUDFWVWKHELWGDWD ,PPHGLDWH 7ZRE\WHV 68,$+ IURPWKHFRQWHQWVRIWKH DFFXPXODWRU 6%,ELW 6XEWUDFWVWKHELWGDWD ,PPHGLDWH 7ZRE\WHV 6%,&+ DQGWKHERUURZIURPWKH FRQWHQWVRIWKH DFFXPXODWRU $''5 $GGVWKHFRQWHQWVRIWKH 5HJLVWHU 2QHE\WH $''& UHJLVWHUWRWKHFRQWHQWV GLUHFW RIWKHDFFXPXODWRU (Contd) © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 35 Table 1.9 $ULWKPHWLFLQVWUXFWLRQV (Contd) Mnemonics Tasks performed on Addressing Instruction Example execution mode length $'&5 $GGVWKHFRQWHQWVRIWKH 5HJLVWHU 2QHE\WH $'&( register and the carry to direct the contents of the accumulator SUB R Subtracts the contents of Register One byte SUB B the register from that of direct the accumulator SBB R Subtracts the contents Register One byte SBB C of the register and the direct borrow from that of the accumulator '$'5S $GGVWKHFRQWHQWVRIWKH Register 2QHE\WH '$'% register pair to that of the direct H and L registers ,155 ,QFUHPHQWVWKHUHJLVWHU Register 2QHE\WH ,15% by 1 direct Press ,1;5S ,QFUHPHQWVWKHUHJLVWHU Register 2QHE\WH ,1;% pair by 1 direct DCR R Decrements the register Register One byte DCR E by 1 direct '&;5S 'HFUHPHQWVWKHUHJLVWHU Register 2QHE\WH '&;' pair by 1 direct $''0 $GGVWKHFRQWHQWVRIWKHUniversity ,QGLUHFW 2QHE\WH $''0 memory location pointed to by the HL register pair to that of the accumulator $'&0 $GGVWKHFRQWHQWVRIWKH ,QGLUHFW 2QHE\WH $'&0 memoryOxford location pointed to by the HL register pair and the carry to that of the accumulator SUB M Subtracts the contents of Indirect One byte SUB M the memory location pointed to by the HL register pair from that of the accumulator SBB M Subtracts the borrow and Indirect One byte SBB M the contents of the memory location pointed to by the HL pair from that of the accumulator (Contd) © Oxford University Press. All rights reserved. 36 Microprocessors and Interfacing Table 1.9 $ULWKPHWLFLQVWUXFWLRQV (Contd) Mnemonics Tasks performed on Addressing Instruction Example execution mode length ,150 ,QFUHPHQWVWKHPHPRU\ ,QGLUHFW 2QHE\WH ,150 location pointed to by the HL register pair by 1 DCR M Decrements the memory Indirect One byte DCR M location pointed to by the HL register pair by 1 '$$ &RQYHUWVWKHFRQWHQWVRI ,PSOLFLW 2QHE\WH '$$ the accumulator from binary to BCD (Decimal- $GMXVW$FFXPXODWRU 7KHIROORZLQJSRLQWVOLVWVRPHNH\IHDWXUHVRIDULWKPHWLFRSHUDWLRQV L )RUDULWKPHWLFRSHUDWLRQVRQHRIWKHGDWDPXVWEHVWRUHGLQWKHDFFXPXODWRU and the other given or addressed in the instruction. LL $GGZLWKFDUU\LQVWUXFWLRQVDUHXVHGIRUPXOWLE\WHDQGKLJKHURUGHUE\WH addition. Press (iii) Similarly, subtract-with-borrow instructions are used in multi-byte and higher-order byte subtraction. (iv) Increment and decrement instructions can be operated not only on the accumulator, but also on other registers including memory locations. Y 7KHFRQWHQWVRIDUHJLVWHUSDLUFDQEHLQFUHPHQWHGRUGHFUHPHQWHGXVLQJ,1; DQG'&;LQVWUXFWLRQV YL '$$LVWKHLQVWUXFWLRQWKDWVXSSRUWV%&'DGGLWLRQ7University KHDGGLWLRQRI %&'GDWDLVGRQHOLNHELQDU\DGGLWLRQXVLQJWKH$''LQVWUXFWLRQ'$$LV used to convert the result of the binary addition of BCD numbers into a BCD number. This instruction cannot be used to directly convert binary numbers into BCD numbers.Oxford 1.14.4 Logical Instructions 7KH PRVW LPSRUWDQW ORJLFDO LQVWUXFWLRQV VXSSRUWHG E\ WKH DUH$1' 25 (;25DQG1277KHFRPSOHWHOLVWLVJLYHQLQ7DEOH Table 1.10 Logical instructions Mnemonics Tasks performed on execution Addressing Instruction Example mode length $1,ELW 7KHELWGDWDLVORJLFDOO\$1'HG ,PPHGLDWH 7ZRE\WHV $1,)+ with the contents of the accumulator. ;5,ELW 7KHELWGDWDLVORJLFDOO\(;25HG ,PPHGLDWH 7ZRE\WHV ;5,+ with the contents of the accumulator. 25,ELW 7KHELWGDWDLVORJLFDOO\25HG ,PPHGLDWH 7ZRE\WHV 25,+ with the contents of the accumulator. (Contd) © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 37 Table 1.10 Logical instructions (Contd) Mnemonics Tasks performed on execution Addressing Instruction Example mode length $1$5 7KHFRQWHQWVRIWKHUHJLVWHUDUH 5HJLVWHU 2QHE\WH $1$& ORJLFDOO\$1'HGZLWKWKHFRQWHQWV GLUHFW of the accumulator. ;5$5 7KHFRQWHQWVRIWKHUHJLVWHUDUH 5HJLVWHU 2QHE\WH ;5$' ORJLFDOO\(;25HGZLWKWKHFRQWHQWV GLUHFW of the accumulator. 25$5 7KHFRQWHQWVRIWKHUHJLVWHUDUH 5HJLVWHU 2QHE\WH 25$( logically ORed with the contents direct of the accumulator. $1$0 7KHFRQWHQWVRIWKHPHPRU\ ,QGLUHFW 2QHE\WH $1$0 location pointed to by the HL UHJLVWHUSDLULVORJLFDOO\$1'HG with the contents of the accumulator. ;5$0 7KHFRQWHQWVRIWKHPHPRU\ ,QGLUHFW 2QHE\WH ;5$0 location pointed to by the HL Press UHJLVWHUSDLULVORJLFDOO\(;25HG with the contents of the accumulator. 25$0 7KHFRQWHQWVRIWKHPHPRU\ ,QGLUHFW 2QHE\WH 25$0 location pointed to by the HL register pair is logically ORed with the contents of the accumulator. RLC Rotates the bits of the accumulator Implicit One byte RLC left by one position University RRC Rotates the bits of the accumulator Implicit One byte RRC right by one position 5$/ 5RWDWHVWKHELWVRIWKHDFFXPXODWRU ,PSOLFLW 2QHE\WH 5$/ left by Oxfordone position, through the carry 5$5 5RWDWHVWKHELWVRIWKHDFFXPXODWRU ,PSOLFLW 2QHE\WH 5$5 right by one position, through the carry &3,ELW &RPSDUHVWKHELWGDWDZLWKWKH ,PPHGLDWH 7ZRE\WHV &3,))+ contents of the accumulator CMP R Compares the contents of the register Register One byte CMP B with that of the accumulator direct CMP M Compares the contents of the memory Indirect One byte CMP M location pointed to by the HL register pair with that of the accumulator &0$ &RPSOHPHQWVWKHFRQWHQWVRIWKH ,PSOLFLW 2QHE\WH &0$ accumulator CMC Complements the carry Implicit One byte CMC STC Sets the carry Implicit One byte STC © Oxford University Press. All rights reserved. 38 Microprocessors and Interfacing )RUORJLFDORSHUDWLRQVRQHRIWKHGDWDPXVWEHVWRUHGLQWKHDFFXPXODWRUDQGWKH other given or addressed in the instruction. Logical operations can be performed with immediate data, data stored in a register, or indirectly addressed memory location content. Besides the instructions already mentioned, two types of rotate instructions DUH DYDLODEOH LQ WKH 2QH VHW²5/& DQG 55&²URWDWHV WKH DFFXPXODWRU contents within itself. The RLC instruction shifts the accumulator content left by RQHELW,QWKHSURFHVVWKHPRVWVLJQL¿FDQWELWRIWKHDFFXPXODWRUEHFRPHVWKH OHDVWVLJQL¿FDQWELW7KH55&LQVWUXFWLRQVKLIWVWKHDFFXPXODWRUFRQWHQWULJKWE\ one bit. 7KHRWKHUVHWRIURWDWHLQVWUXFWLRQV²5$/DQG5$5²URWDWHVWKHDFFXPXODWRU FRQWHQW DORQJ ZLWK WKH FDUU\ ÀDJ 7KH 5$/ LQVWUXFWLRQ VKLIWV WKH DFFXPXODWRU FRQWHQWOHIWE\RQHELWDQGLQWKHSURFHVVWKHPRVWVLJQL¿FDQWELWZLOOEHVKLIWHGWR WKHFDUU\ÀDJDQGWKHFDUU\ÀDJFRQWHQWZLOOEHVKLIWHGWRWKHOHDVWVLJQL¿FDQWELWRI the accumulator. 7KHLQVWUXFWLRQVHWRIWKHVXSSRUWVDFRPSDUHLQVWUXFWLRQIRUFRPSDULQJ the magnitude of two binary numbers. The compare instructions are used to FRPSDUHWKHDFFXPXODWRUFRQWHQWZLWKWKHRSHUDQGVSHFL¿HGLQWKHLQVWUXFWLRQPress CPI instruction uses immediate addressing and CMP uses registers or indirectly addressed memory location for comparing with the accumulator. The result of the FRPSDUHLQVWUXFWLRQLVLQGLFDWHGLQWKHÀDJUHJLVWHUDVIROORZV ,I> $ íRSHUDQG@ LH $ RSHUDQGWKH]HURÀDJLVVHW ,I> $ íRSHUDQG@ LH $ RSHUDQGWKHFDUU\ÀDJLVVHW ,I> $ íRSHUDQG@!LH $ !RSHUDQGWKH]HURDQGFDUU\ÀDJVDUHUHVHW University 1.14.5 Branching Instructions Branching instructions are used to transfer the program execution to a different address. Branching instructions are of two types—jump instructions and subroutine instructions. The jump instructions merely transfer the execution from one location in theOxford program to another, whereas the subroutine instructions in the main program transfer execution to a new location and also return to the main SURJUDP5HWXUQLQVWUXFWLRQVDUHXVHGIRUWKLVSXUSRVH7KHEUDQFKLQJFDQWDNH SODFH XQFRQGLWLRQDOO\ RU FRQGLWLRQDOO\ EDVHG RQ WKH ÀDJ FRQGLWLRQV VKRZQ LQ Table 1.11. PCHL instruction is a special instruction used to branch to the address stored in the HL register pair. RST nLVWKHUHVWDUWLQVWUXFWLRQVXSSRUWHGE\WKH8SRQH[HFXWLRQRIWKH RST n instruction, the program execution will be transferred to the address given by n î)RUH[DPSOH567LQVWUXFWLRQZLOOWUDQVIHUWKHH[HFXWLRQWRWKHDGGUHVV +ZKLFKLVWKHKH[DGHFLPDOHTXLYDOHQWRI LQGHFLPDOIRUP ,QPDFKLQHFRGHRURSFRGHWKHELWRUKH[GLJLWDGGUHVVHVLQWKHEUDQFKLQJ instructions are given such that the lower-order byte of the address follows the KLJKHURUGHUE\WH)RUH[DPSOH-03+LVFRGHGDV&7KHRSFRGHIRU -03&LVVWRUHG¿UVWIROORZHGE\DQGWKHQE\ © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 39 Table 1.11 Branching instructions Mnemonics Tasks performed on Instruction Example execution length -03ELW -XPSXQFRQGLWLRQDOO\ 7KUHHE\WHV -03 -&ELW -XPSLIFDUU\LVVHW 7KUHHE\WHV -& -1&ELW -XPSRQQRFDUU\ 7KUHHE\WHV -1& -3ELW -XPSRQSRVLWLYH 7KUHHE\WHV -3 -0ELW -XPSRQPLQXV 7KUHHE\WHV -0 -=ELW -XPSRQ]HUR 7KUHHE\WHV -= -1=ELW -XPSRQQR]HUR 7KUHHE\WHV -1= -3(ELW -XPSRQSDULW\HYHQ 7KUHHE\WHV -3( -32ELW -XPSRQSDULW\RGG 7KUHHE\WHV -32 &$//ELW &DOOXQFRQGLWLRQDOO\ 7KUHHE\WHV &$// &&ELW &DOORQFDUU\ 7KUHHE\WHV && &1&ELW &DOORQQRFDUU\ 7KUHHE\WHV &1& &3ELW &DOORQSRVLWLYH 7KUHHE\WHV &3 &0ELW &DOORQPLQXV 7KUHHE\WHV &0 &=ELW &DOORQ]HUR 7KUHHE\WHV &= &1=ELW &DOORQQR]HUR 7KUHHE\WHVPress &1= &3(ELW &DOORQSDULW\HYHQ 7KUHHE\WHV &3( &32ELW &DOORQSDULW\RGG 7KUHHE\WHV &32 RET Return unconditionally One byte RET RC Return on carry One byte RC 51& 5HWXUQRQQRFDUU\ 2QHE\WH 51& RP Return on positive One byte RP RM Return on minus One byte RM RZ Return onUniversity zero One byte RZ 51= 5HWXUQRQQR]HUR 2QHE\WH 51= RPE Return on parity even One byte RPE RPO Return on parity odd One byte RPO PCHL Copy HL contents to One byte PCHL Oxfordthe program counter 567 5HVWDUW 2QHE\WH 567 1.14.6 Machine Control Instructions Machine control instructions are used to control the microprocessor execution DQGIXQFWLRQLQJDQGDUHOLVWHGLQ7DEOH7KH\DUHH[SODLQHGLQGHWDLOLQWKH IROORZLQJSRLQWV L 123PHDQVQRRSHUDWLRQ:KHQWKLVLQVWUXFWLRQLVH[HFXWHGQRWKLQJLVGRQH no changes occur in the contents of the registers. The program counter alone is incremented to fetch and execute the next instruction. (ii) HLT instruction is used to halt the execution of the program. The operation of the microprocessor is suspended when HLT instruction is executed. The only way to exit the halt state is to apply the hardware reset signal. © Oxford University Press. All rights reserved. 40 Microprocessors and Interfacing (iii) Interrupts are disabled and enabled using DI and EI signals, respectively. Once the DI instruction has been executed, the processor ignores any interrupt request received. To enable interrupts again, the EI instruction has to be executed. (iv) The SIM instruction is used to send serial data on the serial output data (SOD) line of the microprocessor and the RIM instruction is used to receive serial data on the serial input data (SID) line of the processor. The SIM and RIM instructions are also associated with the setting and reading of interrupt PDVNVIRU567KDUGZDUHLQWHUUXSWV Table 1.12 Machine control instructions Mnemonics Tasks performed on execution Addressing Instruction mode length 123 1RRSHUDWLRQ ,PSOLFLW 2QHE\WH HLT Halts the microprocessor execution Implicit One byte DI Disables interrupts Implicit One byte EI Enables interrupts Implicit One byte 5,0 5HDGVLQWHUUXSWPDVN ,PSOLFLW 2QHE\WH 6,0 6HWVLQWHUUXSWPDVN ,PSOLFLWPress 2QHE\WH 1.15 SAMPLE PROGRAMS 1. Write an assembly language program to add two numbers. The program given in Table 1.13 uses immediate addressing for the two data to be DGGHG7KHGDWDWREHDGGHGDUHVWRUHGLQPHPRU\ORFDWLRQV+DQG+ 7KHVXPLVVWRUHGLQWKHPHPRU\ORFDWLRQ+7KLVSURJUDPDVVXPHVWKDWQRUniversity carry is generated from the addition. Table 1.13 3URJUDPIRUDGGLQJWZRELWQXPEHUV Memory Machine code/ Labels Mnemonics with Comments address Opcode Oxford operands ( 67$57 09,$+ /RDGWKH¿UVWQXPEHULQ WKHDFFXPXODWRU & $',+ $GGWKHVHFRQGQXPEHUZLWK WKHFRQWHQWVRIWKHDFFXPXODWRU 67$+ 6WRUHWKHVXPLQWKHPHPRU\ ORFDWLRQ+ +/7 7HUPLQDWHSURJUDPH[HFXWLRQ :ULWHDQDVVHPEO\ODQJXDJHSURJUDPWRDGGWZRQXPEHUVRIELWVHDFK This program also uses immediate addressing for loading the data in the processor UHJLVWHUV7KHVXPLVVWRUHGLQWKHPHPRU\ORFDWLRQV+DQG+DVVKRZQ LQ7DEOH © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 41 Table 1.14 3URJUDPIRUDGGLQJWZRELWQXPEHUV Memory Machine Labels Mnemonics with Comments address code/ operands Opcode 67$57 /;,+)+ /RDGWKH¿UVWELWQXPEHULQ ) WKH+/UHJLVWHUSDLU /;,%$+ /RDGWKHQH[WQXPEHULQWKH%& $ UHJLVWHUSDLU '$'% $GGWKHWZRQXPEHUVXVLQJ double addition instruction. 6+/'+ 6WRUHWKHUHVXOWLQWKH+/SDLULQ WKHPHPRU\ORFDWLRQV+DQG + $ +/7 7HUPLQDWHSURJUDPH[HFXWLRQ 3. Write an assembly language program to add the two numbers stored in the PHPRU\ORFDWLRQV+DQG+DQGVWRUHWKHUHVXOWLQ+Press This program uses indirect addressing instructions to load the numbers to be added in the processor registers. The carry, if generated, is ignored. The program LVVKRZQLQ7DEOH Table 1.15 3URJUDPIRUDGGLQJWZRQXPEHUVIURPPHPRU\ Memory Machine Labels MnemonicsUniversity with Comments address code/ operands Opcode 67$57 /;,++ ,QLWLDOL]H+/UHJLVWHUSDLUWRSRLQW WRWKHPHPRU\ORFDWLRQRIWKH Oxford ¿UVWQXPEHU ( 029$0 /RDGWKH¿UVWQXPEHULQWKH accumulator. ,1;+ ,QFUHPHQWWKH+/SDLUWRSRLQWWR the memory location of the next number. $''0 $GGWKHWZRQXPEHUV ,1;+ ,QFUHPHQWWKH+/SDLUWRSRLQWWR the next memory location. 0290$ 6WRUHWKHFRQWHQWVRIWKH accumulator in the memory location pointed to by the HL register pair. +/7 7HUPLQDWHSURJUDPH[HFXWLRQ © Oxford University Press. All rights reserved. 42 Microprocessors and Interfacing 1.16 INSTRUCTION EXECUTION 7KHPLFURSURFHVVRULVGHVLJQHGWRIHWFKWKHLQVWUXFWLRQSRLQWHGWRE\WKH program counter, and then decode and execute the instruction within the processor. ,IQHFHVVDU\IXUWKHURSHUDQGIHWFKWDNHVSODFHEHIRUHFRPSOHWLQJWKHH[HFXWLRQ (DFKLQVWUXFWLRQDVZHKDYHDOUHDG\VHHQKDVWZRSDUWV²RSHUDWLRQFRGH NQRZQ DVRSFRGH DQGRSHUDQG7KHRSFRGHLVDFRPPDQGVXFKDV$''DQGWKHRSHUDQG is an object to be operated on, such as a byte or the contents of a register. Instruction cycleLVWKHWLPHWDNHQE\WKHSURFHVVRUWRFRPSOHWHWKHH[HFXWLRQ RIDQLQVWUXFWLRQ$QLQVWUXFWLRQF\FOHFRQVLVWVRIRQHWRVL[PDFKLQHF\FOHV Machine cycle is the time required to complete one operation—accessing either WKHPHPRU\RUDQ,2GHYLFH$PDFKLQHF\FOHFRQVLVWVRIWKUHHWRVL[7VWDWHV T-state LVWKHWLPHFRUUHVSRQGLQJWRRQHFORFNSHULRG7KH7VWDWHLVWKHEDVLF XQLWXVHGWRFDOFXODWHWKHWLPHWDNHQIRUH[HFXWLRQRILQVWUXFWLRQVDQGSURJUDPVLQ a processor. 7RH[HFXWHDSURJUDPWKHSHUIRUPVYDULRXVRSHUDWLRQVVXFKDVRSFRGHIHWFK operand fetch, and memory read/write or I/O read/write. The microprocessor’s H[WHUQDOFRPPXQLFDWLRQIXQFWLRQFDQEHGLYLGHGLQWRWKUHHFDWHJRULHV (i) Memory read/write (ii) I/O read/writePress LLL ,QWHUUXSWUHTXHVWDFNQRZOHGJH POINTS TO REMEMBER x The microprocessor is an electronic circuit that functions as the central processing unit (CPU) of a computer, providing computational control. x The microprocessor is the controllingUniversity element in a computer system. The microprocessor performs data transfers, does simple arithmetic and logical RSHUDWLRQVDQGPDNHVVLPSOHGHFLVLRQV x The basic operation of the microprocessor is to fetch instructions stored in the memory and execute them one by one in sequence. x Microprocessors are used in almost all advanced electronic systems. x MicrocontrollersOxford are advanced forms of microprocessors, with memory and ports present within the chip. x $ PLFURFRPSXWHU V\VWHP LV PDGH E\ LQWHUIDFLQJ PHPRU\ DQG ,2 GHYLFHV WR D microprocessor. x 0LFURSURFHVVRUHYROXWLRQLVFODVVL¿HGLQWR¿YHJHQHUDWLRQV7KHSURFHVVRUVWKDWDUH FXUUHQWO\LQXVHEHORQJWRWKH¿IWKJHQHUDWLRQ x The microprocessor is a semiconductor device consisting of electronic logic circuits manufactured using either large-scale integration (LSI) or very large-scale LQWHJUDWLRQ 9/6, WHFKQLTXH,WZRUNVDWD¿[HGFORFNIUHTXHQF\ x $EXV is a collection of wires connecting two or more chips. x $ W\SLFDO PLFURSURFHVVRU FRPPXQLFDWHV ZLWK PHPRU\ DQG RWKHU LQSXWRXWSXW devices using three buses—address bus, data bus, and control bus. x 6DOLHQWIHDWXUHVRIWKHPLFURSURFHVVRUPDQXIDFWXUHGE\,QWHO ,WLVDQELWPLFURSURFHVVRU ,WKDVDELWDGGUHVVEXV $±$ DQGKHQFHFDQDGGUHVVXSWR E\WHV .% © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 43 7KHKDVDPXOWLSOH[HGEXV $'±$' ZKLFKLVXVHGDVWKHORZHURUGHU DGGUHVVEXVDQGWKHGDWDEXV,WFDQEHGHPXOWLSOH[HGXVLQJDODWFKDQGWKH$/( signal. The data bus is a group of eight lines (D0–D7). It supports external interrupt request. ,WKDVDELWSURJUDPFRXQWHU 3& DQGDELWVWDFNSRLQWHU 63 ,WKDVVL[ELWJHQHUDOSXUSRVHUHJLVWHUVZKLFKFDQEHDUUDQJHGLQSDLUVDV%& DE, and HL. ,WUHTXLUHVD9SRZHUVXSSO\DQGRSHUDWHVDW0+]FORFNIUHTXHQF\ ,WFRQWDLQVSLQVDQGLVDYDLODEOHDVDGXDOLQOLQHSDFNDJH ',3 ,WKDV¿YHÀDJV²VLJQ]HURDX[LOLDU\FDUU\SDULW\DQGFDUU\ x The microprocessor operations related to data manipulation can be summarized in WKHIROORZLQJIRXUIXQFWLRQV (i) Transferring data (ii) Performing arithmetic operations (iii) Performing logical operations (iv) Testing for a given condition and altering the program sequence x 7KHLQVWUXFWLRQVDUHFODVVL¿HGLQWRWKUHHJURXSVDFFRUGLQJWRZRUGVL]H RQHWZR and three-byte instructions. x $Q LQVWUXFWLRQ KDV WZR SDUWV²RSFRGH RSHUDWLRQ WR EHPress SHUIRUPHG DQG RSHUDQG GDWD WR EH RSHUDWHG RQ 7KH RSHUDQG FDQ EH GDWD ELW RU ELW DGGUHVVHV registers, or implicit in the opcode. The method of specifying an operand (directly, indirectly, etc.) is called addressing mode. x The instructions are executed in steps of machine cycles and each machine cycle requires many T-states. UniversityKEY TERMS Accumulator ,WLVDQELWUHJLVWHU LWLVDSDUWRIWKH$/8DQGLVWKHPRVWLPSRUWDQW UHJLVWHU,WLVXVHGWRVWRUHELWGDWDDQGWRSHUIRUPDULWKPHWLFDQGORJLFDORSHUDWLRQV The output of an operation is also stored in the accumulator. The accumulator is LGHQWL¿HGDVUHJLVWHU$ Address bus ThisOxford bus carries the binary number (i.e., the address) used to access a memory location. Binary data can then be written into or read from the addressed PHPRU\ORFDWLRQ7KHDGGUHVVEXVFRQVLVWVRIZLUHVDQGFDQWKHUHIRUHKDQGOH bits. Addressing mode It is the method of specifying the data to be operated on by the instruction. Bus It is a group of conducting lines that carry data, address, and control signals Clock speed This determines how many instructions per second the processor can H[HFXWH,WLVVSHFL¿HGLQPHJDKHUW] 0+] Control bus This bus has various lines for coordinating and controlling PLFURSURFHVVRURSHUDWLRQV)RUH[DPSOHRD and WR lines. Data bus This bus carries data in binary form between the microprocessor and H[WHUQDOXQLWVVXFKDVPHPRU\7\SLFDOVL]HLVHLJKWRUELWV DMA controller ,WLVXVHGWRWDNHFRQWURORIWKHV\VWHPEXVE\SODFLQJDKLJKVLJQDO on the Hold pin. Flag ,WLVDÀLSÀRSXVHGWRVWRUHLQIRUPDWLRQDERXWWKHVWDWXVRIWKHSURFHVVRUDQG the status of the instruction executed most recently. © Oxford University Press. All rights reserved. 44 Microprocessors and Interfacing Hold and HLDA 7KHVH VLJQDOV DUH XVHG IRU GLUHFW PHPRU\ DFFHVV '0$ W\SH RIGDWDWUDQVIHU7KH+ROGUHTXHVWPDNHVWKHGULYHDOOLWVWULVWDWHGSLQVWRKLJK LPSHGDQFHVWDWH7KH+/'$VLJQDOJRHVKLJKWRDFNQRZOHGJHWKHUHFHLSWRIWKH+ROG signal. Immediate addressing It transfers the operand given in the instruction—a byte or word—to the destination register or memory location. Implied addressing ,QWKLVDGGUHVVLQJPRGHWKHLQVWUXFWLRQLWVHOIVSHFL¿HVWKHGDWD to be operated on. IN This instruction is used to move data from an I/O port to the accumulator. Indirect addressing It transfers a byte or word between a register and a memory location addressed by another register. Instruction cycle It is the time required to execute an instruction. IO/M signal 7KLVVLJQDOLVXVHGWRGLIIHUHQWLDWHPHPRU\DFFHVVDQG,2DFFHVV)RU input/output instructions it is high; for memory reference instructions it is low. JMP and CALL -03LQVWUXFWLRQSHUPDQHQWO\FKDQJHVWKHSURJUDPFRXQWHU&$// LQVWUXFWLRQ OHDYHV LQIRUPDWLRQ RQ WKH VWDFN VR WKDW WKH RULJLQDO SURJUDP H[HFXWLRQ sequence can be resumed. Machine cycle It is the time required to access the memory or input/output devices. Memory direct addressing It moves a byte or word between a memory location and a register. Press Opcode ,WLVWKHSDUWRIWKHLQVWUXFWLRQWKDWVSHFL¿HVWKHRSHUDWLRQWREHSHUIRUPHG Operand It is the data on which the operation is performed. 287 This instruction is used to move data from the accumulator to an I/O port. Ready It is an input signal to the processor. It is used by the memory or I/O devices to get extra time for data transfer or to introduce wait states in the bus cycles. Register direct addressing It transfers a copy of a byte or word from a source register to a destination register. Timing diagram ,WLVDJUDSKLFDOUHSUHVHQWDWLRQRIWKHWLPHWDNHQE\HDFKLQVWUXFWLRQUniversity for execution. The execution time is represented in T-states. Trap ,WLVDQRQPDVNDEOHLQWHUUXSWRIWKHDQGLVQRWGLVDEOHGE\SURFHVVRUUHVHW or after reorganization of interrupt. T-state ,WLVWKHEDVLFXQLWXVHGWRFDOFXODWHWKHWLPHWDNHQIRUH[HFXWLRQRILQVWUXFWLRQV DQGSURJUDPVLQDSURFHVVRU,WLVWKHWLPHFRUUHVSRQGLQJWRRQOxford HFORFNSHULRG REVIEW QUESTIONS 1. What is the main function of a computer? 1DPHDQ\WKUHHLQSXWGHYLFHVRIDFRPSXWHU 1DPHDQ\WZRRXWSXWGHYLFHVRIDFRPSXWHU 1DPHDQ\WKUHHVWRUDJHGHYLFHVRIDFRPSXWHU 1DPHDQ\WKUHHSODFHVZKHUHFRPSXWHUVFDQEHXVHG 'UDZDEORFNGLDJUDPRIDFRPSXWHUDQGODEHOLWVFRPSRQHQWV :KRGHYHORSHGWKHZRUOG¶V¿UVWPLFURSURFHVVRU" :KDWLVWKHGDWDEXVZLGWKRIWKHPLFURSURFHVVRU" :KHQGLG,QWHOLQWURGXFHWKH3HQWLXPPLFURSURFHVVRU" :KDWLVWKHDPRXQWRIPHPRU\WKDWWKH3HQWLXPSURFHVVRUFDQDGGUHVV" 11. What are the basic units of a microprocessor? :KDWLVWKHIXQFWLRQRIPLFURSURFHVVRULQDV\VWHP" © Oxford University Press. All rights reserved. Microprocessors—Evolution and Introduction to 8085 45 +RZ PDQ\ PHPRU\ ORFDWLRQV FDQ EH DGGUHVVHG E\ D PLFURSURFHVVRU ZLWK address lines? 1DPHDQ\WZRW\SHVRIPHPRULHVWKDWDUHXVHGLQDFRPSXWHU 'H¿QHFRPSXWHUKDUGZDUH 'H¿QHFRPSXWHUVRIWZDUH 17. What is the role of CPU in a computer? :KDWDUHLQSXWDQGRXWSXWGHYLFHV" 'HVFULEHDQGGUDZWKHGLDJUDPRI9RQ±1HXPDQQPRGHO 'H¿QHWKHIROORZLQJDEEUHYLDWLRQV &385$0DQG520 1DPHDQ\WKUHHIHDWXUHVRIWKH :KDWDUHWKHRSHUDWLRQVSHUIRUPHGE\WKH$/8RIWKH" :KDWDUHWKHYDULRXVUHJLVWHUVLQWKH" :KDWLVDÀDJ"/LVWLWVW\SHV:KDWLVWKHVWUXFWXUHRIWKHÀDJUHJLVWHU"([SODLQ HDFKÀDJZLWKDQH[DPSOH /LVWWKHELWUHJLVWHUVRIWKHPLFURSURFHVVRU :KDWLVDEXV" :K\LVWKHGDWDEXVELGLUHFWLRQDO" +RZDUHWKHVLJQDOVRIWKHFODVVL¿HG" +RZDUHFORFNVLJQDOVJHQHUDWHGLQWKH":KDWLVWKHIUHTXHQF\RIWKHLQWHUQDO FORFN" Press +RZGRHVWKHSURFHVVRUGLIIHUHQWLDWHDPHPRU\DFFHVV UHDGZULWH VLJQDO from an I/O access (read/write) signal? :K\LVFU\VWDODSUHIHUUHGFORFNVRXUFH" :KLFKLQWHUUXSWKDVWKHKLJKHVWSULRULW\LQWKH":KDWLVWKHSULRULW\RIWKH other interrupts? 33. When and where is the Ready signal used? :KDWDUH+ROGDQG+/'$"+RZDUHWKH\XVHG" 'UDZDJHQHUDOEORFNGLDJUDPRIDPLFURSURFHVVRUEDVHGV\VWHP([SODLQEULHÀ\University WKHYDULRXVEORFNVRIWKHV\VWHP*LYHVRPHH[DPSOHVRIWKHW\SHVRIGHYLFHVXVHG IRUHDFKEORFN :KDWLVDPLFURSURFHVVRU"6NHWFKDQGH[SODLQWKHYDULRXVSLQVRIWKH ([SODLQWKHRSHUDWLRQRIWKHVHVLJQDOV 5HDG\6DQG6+ROGDQG+/'$ DQG$/( Oxford ([SODLQWKHDUFKLWHFWXUHRIWKHZLWKWKHKHOSRILWVLQWHUQDOEORFNVFKHPDWLF diagram. /LVWWKHIRXUFDWHJRULHVRILQVWUXFWLRQVWKDWDUHXVHGIRUGDWDPDQLSXODWLRQ 'H¿QHRSFRGHDQGRSHUDQG,GHQWLI\WKHRSFRGHDQGWKHRSHUDQGLQWKHLQVWUXFWLRQ MOV H, L. ([SODLQWKHLQVWUXFWLRQ;&+* :KDWLVDQLQVWUXFWLRQ"/LVWDQ\IRXUDULWKPHWLFLQVWUXFWLRQVDQGWKHLUXVHV 'H¿QHVWDFN([SODLQWKHLQVWUXFWLRQVUHODWHGWRVWDFNRSHUDWLRQV :KHQLVWKHLQVWUXFWLRQ;5$$XVHG" +RZPDQ\RSHUDWLRQVDUHWKHUHLQWKHLQVWUXFWLRQVHWRIWKHPLFURSURFHVVRU" ([SODLQZLWKH[DPSOHVWKHGLIIHUHQWLQVWUXFWLRQIRUPDWVEDVHGRQWKHOHQJWKRIWKH instructions. /LVW WKH IRXU LQVWUXFWLRQV ZKLFK FRQWURO WKH LQWHUUXSW VWUXFWXUH RI WKH microprocessor. :KDWLVWKHODVWLQVWUXFWLRQH[HFXWHGLQDSURJUDP":K\" © Oxford University Press. All rights reserved. 46 Microprocessors and Interfacing :KDWLVWKHVLJQL¿FDQFHRI;&+*DQG63+/LQVWUXFWLRQV" ([SODLQWKHRSHUDWLRQFDUULHGRXWZKHQWKHH[HFXWHVWKHLQVWUXFWLRQ567 :KDW LV DGGUHVVLQJ" :KDW DUH WKH YDULRXV DGGUHVVLQJ PRGHV DYDLODEOH LQ WKH " ([SODLQGLUHFWDGGUHVVLQJZLWKDQH[DPSOH ([SODLQLPSOLHGDGGUHVVLQJZLWKDQH[DPSOH :KDWDUHWKHPDFKLQHF\FOHVLQWKHPLFURSURFHVVRU" THINK AND ANSWER &RPSDUHWKHLQVWUXFWLRQV&$//DQG386+ :KDWLVWKHGLIIHUHQFHEHWZHHQWKHVKLIWDQGURWDWHLQVWUXFWLRQV" +RZPDQ\DGGUHVVOLQHVDUHWKHUHLQD î(3520FKLS" ([SODLQWKHGLIIHUHQFHEHWZHHQWKHLQVWUXFWLRQV-03DQG&$// ,IWKHLQVWUXFWLRQV&$//DQG5(7ZHUHQRWDYDLODEOHLQWKHZRXOGLWVWLOOEH possible to write subroutines? How would the subroutine be called? How would one return to the main program? Press University Oxford © Oxford University Press. All rights reserved.