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Report
Design of the processor-board for the Ceres-2 workstation
Author(s): Heeb, Beat
Publication Date: 1988-11
Permanent Link: https://doi.org/10.3929/ethz-a-000491598
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ETH Library •• , Eidgenossische lnstitut fUr lnformatik Technische Hochschule Fachgruppe ZUrich Computer Systeme
Beat Heeb Design of the Processor-Board for the Ceres-2 Woa·l November 1988 93 Design of the Processor-Board for the Ceres-2 Worl(station Beat Heeb Abstrad Ceres is a single user workstation based on the NS32032 microprocessor. The NS32532, a new, more powerful, but fully software compatible member of the NS32000 family made it possible to enhance the performance of the machine without much effort. Because of the modular structure of Ceres, only the processor board had to be changed, while the rest of the hardware and all software (except device handlers) remained unchanged. This paper describes the differences between the new processor board and the old one and presents the result of some performance measurements. Author's address: lnstitut fur lnformatik ETH-Zentrum CH-8092 Zurich I Switzerland (C) 1988 lnstitut fur lnformatik, ETH Zurich 4 1 Introduction Contents The Ceres workstation is a single user computer, designed by N. Wirth and H. Eberle between 1984 and 1986. Its Introduction main parts are a NS32032 processor from National Semiconductor and the corresponding Floating-Point-Unit (FPU) and Memory-Management-Unit (MMU). It includes a high-resolution display (1024 * 800 dots), a 40 MByte 2 Main Changes 5 Winchester disk, a floppy disk drive, keyboard, 3 button mouse and interfaces for V24 and a local network The main 2.1 The new Processor 5 properties of the machine are Its simple design and its open architecture. The latter made it possible to. add a 2.2 The new Bus Arbiter 6 high-resolution color display and an interface for a laser-printer without any problems. A technical description of the Ceres is given in [1], a more detailed analysis can be found in [2]. Miscellaneous Changes 11 3.1 The Mouse Interface 11 The modular structure of the machine makes it also possible to enhance its power without a complete redesign, 3.2 The Refresh- and I/O-Delay-Counter 12 more precisely, only the processor board has to be changed. This is especially fruitful when more powerful 3.3 The Address Decoder 13 processors exist that retain most of the properties of the existing one. Until now, two such processors are available, 3.4 The Boot ROM 14 the NS32332 and the NS32532. Both have the same programming model and are fully software-compatible with the NS32032 (on object code level). This Is essential because it hides the change from the programmer. Started in 1987 a 4 Measurements 15 prototype board was built for each of these two processors. After successful completion only the superior one (that 4.1 Performance 15 with the NS32532) was considered further. This paper documents the differences between this new processor board 4.2 Bus Utilization 17 and the old one. It also Includes results of some measurements made to compare the three variants and to quantify 4.3 Influence of Memory Speed 18 the reached progress. Conclusions 19 Appendices 2 Main Changes A Summary of User-Relevant Changes 20 B PAL and EPLD Listings 22 C Circuit Diagrams 27 2.1 The new Processor The central part of the processor board is the processor itself, dictating most of the logic requirements. For the description of a new processor board it is therefore necessary to present the important properties of the new processor first The following features of the NS32532 are noteworthy: 1) The clock rate is increased from 10 to 25 MHz 2) The processor includes the memory-management-unit (MMU) and the timing-control-unit (TCU) 3) There is a separate 32 bit address bus instead of a multiplexed 24 bit address bus 4) The minimal number of cycles per memory access is decreased from 5 to 2 5) A 512 byte instruction cache and a 1024 byte data cache are included in the CPU chip 6) The size of the data bus can be changed between 8, 16 and 32 bit for each memory reference 7) There is a special mode for reading multiple words from consecutive addresses (burst-mode) 8) The size of the MMU pages is increased from 512 to 4096 bytes (a consequence of the wider address bus) 9) There are some new instructions for cache control Details on the NS32532 can be found in [3]. 7 6 Points 2) and 3) have the positive effect that they simplify the processor cluster considerably: about such a design. A simple solution of this problem is to replace the latch and the priority-encoder by a single synchronous state-machine. The corresponding state diagram looks as follows: D -CPUREQ * CPUREQ* REQ3 * REQ2* REQ1 * REQO* REFREQ * DSPREQ D -REQ3 * -REQ3 * -REQ2 * -REQ1 * -REQO* -REFREQ * -DSPREQ -REQ2 * -REQ2 * -REQ1 * -REQO* -REFREQ * -DSPREQ -REQ1 * -REQ1 * A -REQO * -REFREQ * -DSPREQ -REQO * -REQO* -REFREQ * -DSPREQ A• -REFREQ * -REFREQ * -DSPREQ -DSPREQ -DSPREQ Figure 2.1 Processor clusters for the two processors Beside the 32 drivers used for the connection from the local and the the global data bus, the old configuration needs another 16 drivers connected between the lower half of the local and the upper half of the global data bus. This was necessary because the MMU NS32082 was designed forthe N$32016 and supports only a 16 bit data bus, but must Figure 2.2 Simple master control logic state diagram be able to access the page tables in the main memory. With the integration of the MMU in the new CPU this complication disappeared. Each state means that the corresponding grant output is active, except in the idle state where no output is active. An additional signal, active in each state except idle, is needed to start the bus timing. The ROY signal is activated by the The only slave processor not included In the CPU is the floating-point-unit (I·PU). Corresponding to the processors, bus control unit during the last clock cycle of a memory access and is used as a start signal for the next access by the the old unit (a N$32081) is replaced by a new faster one (a NS32381). Apart from speed the only difference between master control unit the two versions is the data interface enhanced from 16 to 32 bit. Because the FPU connects directly to the CPU without any discrete logic needed, this change causes no further problems. The FPU is documented in (3]. This solution, while being clean and elegant, doesn't solve the problem that motivated the asynchronous solution on the old board: The request signal available from the processor is valid too late to be latched synchronously without Random logic is needed, however, for the bus signals BE0• .3 (byte enable), RIW (read/write), and /LO (interlocked a wasted clock cycle. This fact can be seen as a mistake in the design of the NS32032, however on the NS32532 the operation), for the ROY (ready) input, and for the enable input of the data drivers. All these signals are produced by a late availability of the request signal is unavoidable because preceding each memory access the cache must be single user-programmable logic device (PAL). This solution is not only fast and elegant but also flexible. The latter checked for a hit, in which case no request is to be activated. The NS32532 drives three signals at the beginning of a became important when it was· discovered in first tests that the BE signals are invalidated too early by the processor memory access, namely the ADS (address strobe), BMT(begin memory transfer), and CONF (confirm). to meet the requirements of the RAM board on highest speed. This problem could be solved by latching the BE signals until the end of the ROY signal. This change was done without modifying the hardware, just by reprogramming the device. 2.2 The new Bus Arbiter CLK A0 .. 31 The central part of the processor board (and also of the whole computer) is the arbiter which manages the bus and determines the actual bus master. The arbiter is conceptually independent of the CPU and all other bus masters, but, ADS' because the CPU is the bus master most of the time, the performance of the whole system strongly depends on a fast interaction between the CPU and the arbiter. It was therefore necessary to change the arbiter according to the BMr requirements of the new processor. CONF' The arbiter consists of two loosely coupled parts which could be named as the master control unit and the bus Figure 2.3 NS32532 memory access timing control unit. The former resolves bus request conflicts by a fixed priority scheme and determines the actual bus master, the latter controls the general bus signals and fixes the bus timing. ADS is active during the first clock cycle of each memory access, BMT is activated simultaneously with Aos· but is immediately when a cache hit is detected, CONF is activated after the second half of the first clock cycle The master control unit on the old processor board consists of an asynchronous latch and a (combinatorial) dea~ivated and os active only when the memory access is really needed. CONF has the other important priority-encoder. This asynchronous latch doesn't satisfy in two ways: first, it is difficult to generate a proper enable guarantee~ ~o bec~me property of remaonong actove until the end of the access, which makes it an ideal request signal. signal, particularly when the clock rate is increased to 25 MHz, and second it is nearly impossible to reason formally 8 9 In order to use this late request signal without wasting the first dock cycle, the following changes are necessary: First Figure 2.5 shows the resulting state diagram: the bus must be dedicated to the processor by default whenever no request signal Is active. This was also done on the old board and can easily be implemented by merging the states Idle and CPU. Bu~ although this was sufficient on the old asynchronous approach it is not on the new one; In a synchronous system, a start signal depending on the CPU request valid in the first cycle cannot be active before the second cycle. The only solution here is to make NDBE+ that the normal case. This Is possible because the only bus signal activated during the second dock cycle is DBE IOEN * NloRdy (data buffer enable) which can be merged with the start signal. In other words, the master control logic provides the DBE signal in the second cycle Instead of a start signal in the first one. But then the state machine must be changed such that the first cycle can be distinguished from the others. This requires doubling each state and gives the following final state diagram: NREQ3 * REQ3 * REQ2* REQ1 * REQO* REFREQ * DSPREQ NREQ2 * NREQ2 * NREQ1 * NREQO* NREFREQ * NDSPREQ NREQ1 * NREQ1 * NREQO* NREFREQ * NDSPREQ NREQO* NREQO * NREFREQ * NDSPREQ NIOEN * NREFREQ * NREFREQ * NDSPREQ NWAIT2* NDSPREQ NDSPREQ (WAIT1 + CWAIT) .-----!cpu· R3' R2' R1' RO' REF' DSP' NCPUREQ+ CPUREQ* REQ3 + NREQ3 * REQ2+ NREQ2 * Figure 2.5 Bus control logic state diagram REQ1 + NREQ1 * REQO+ NREQO * REFREQ + NREFREQ * The CLR.REQ signal, introduced as a reset signal for the request flip-flops of the various masters, is no longer needed, DSPREQ NDSPREQ because, as a consequence of the synchronous master control unit, these flip-flops can be reset directly by the corresponding grant signal. For being compatible with existing boards, the signal is held active on the new processor board. The signals /oAcc and /oRdy are added for communication with the 1/0 delay counter described latter. Thanks to the smaller number of output signals needed and with some effort in finding an efficient coding for the Figure 2.4 Final master control logic state diagram states, it was possible to realize this state machine with another single PAl device (16R8). Because both parts of the arbiter are synchronous machines operating with the same dock, they can be seen as one single state machine too. The upper row of states corresponds to the first dock cycle, during the other states the DBE is active. The grant However a description of this machine as a whole leads to an explosion of states and has no advantage over the outputs are active in either of the two corresponding states, implying that exactly one grant is active in each cycle. presented two-part specification. The whole state machine is implemented in one PAl device .(16R8). The other state machine needed is the bus control unit. To hold compatibility with existing memory boards, while using the higher clock speed of the new processor, a memory access covers at least 6 cycles. Because the processor can fetch or store an operand in two cycles, at least 4 wait states must be inserted. In the case of an 1/0 device 12 additional wait states are required to achieve the desired delays. Since the first cycle is handled by the master control unit, the machine consists of 5 main and 12 wait states. Compared with the old board the total number of states Is nearly the same; the reason lies in the fad that the clock speed and the number of states had to be doubled on the old board to reach the granularity required by the bus signals. Beside the 12 wait states inserted when IOEN (1/0 enable) is active, one or two walt states can be inserted by activating the signals WAIT1 or WA/12. In contrast to the old board, a third wait state is Inserted when WAIT1 and WA/12 are both active. This is necessary because one wait state on the new board is much less than one on the old. As before, an unlimited number of extra wait states take place as long as CWAIT (continuous wait) is active. 10 11 The following timing diagram contains the specification of all relevant bus signals: 3 Miscellaneous Changes (timing inteiVals In ns) 3.1 The Mouse lntetface T1 T1 T2 T3 T4 T5 r-- The function of the mouse interface is to make the physical position of the mouse available to the programmer. To CLK -,__ 11_11_ h-h- !L-!L- do that, the mouse provides two pairs of phase coded signals, one for the horizontal and one for the vertical movement The actual coordinates can be determined from these signals by a direction discriminator and an REQ' ~ I up/down counter for each directio~. The values of these counters can be read by the processor through an I/O-port ~<12 GNT I rr- On the old board the mouse interface was built with a PAL for the direction discriminators and standard chips for the counters. With a total of more than seven chips, this interface consumes a considerable part of the total space ~<12 and power. Thanks to the availability of new, advanced programmable logic devices (EPLDs) the number of DBE' I I rr- components on the new board could be reduced drastically. Because the interface consists of two identical, ~<12 independent parts, tw~ PlDs can be used with the same contents. Figure 3.1 shows the logic needed: DS' I I rr- ~<12 ~<12 RDY I I 1---1_<3 A,AV', R/W' 1---1 1-- ~<2 BEn' I I I 12 Bit DO .. D11 >20~ Counter j-- Din '--1-- <47 D out - 1--- - Select * Write >15_14- Select* Read WAIT I I Figure 3.1 Mouse logic for one dimension Figure 2.6 Bus signal timing The mouse signals MA and MB are first synchronized and delayed by four D-flip-flops. By comparing the delayed It is noteworthy that it was possible to reduce the time for a whole memory access from 500ns to 240ns using the with the undelayed signal, the control logic then detects the rising and falling edges and enables the counter for same memory board, because only two of the five bus cycles are used for memory access on the old processor. The Incrementing or decrementing. A read from the attached address enables the outputs of the counter while a write to rest is wasted for transferring virtual and physical addresses over the data bus and for releasing the bus in the last the same address resets the counter to. zero. The logic equations for the control logic contain all relevant cases: cycle. Up MA1 * MA2 * NMB1 * MB2 + MA1 * NMA2 * MB1 * MB2 + Finally we can conclude that the new arbiter is not only better adapted to the new CPU, but that also its behaviour NMA1 * MA2 * NMB1 * NMB2 + NMA1 * NMA2 * MB1 * NMB2; can be described more precisely and its implementation is much simpler. Down MA1 * MA2 * MB1 * NMB2 + NMA1 * MA2 * MB1 * MB2 + MA1 * NMA2 * NMB1 * NMB2 + NMA1 * NMA2 * NMB1 * MB2; The chip chosen for the realization of this circuit is the EP600 from Altera Corporation [4]. This chip contains 16 independently configurable 1/0 macro cells, 4 additional inputs, and a logic array connecting all together. of the 16 macro cells, 4 are used as D-flip-flops and the remaining 12 are configured as toggle-flip-flops with tri~state outputs for the counter. The control logic together with the logic needed to build the counter fit well into the logic array. The formal description of the whole chip is contained in appendix B. 12 13 Beside the two chips for the x and y coordinates, a single driver chip is necessary for the mouse button signals. An and must be synchronized by a flip-flop. This is not hard, because these flip-flops fit into the chip already needed additional decoder present on the old board is avoided by presenting the three values (x, y, and buttons) in one for synchronizing the master reset and interrupt request signals which are asynchronous anyway. double-word instead of assigning a separate 1/0 address to each of them. Figure 32 shows the location of the values in this double-word: RefReq and RFSH are connections to the master control logic, which starts the refresh cycles. JoAcc is a signal generated by the bus control logic during each 1/0 cycle. JoRdy. which is fed back to the bus control logic, prevents 31 23 0 the start of a new 1/0 cycle when it is inactive. 0 y X Figure 3.2 Mouse 1/0 port 3.3 The Address Decoder Note that the x and y coordinates can still be read Independently by using word-wide read operations. The main function of the address decoder is to deliver some bus signals like the /OEN, which is active wheneve~:!!_Je address lies within the 1/0 domain, as well as the select signals for the individual 1/0 devices on the processor 3.2 The Refresh- and I/O-Delay-Counter board. Because the wider address bus of the NS32532 leads to new 1/0 addresses anyway, the addresses are changed such that each of the major devices ·lies in a separate MMU page, which allows to protect devices individually against illegal accesses. Figure 3.5 shows the resulting memory map: To refresh the dynamic RAM chips used in the Ceres periodically, a refresh-counter Is used that requests the bus every 16~s. Instead of a data transfer, a refresh cycle is started by the RFSH signal which Is simply the grant corresponding to the refresh request. On the old board the refresh-counter consists of a counter driven by the .------.,FFFFFFFF - FFFFFFFF - FFFFFFFF processor clock (10MHz) and a flip-flop which is set when the counter value reaches 160 and Is cleared by the RFSH p::...::.==; FFFCOOOO NMI Ack FFFFFFOO signal. INT Ack FFFFFEOO Clr Parity FFFFFDOO The delay-counter Is not present on the old board; its introduction was motivated by the following problem: Some ROM FFFFEOOO DIP Switch FFFFFCOO 1----JFEFSOOOO of the 1/0 devices (disk controller, sec, and RTC) not only need a longer access tune, which is guaranteed by the 1/0 sec Clr Boot FFFFFBOO Disp. Cont. cycle of the arbiter, but also a minimal time of about 1 ~s between two accesses. On the old board this delay had to FFFFDOOO FFFFFAOO 1----;FEFOOOOO be achieved by proper measures in software. With the new, considerably faster processor this is no longer feasible, Color UART because, on the one hand the violations are more frequent and less obvious, on the other hand the cache makes it VRAM FFFFCOOO FFFFF800 1----JFEESOOOO Printer nearly impossible to guarantee a delay by software. The only proper way is to guarantee the delay by hardware. This 1----1 FEE40000 Mouse Interface is done by a circuit consisting of a counter and a flip-flop, a circuit similar to the refresh counter. FFFFBOOO FFFFF600 1--'-V'-"RA:..::M.!.!.--l FEEOOOOO Color Disp. RTC Control FFFFAOOO FFFFF400 To minimize the expense for the two counters, another EP600 is used for both circuits. A block diagram of the two Color Disp. parts is contained in Figure 3.3 and 3.4: ICU Palette FFFF9000 FFFFF200 Disk Color Disp. Controller Cursor FFFF8000 FFFFFOOO PCik PCik Figure 3.5 Memory Map Like on the old board, the address decoder consists of a PAL device (16L8) for the coarse decoding and two decoders for the individual select signals. In contrast to the old solution, only a minimum of the address signals is directly connected to the PAL, the remaining signals (A19.. A23, A25 .. A31), which must be high in all considered cases, are combined with a single AND-gate. This not only solves the problem of the increased number of address lines, but also leaves a part of the PAL unused, giving room for some random logic needed for the CLR.PAR signal on the bus and the JoOec signal used by the processor to handle 1/0 accesses correctly. Figure 3.3 Refresh counter Figure 3.4 1/0 delay counter Another part related to the address decoder is the boot logic. During the boot phase (after CPU reset) the ROM PC/k is a 6MHz clock signal used by the. sec chip (serial communications controller). It was chosen instead of the space must start at address zero because the program counter is cleared by a system reset and the initial program processor clock because that simplifies the design and, more important, makes the design independent of the actual must therefore start at address zero. The boot phase is identified by a special flip-flop, set by the RESET signal and processor clock frequency. The only drawback is that the resulting signals have no relationship to the processor clock cleared by an access of the 'Clear Boot' 1/0 address under software control. 14 15 on the old board the special address mapping is achieved by manipulating the processor address bus in a way such 4 Measurements that the RAM space starting at zero is mapped to the ROM space. On the new board a simpler solution is used: Instead of manipulating the address bus, the behaviour of the RomEn (ROM enable) signal is changed during the boot phase in a way that every read cycle not belonging to an 1/0 device accesses the ROM. To prevent other devices 4.1 Performance like the RAM from beeing accessed simultaneously, the AV signal (address valid) is held inactive during these special ROM accesses. The additional logic needed for these signals as well as the boot flip-flop itself could be placed in the address decoder PAL The main motivation for the design of a new processor board was an expected gain in performance. For a quantification of the gain, the execution times of some test programs were measured. To get a complete view over the available parts of the NS32000 series, the following Ceres configurations were compared: 3.4 The Boot ROM -The old processor board with the NS32032 operating at 10M Hz The boot ROM holds the initial program which typically loads the final system programs from the disk. The usual 28 - A prototype board with the NS32332 operating at 15MHz pin ROM chips are accessed byte by byte. To support a 32 bit data bus, four such chips are needed. This is very -The new processor board with the NS32532 operating at 25M Hz but without caches inefficient because even one chip is far too big for a typical boot program. To avoid this problem, the dynamic bus - The new processor board with enabled data- and instruction caches sizing feature of the new processor is used. Through an input signal of the processor, which is made available on the bus as the BYTE signal, it is possible to switch to an 8 bit wide data bus for each memory access. By activating this It is noteworthy that the measurements were made on the same physical machine with only the processor board signal for ROM accesses, a single ROM chio suffices. The only drawback, the reduction of execution speed, Is changed. This ensures that the rest of the hardware, in particular the memory, as well as the programs are exactly insignificant, because the ROM is used during system startup only and has no influence afterwards. identical and results in a fair comparison of the processors and their bus interface. The ROM devices normally used are EPROMs (erasable, programmable read only memory) which can be The benchmark programs used for performance comparison in [2] are not useful here because they execute a small programmed and erased by the user with a special hardware unit This way of programming Is well suited for the loop with only a few instructions in it The instructions as well as the variables of such a loop would fit entirely in manufacture of small series, but is a time consuming task during the development of the boot program. A better way the caches, resulting in a very fast execution, but the execution times are no longer related to those of real programs. is to use an EEPROM (electrically erasable, programmable read only memory) which can be programmed without To bypass this problem the following programs are chosen for comparison: being removed from the machine. Because the used EEPROM (2864) is pin compatible to the corresponding EPROM (2764), the ROM logic could easily be extended to support both types. The only changes are the use of a bidirectional data driver and an additional logic for the write signal. To prevent the ROM from being overwritten Quid Bit Blod< Transfer Bit Block Transfer moves a square of 512 by 512 pixels on the screen. The distance is chosen in a way that each word must be shifted during the transfer_ Display Character A program which displays a 12 pixel high character on the screen. The average over all characters of the alphabet is chosen and the font patterns are already contained in memory. Layout Ched< This program is part of a layout editor for printed circuit boards. It verifies the final layout against a formally defined netlist. The program contains complex algorithms as well as large data structures holding both the layout and the netlist in the main memory. Compile The Modula 2 compiler_ Because this program frequently accesses the winchester disk, its performance is more influenced by the disk controllerthan by the processor. It is included in this list for completeness. 17 16 A comparison of the execution times of these programs running on the different processors Is shown in Flgur,e 4.1: 4.2 Bus Utilization Using a faster processor with equally rapid memory forces an increase of bus utilization. When this comes close to 0 2 3 4 6 7 8 100%, the memory Interface becomes a serious bottleneck for the system. To see whether that happens, the bus - utilization was measured for the same system configurations and programs as above. The measuring was done by A 1.0 counting the memory references with a simple frequency counter. The expected utilization can be calculated as the B 1.9 I Quicksort product of the access frequency and the memory cycle time. The results are shown in Figure 4.2: c 3.9 D 7.3 I roo-- A 1.0 0 10 20 30 40 50 60 70 80 90 100 % B 1.9 Dhrystone c 2.9 A 36 I D 4.6 I B 48 Quicksort I c 75 A -1.0 I D 24 I Bit Block B 2.0 Transfer c .3.4 I A 49 I D 8.2 II B 69 Dhrystone I c 77 A -1.0 I D 61 Display B 2.0 I Character c 3.5 I A 45 I D 6.8 I Bit Block B 60 r-- Transfer c 73 A 1.0 I D 33 I layout B 1.9 Check c 2.5 I A 44 I D 6.2 I Display B 62 I Character c 78 I A - ~ D 51 il B 1.4 Compile !1 c 1.8 I A 58 I D 2.2 I layout B "83 I Check c 87 I D 35 I A: NS32032, 10MHz B: NS32332, 15MHz C: NS32532, 25MHz, no caches A: NS32032, 10MHz D: NS32532, 25MHz, caches enabled B: NS32332, 15MHz C: NS32532, 25MHz, no caches D: NS32532, 25MHz, caches enabled Figure 4.1 Relative performance Figure 4.2 Bus utilization As expected the performance increases for each new processor. The gain is higher than the difference in clock speed, showing that the efficiency of the micro-code of the new processors is also improved. The most important increase, however, comes from the caches, which almost double performance. Bus utilization of the NS32532 approaches 90%, which is considerably high. Enabling the caches, however, results in values mostly below that of the NS32032, which is surprisingly low. The conclusion is that. thanks to the caches, even an additional increase in the speed of the processor would be possible without a serious problem with the memory bandwidth. 19 18 4.3 Influence of Memory Speed 5 Conclusions To analyse the interaction of the memory and the processor further, the influence of the memory speed on the system performance was examined directly. This was done by comparing the NS32532 board with a special version A new processor board was built for the Ceres workstation. The major changes are the replacement of the NS32032 providing a memory cycle time of 5 instead of 6 dock cycles. To use this special board with the normal memory, the CPU by a more powerful member of the software compatible NS32000 family and the adaptation of the bus arbiter CPU dock frequency was lowerd from 25 to 20MHz. The measured performance was then corrected with a constant which is the heart of the system. Some minor changes were done to make the design simpler and cleaner. Some factor. Figure 4.3 shows the results: parts were replaced by modem, flexible programmable logic devices (EPlDs). The result is a board with a chip count decreased from 64 to 45, a current consumption reduced from 2.7 to 1.5 1.0 1.1 12 Ampere, but with a performance Increased by a factor of 5 to 8. The board is compatible with all existing Ceres boards on the hardware side and needs only a few changes in system programs (1/0 addresses) on the software A 1.11 side. Quicksort I B 1.02 I Measurements were made to examine the properties of the system. Beside the mentioned performance win, the A 1.12 I Dhrystone results suggest that the existing memory board, although designed for a much slower processor, is still a good B 1.07 I choice, because the effect of the higher frequency on the memory bandwidth is neutralized by the caches included in Bit Block A 1.14 I the processor. Transfer B 1.03 I Display A 1.14 I A prototype on a wire wrap board was operating 4 month after the start of the project The final version, built on a Character B 1.06 I printed circuit board, took another 3 month. A series of 30 computers containing the new board is currently being completed. layout A 1.16 I Check B 1.04 I The only substantial problem encountered during the design was an elect~ical interference between some wires on the prototype, which disappeared entirely on the final board. it seems that a processor operating at 25MHz reaches the limits beyond which a wire wrap prototype is no longer feasible. A: NS32532, 25MHz, no caches B: NS32532, 25MHz, caches enabled Aclcnowledgements Figure 4.3 Performance win due to the elimination of a wait state I wish to thank N. Wirth for the suggestion and guidance of the project. I also wish to thank H. Eberle for the Without caches the reduction of the memory cycle from 6 to 5 dock cycles results in a performance improvement of development and documentation of the Ceres, without which my work had never been possible. Finally 1 wish to 11 - 16%, which is near the theoretical limit of 1/6. With enabled caches the win decreases to a few percent Each thank I. Noack and A. Weiss for their untiring help in solving practical problems. further eliminated wait state brings a still worse result because the internal execution times of the processor become more dominant In contrast, the cost of faster memory increases more than linearly with the number of saved wait states. References The results of this and the above measurements show that the comparatively slow memory board built for the [1) H. Eberle: Hardware Description of the Workstation Ceres, NS32032 is still a good solution for the NS32532, although the four wait states look poor at first sight Any effort for lnstitut fUr lnformatik, ETH Zurich, report no. 70, January 1987 speeding up memory would not be jusified by the expected gain. [2) H. Eberle: Development and Analysis of a Workstation Computer, Ph. D. thesis no. 8431, ETH Zi.irich, 1987 [3) Series 32000 Microprocessors Databook, National Semiconductor, 1988 [4) ALTERA Data Book, Altera Corporation, January 1988 [ 5) R. P. Weicker: Dhrystone: A Synthetic Systems Programming Benchmark, Comm. of the ACM, Vol. 27, No. 10, October 1984, pp. 1013-1030. 21 20 Mouse Appendix A: Summary of User-Relevant Changes - X counter: bits 0 ..11 - Y counter: bits 16.. 23 (bits 0 .. 11 of high word) -buttons: ML: bit 14, MM: bit 13, MR: bit 12 (0 =pressed, 1 = released) - A write to the mouse port resets both counters to zero Software Differences DIP-Switch Bit 8: Boot switch (1: normal I 0: special) - Mouse: $FFFFBOOO < $FFFDOO .. $FFFD08 > The following bus signals are changed: - UART: $FFFFCOOO .. $FFFFC03C < $FFFD40.. $FFFD7C > - SCC: $FFFFDOOO .. $FFFFDOOC < $FFFD80 .. $FFFD8C > BUS.ERR' pin Aa13 - INT acknowledge: $FFFFFEOO < $FFFFEOO > New signal, Raises a bus-error exception on the processor. - DIP-switch: $FFFFFCOO < $FFFDCO > - Clear boot: read from $FFFFFBOO < write to $FFFDCO > -Clear parity: read from $FFFFFDOO - new configuration register IO.EN' pin Ba11 - new debug registers Active when the address lies In the new 1/0 domain: $FFFCOOOO .. $FFFFFFFF. - V bit in the PSR for automatic overflow trap - new instructions: BYTE' pin Ba16 CINV cache invalidate LPR CFG, x load configuration register New signal. Tells the processor to use a byte-wide bus for the actual memory access: SPR CFG, x store configuration register CLI< pin Ba25 MMU Processor clock increased from 10 to 25MHz. -4 kB pages - new registers FCLI< pin Ba27 No longer supported. FPU - 8 LONGREAL-registers < 8 REAL or4 LONG REAL> ( F1 is still part of LO!) - new bits in the status register A24 pin Bc25 to A31 pin Bc32 - new instructions: SCALB x, y y := y * 2~TRUNC(x) New signals. Most significant byte of the 32 bit address bus. LOGB x, y y := TRUNC(Iog2(x)) DOT X, y LO := LO + x * y POLYx,y LO:=y+x*LO sec Receiver driver enabled via DTR output (independant of transmitter driver) 22 23 Bus Control PAL PAL time25: 16R8; Appendix B: PAL- and EPLD Listings (* NS32532 25MHz Bus Timing State Machine B. Heeb, 26.5.88 *) PIN 2: -DBE; 19 -IoAcc; 3: -WRITE; 18 ROY; 4: -IOEN; 17 -OS; Master Control PAL 5: -WAIT2; 16 -lORD; 6: -WAIT1; 15 -IOWR; 7: -CWAIT; 14 -dO; PAL prio: 16R8; 8: -IoRdy; 13 -d1; (* NS32532 Priority Encoder B. Heeb, 8.3.88 *) 12 -d2; PIN 2: -DSPREQ; 19: -DSPGNT; (* ROY dO d1 d2 IoAcc 3: -RefReq; 18: -RFSH; Tl: 0 0 0 0 0 4: -REQO; 17: -GNTO; T2: 0 1 1 1 0 5: -REQ1; 16: -GNT1; T3: 0 0 1 1 0 6: -REQ2; 15: -GNT2; T4: 0 1 0 1 0 7: -REQ3; 14: -GNT3; W12: 0 0 0 1 0 8: -CpuReq; 13: -CpuGnt; W11: 0 1 1 1 1 9: ROY; 12: -DBE; W10: 0 0 1 1 1 W9: 0 1 0 1 1 EQUATIONS W8: 0 0 0 1 1 W7: 0 1 1 0 1 DSPGNT ROY * DSPREQ W6: 0 0 1 0 1 + -DBE * CpuGnt * DSPREQ W5: 0 1 0 0 1 + DSPGNT * -ROY; W4: 0 0 0 0 1 W3: 0 1 1 0 0 RFSH := ROY * RefReq * -DSPREQ W2: 0 0 1 0 0 ! R~~~ : :~g~n; ~D~~~~~f * -DSPREQ Wl: 0 1 0 0 0 T5: 1 0 0 0 0 *) GNTO := ROY * REQO * -RefReq * -DSPREQ EQUATIONS + -DBE * CpuGnt * REQO * -RefReq * -DSPREQ + GNTO * -ROY * -RFSH * -DSPGNT; -ROY := -dO + dl GNT1 ROY * REQ1 * -REQO * -RefReq * -DSPREQ + IoAcc + -DBE * CpuGnt * REQ1 * -REQO * -RefReq * -DSPREQ + CWAIT + GNT1 * -ROY * -GNTO * -RFSH * -DSPGNT; + d2 * -IoAcc * IOEN GNT2 := ROY * REQ2 * -REQ1 * -REQO * -RefReq * -DSPREQ + d2 * -IoAcc * WAIT! + -DBE * CpuGnt * REQ2 * -REQ1 * -REQO * -RefReq * -DSPREQ + d2 * -IoAcc * WAIT2; + GNT2 * -ROY * -GNT1 * -GNTO * -RFSH * -DSPGNT; dO := -dO * -dl * -d2 * -IoAcc * -ROY * DBE * -IOEN GNT3 := ROY* REQ3 * -REQ2 * -REQ1 * -REQO * -RefReq * -DSPREQ ! =~8: d~l•*-~i * -IoAcc *-ROY* DBE * IoRdy + -DBE * CpuGnt * REQ3 * -REQ2 * -REQ1 * -REQO * -RefReq * -DSPREQ + -dO * d2 * -ROY + GNT3 * -ROY * -GNT2 * -GNT1 * -GNTO * -RFSH * -DSPGNT; + -dO * IoAcc * -ROY CpuGnt := ROY * -REQ3 * -REQ2 * -REQ1 * -REQO * -RefRea * -DSPREQ + dO * -dl * d2 * -IoAcc * WAIT! * -IOEN * -ROY + dO * -dl * -IoAcc * CWAIT * -IOEN * -ROY; ! =~~: ~~~G~t-~NT~E~3-~NT~E~2-~NT~E~1-~NT~E~ -~s~e;R:gs~GN~SPREQ + -ROY * -CpuGnt * -GNT3 * -GNT2 * -GNT1 * -GNTO * -RFSH * -DSPGNT; d1 := -dO * -dl * -d2 * -IoAcc * -ROY * DBE * -IOEN =~8: =~1 d~2•*-~~Acc *-ROY* DBE * IoRdy DBE : = -ROY * DSPGNT : : + -ROY * RFSH + -dO * -dl * IoAcc * -ROY + -ROY * GNTO + dO * dl * -ROY + -ROY * GNT1 + dO * -dl * d2 * -IoAcc * WAIT2 * -IOEN * -ROY; + -ROY * GNT2 + -ROY * GNT3 d2 := -dO * -d1 * -d2 * -IoAcc * -ROY * DBE * -IOEN ! =~i : 8E~~eq * -REQ3 * -REQ2 * -REQ1 * -REQO * -RefReq * -DSPREQ ! d~O•*d2dl :RD~2 * -IoAcc *-ROY* DBE * IoRdy + -dO * -d1 * d2 * -IoAcc * -ROY END prio. + dO * -d1 * d2 * -IoAcc * IOEN * -ROY + dO * -d1 * d2 * IoAcc * -ROY; IoAcc := -dO * -d1 * d2 * -IoAcc * -ROY + dO * loAcc * -ROY + dl * IoAcc * -ROY + d2 * IoAcc * ~ROY; OS := -dO * -d1 * -d2 * -IoAcc * -ROY * DBE * -IOEN ! 0go.•_Rg}: :i6w; -IoAcc *-ROY* DBE * IoRdy + OS * -ROY * -dO + DS * -ROY * dl + OS * -ROY * d2 + DS * -ROY * IoAcc + OS * -ROY * CWAIT; lORD dO * d1 * d2 * IoAcc * -WRITE + lORD * -ROY; IOWR := dO * d1 * d2 * IoAcc * WRITE + IOWR * -ROY * -dO + IOWR * -ROY dl + IOWR * -ROY** d2 + IOWR * -ROY * IoAcc + IOWR * -ROY * CWAIT; END time25. 25 24 Processor Control PAL MouseEPLD PAL proc: 1 6L8; B Heeb (* NS32532 Processor Control Logic B. Heeb 9.6.88 *) ETH Zuerich PIN 1: -CpuGnt; 8/6/88 2: -be3; 19: -ILO; 1.0 3: -be2; 18: -BE3; A 4: -bel; 17: -BE2; EP600 5: -beO; 16: -BEl; Ceres2 Mouse Counter 6: -ddin; 15: -BEO; 7: -ilo; 14: -WRITE; OPTIONS: TURBO = OFF 8: RDY; 13: -cpuRdy; 9: -DBE; 12: -BuffEn; PART: EP600 11: Slave; INPUTS: Clk1@1, Clk2@13, MA@2, MB@11, Write'@14, Sel'@23 EQUATIONS IF CpuGnt THEN BEO := beO * DBE * -RDY OUTPUTS: D0@3, D1@4, D2@5, D3@6, D4@7, D5@8, D6@9, + ddin * DBE * -RDY D7@10, D8@15, D9@16, D10@17, D11@18 + BEO * RDY; NETWORK: IF CpuGnt THEN BEl bel * DBE * -RDY Clkl = INP(Clk1) + ddin * DBE * -RDY Clk2 = INP(Clk2) + BEl * RDY; MA = INP(MA) IF CpuGnt THEN BE2 := be2 * DBE * -RDY MB = INP(MB) + ddin * DBE * -RDY nWrite = INP(Write') Write= NOT(nWrite) + BE2 * RDY; nSel INP(Sel') Sel = NOT(nSel) DO,DO = TOTF(DOt, Clk1, Clr, , OutEn) IF CpuGnt THEN BE3 := be3 * DBE * -RDY D1,D1 = TOTF(D1t, Clk1, Clr, OutEn) + ddin * DBE * -RDY D2,D2 TOTF(D2t, Clk1, Clr, OutEn) + BE3 * RDY; D3,D3 TOTF(D3t, Clk1, Clr, OutEn) IF CpuGnt THEN WRITE := -ddin * -DBE D4,D4 = TOTF(D4t, Clk1, Clr, , OutEn) + WRITE * DBE; DS,DS TOTF(DSt, Clk1, Clr, OutEn) D6,D6 TOTF(D6t, Clk1, Clr, OutEn) IF CpuGnt THEN ILO := ilo; D7,D7 = TOTF(D7t, Clk1, Clr, , OutEn) IF TRUE THEN CpuRdy := RDY CpuGnt + Slave; D8,D8 TOTF(D8t, Clk2, Clr, OutEn) * D9,D9 TOTF(D9t, Clk2, Clr, , OutEn) IF TRUE THEN BuffEn := CpuGnt * DBE; D10,D10 = TOTF(D10t, Clk2, Clr, , OutEn) D11,D11 = TOTF(D11t, Clk2, Clr, , OutEn) END proc. MA1 = NORF(MA1d, Clk2, , ) MB1 NORF(MB1d, Clk2, ) MA2 = NORF(MA2d, Clk2, , ) MB2 = NORF(MB2d, Clk2, , ) Address Control PAL EQUATIONS: MA1d MA; PAL Addr: 16L8; MB1d MB; MA2d MA1; (* NS32532 Address Control Logic B. Heeb 10.6.88 *) MB2d MB1; MAl & /MA2 & MB1 & MB2 + PIN 1: -CpuGnt; Up MA1 & MA2 & /MB1 & MB2 + 2: A16; 19: -IoSel; /MA1 & MA2 & /MB1 & /MB2 + /MAl & /MA2 & MB1 & /MB2; 3: A17; 18: -boot; Down MA1 & MA2 & MB1 & /MB2 + /MAl & MA2 & MB1 & MB2 + 17: -AV; MA1 & /MA2 & /MB1 & /MB2 + /MAl & /MA2 & /MB1 & MB2; ~: ~~~i.d; 16: -WRITE; OutEn /Write & Sel; 6: A24; 15: -IOEN; Clr Write & Sel; 7: -RESET; 14: -CLRPAR; DOt Up + Down; 8: -clrPar; 13: -IoDec; Dlt Up & DO + Down & /DO; 9: -ClrBoot; 12: ...... RamEn; D2t Up & DO & D1 +Down & /DO & /D1; 11: -Ioinh; D3t Up & DO & D1 & D2 + Down & /DO & /D1 & /D2; D4t Up & DO & D1 & D2 & D3 + Down & /DO & /D1 & /D2 & /D3; EQUATIONS DSt Up & DO & D1 & D2 & D3 & D4 + Down & /DO & /D1 & /D2 & /D3 & /D4; D6t Up & DO & D1 & D2 & D3 & D4 & DS + IF TRUE THEN IoSel := A16 * A17 * A18 * A24 * HiAd * AV * -Ioinh; Down & /DO & /D1 & /D2 & /D3 & /D4 & /DS; IF TRUE THEN boot RESET D7t Up & DO & D1 & D2 & D3 & D4 & DS & D6 + + boot * -ClrBoot; (* RS Latch *) Down & /DO & /D1 & /D2 & /D3 & /D4 & /DS & /D6; D8t Up & DO & D1 & D2 & D3 & D4 & DS & D6 & D7 + IF CpuGnt THEN AV := -boot + WRITE Down & /DO & /D1 & /D2 & /D3 & /D4 & /DS & /D6 & /D7; + A24; D9t Up & DO & D1 & D2 & D3 & D4 & DS & D6 & D7 & D8 + Down & /DO & /Dl & /D2 & /D3 & /D4 & /D5 & fD6 & /D7 & /D8; IF TRUE THEN IOEN := A18 * A24 * HiAd * AV * -Ioinh D10t Up & DO & Dl & D2 & D3 & D4 & D5 & D6 & D7 & D8 & D9 + + -A16 * -A17 * -A18 * -A24 * HiAd * AV * WRITE * -Ioinh; Down & /DO & /Dl & /D2 & /D3'& /D4 & /D5 & /D6 & /D7 & /D8 & /D9; D11t Up & DO & Dl & D2 & D3 & D4 & D5 & D6 & D7 & D8 & D9 & D10 + IF TRUE THEN CLRPAR := ClrPar + RESET; Down & /DO & /D1 & /D2 & /D3 & /D4 & /DS & /D6 & /D7 & /D8 & /D9 & /D10; IF TRUE THEN IoDec A18 * A24 * HiAd * AV + -A16 * -A17 * -A18 * -A24 * HiAd * AV * WRITE; END$ IF TRUE THEN RornEn -A16 * -A17 * -A18 * -A24 * HiAd * AV * -RESET + CpuGnt * boot * -A24 * -WRITE; END Addr. 26 27 Appendix C: Circuit Diagrams TimerEPLD B Heeb dO .. d31 a0 .. a31 ETH Zuerich 8/6/88 u2 u! R1 NS32532 CPU 1.0 C!O m 031 A 8T4 s /10 SPC' D10 030 EP600 f11 C14 St4 19 029 m FlO 815 Ceres2 IO & Refresh Timer St2 18 028 ST2 G11 Cl5 St1 K9 027 StQ K8 ST1 K4 816 OPTIONS: TURBO OFF STO 026 = Odin' B C16 16 ODIN' 025 £14 ••r A9 12 024 PART: EPGOO RSr 12 016 Clk A8 023 CU< HZ El5 022 INPUTS: RFSH'@2, IoAcc'@11, Clk G2 F14 £16 021 Vee 87 El 020 A5 NOE D1 Fl5 OUTPUTS: RefReq@3, IoRdy@4 019 PS1 C! F16 85 018 PSO G15 83 017 NETWORK: 84 GT6 016 Clk = INP(Clk) 811 HI 015 (11 HI nRFSH INP(RFSH') RFSH = NOT(nRFSH) 014 E10 116 nioAcc = INP(IoAcc') IoAcc = NOT(nioAcc) 013 G!O K16 RefReq SONF(RefReqs, Clk, RefReqr, ClrRef, , 012 = HIO K!5 011 IoRdy = SONF('IoRdys, Clk, IoRdyr, Clrio, , ) 15 !16 010 rO NOTF(rOt, Clk, ) t4 !15 09 r1 NOTF(rlt, Clk, ) K2 !14 08 11 M15 r2 NOTF(r2t, Clk, ) 07 H1 NT r3 NOTF(r3t, Clk, ) 06 M14 r4 NOTF(r4t, Clk, ) f2 05 E! NT 04 rS NOTF(rSt, Clk, ) C2 PI 03 r6 NOTF(r6t, Clk, , ) 82 R16 10 NOTF(iOt, Clk, Clrio, ., 516 02 11 NOTF(ilt, Clk, Clrlo, Pl5 01 i2 NOTF(i2t, Clk, Clrio, DO 6 86 EQUATIONS: i:~~~~:iliTF~==.=~C9 SON'FSSR' ClrRef = RFSH; % Refresh Timer % ...!!!'-""'-"!.Lj IOOEC' Clrio = IoAcc; ...l!!:£...~~ INVIC' rOt VCC; INV DC' rlt rO; lNVSET' CIA6 r2t rO & r1; Vee r3t rO & r1 & r2; CIA5 r4t rO & r1 & r2 & r3; CIM R10 .. 12 CIAJ rSt rO & r1 & r2 & r3 & r4 & jr6; 1k CIA2 r6t rO & r1 & r2 & r3 & r4 & (rS + r6); CIA1 RefReqs rO & r1 & r2 & r3 & r4 & /rS & r6; CIAO = Aa13 BUS.ERR' /1 RefReqr = GND; Cll iOt VCC; % I/0 Timer % BER' = BRr ilt = iO; Ba16 BYTE' 8W1 i2t = iO & i 1; BWO IoRdys i1 & i2; READY' IoRdyr = GND; 12 BIN' Aa7 PAR.ERR' END$ C ulnt' 87 RSr l Al INT' ~·~·~r~~Ai6~Vee 06 ~~6'· Vee N12 HOlD' Vee no SYNC' Dto CLK ns532.cpu1.Sil ETH ZOrich Processor Cluster Date: 10.6.88 28 29 V u1o u14 AlS645 Al5541 Ac32 031 2 d31 9 A31 AO BO 18 DO YO 11 Ac31 030 3 d30 8 A30 A1 81 17 01 Y1 12 Ac30 029 4 d29 7 A29 A2 B2 16 02 Y2 13 Ac29 028 5 d28 6 A28 A3 83 15 03 Y3 14 Ac28 027 6 d27 5 A27 A4 84 14 D4 Y4 15 Ac27 026 7 13 d26 4 A26 A5 85 05 Y5 16 Ac26 025 8 d25 3 A25 A6 66 12 D6 Y6 17 Ac25 024 d24 2 A24 A7 87 11 07 Y7 18 DIR G' GO' G1' 1 19 1 19 u11 u15 Al5645 Al5541 Ac24 023 2 18 d23 9 11 A23 AO 80 DO YO A<23 on 3 17 d22 •22 8 12 A22 A1 81 '" 01 Y1 Ac22 021 4 16 d21 7 13 A21 A2 82 02 Y2 Ac21 020 5 15 d20 a20 6 14 · A20 A3 83 '" 03 Y3 Ac20 019 6 14 d19 a19 5 15 A19 A4 84 04 Y4 A<19 018 7 13 d18 •18 4 16 A18 A5 85 05 Y5 A<18 017 8 12 d17 a17 3 17 A17 A6 86 06 Y6 A<17 016 9 11 d16 a16 2 18 A16 A7 87 07 Y7 DIR G' GO' G1' 1 19 1 19 u12 u16 Al5645 Al554t A<16 015 2 18 d15 9 11 A15 AO 80 DO YO Ac15 014 3 17 d14 •14 8 12 A14 A1 81 '" 01 Y1 A<14 013 4 16 d13 7 13 A13 A2 82 •13 02 Y2 A<13 012 5 15 12 a12 6 14 A12 A3 83 03 Y3 A<12 011 6 14 d11 a11 5 15 A11 A4 84 04 Y4 A<11 010 7 13 d10 a10 4 16 A10 A5 85 05 Y5 Ac10 09 8 12 d9 a9 3 17 A9 A6 86 06 Y6 Ac9 DB 9 11 dB a8 2 18 AS A7 87 07 Y7 OIR G' GO' G1' 1 19 1 19 u13 u11 Al5645 ALS541 Ac8 07 2 18 d7 9 11 A7 AO 80 •7 DO YO Ac7 06 3 17 d6 a6 ,. 12 A6 A1 B1 1>1 Y1 Ac6 05 4 16 d5 a5 13 A5 A2 82 02 Y2 Ac5 04 5 15 d4 a4 .. A4 A3 B3 D3 Y3 14 Ac4 03 6 14 d3 .. 15 A3 A4 84 •3 D4 Y4 Ad 02 7 13 d2 a2 16 A2 A5 B5 05 Y5 Ac2 m 8 12 d1 a1 17 A1 A6 86 ' 06 Y6 A<1 DO 9 11 dO ao )' 18 AO A7 87 07 Y7 9 r/w' CpuGnt' BuffEn' Jt ff ns532.cpu2.Sil ns532.cpu3.Sil ETH Zurich Reset-logic, Buffers Author: B. Heeb Date: 10.6.88 ETH Zurich Arbiter, Ref. Counter Date: 10.6.88 Addr. Decoder 30 31 RAl u31 Am9519A-1 Aa12 INT7' 2S 4 41 IR7 07 A<8 ~ ------Ds3695-. Aa11 INT6' 24 07 IR6 06 s 06 A In tAck' 4K7 52 07 A<8 06 Ac7 OS Ac6 04 AcS 03 A<4 02 Ad 01 A<2 ~~ 00 A ~K8.5 ~KB.4 K8.2 C>-"'KB,.Rx,.o.,______--'-l KB.TxO K8.3 +12V +12V R23 .. 2'5 IOK V243 RxD 6 TxO V14.2 V24.6 DSR RTS V24.4 V24.5 CTS V24.8 DCD 11 OTR V24.20 u16 R28 ..31 V24.1~ 1K fAlS645 -12V 2 18 07 AO BO 3 17 6 AI 81 V24.74 ul8 4 16 s 82 .!. A2 15 04 07 A<8 81 3V M3002 s A3 Bl 12 6 14 03 06 A<7 Vco VBB 03 A4 84 1~ 11 7 13 02 OS A<6 5. .40pf C5 + 02 AS BS V24.13 10 8 12 01 c::>---YfL 04 A ns532.cpu4.Sil ns532.cpt6.Sil ETH ZOrich ICU I DSW I UART Author: B. Heeb Date: 10.6.88 ETH ZOrich sec, RTC Author: B. Heeb Date: 10.6.88 32 •• , Eidgenossische lnstitut fUr lnformatik 00 Ac1 Fachgruppe 01 Ac2 Technische Hochschule Dl AcJ OJ Ar.f 04 k5 ZUrich Computer Systeme 1)5 A<6 D6 1.<7 07 Ac8 u25d 1117~8a9 8 18~8.!10 Markus Grieder Eleldronische Post im Netz der Ceres n.tJo onE' Arbeitsplatzrechner Romfn' rclk MoU\eS£'1' r/w' u43 Er600 "" Ef'600 3 016 Ac17 3 DO 4 017 ArT8 4 01 "''Ac2 _.1_ 5 018 1.<19 5 02 Ac3 ClKl Cl~1 6 019 Ac20 f--1- 6 OJ ..,. 7 020 1.<21 7 04 Ac5 Mouse .Y.ouse 021 1.<12 05 Ac6 PAL PAL MS..? MYA 2 •9 022 Ac23 M5.4 MXA 2 •9 D6 Ac7 MS3 MYB 11 10 023 Acl.f M5.5 MXB 11 10 07 Ac8 INP 110 15 024 1.<25 INP 110 15 [>8 Ac9 f-4 16 025 1.<26 ~ 16 09 AdO i-lL 17 026 1.<27 r-ll- 17 010 1.<11 ,. 027 1.<28 18 011 1.<12 Hl- __.!1_ !-!?. __.!1_ CU<2 ClK2 ~ M5.1 ~ ~ f-?;fL2 MS6 eo ~ ~ MP.O' 18 011 ArB t\158 2 00 YO Mf:1' 17 A< I< MS.J 3 01 Yl DH Mf:.2' 4 16 014 A<15 M5.9 Yl 02 15 [)15 Ac16 03 Y3 14 [))R Ac29 04 Y4 =t 13 029 AcJO November 1988 05 ¥5 12 1.<31 --+ 06 ¥6 mo 11 1>11 1.<37 ::f 07 Y7 GO' G1' 1 19 IO.RO' m532.cpu6.SII. 94 ETH Zurich Boot- ROM Author: B. Heeb Date: 10.6.88 Mouse - Decoder