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Switch Kenji Yoshigoe University of South Florida University of South Florida Scholar Commons Graduate Theses and Dissertations Graduate School 8-9-2004 Design and Evaluation of the Combined Input and Crossbar Queued (CICQ) Switch Kenji Yoshigoe University of South Florida Follow this and additional works at: https://scholarcommons.usf.edu/etd Part of the American Studies Commons Scholar Commons Citation Yoshigoe, Kenji, "Design and Evaluation of the Combined Input and Crossbar Queued (CICQ) Switch" (2004). Graduate Theses and Dissertations. https://scholarcommons.usf.edu/etd/1313 This Dissertation is brought to you for free and open access by the Graduate School at Scholar Commons. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Scholar Commons. For more information, please contact [email protected]. Design and Evaluation of the Combined Input and Crossbar Queued (CICQ) Switch by Kenji Yoshigoe A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Computer Science and Engineering Department of Computer Science and Engineering College of Engineering University of South Florida Major Professor: Kenneth J. Christensen, Ph.D. Tapas K. Das, Ph.D. Miguel A. Labrador, Ph.D. Rafael A. Perez, Ph.D. Stephen W. Suen, Ph.D. Date of Approval: August 9, 2004 Keywords: Performance Evaluation, Packet switches, Variable-length packets, Stability, Scalability © Copyright 2004, Kenji Yoshigoe Acknowledgements I would like to express my gratitude to my advisor Dr. Kenneth J. Christensen for providing me tremendous opportunities and support. He has opened the door for me to pursue an academic career, and has mentored me to a great extent. I would not have been able to come this far, had I not had his valuable advice throughout my Ph.D. studies. I would like to thank my committee: Dr. Tapas K. Das, Dr. Miguel A. Labrador, Dr. Rafael A. Perez, and Dr. Stephen W. Suen. I would like to acknowledge the National Science Foundation and the Department of Computer Science and Engineering at the University of South Florida for financial support. And last, but not least, I would like to acknowledge my parents. I dedicate this to you since it would not have been possible without your unconditional support. Table of Contents List of Tables.......................................................................................................................v List of Figures ................................................................................................................... vi Glossary of Acronyms...................................................................................................... xii Abstract .............................................................................................................................xv Chapter 1: Introduction .......................................................................................................1 1.1 Background ...............................................................................................................1 1.2 Motivation.................................................................................................................3 1.3 Contributions of this dissertation ..............................................................................5 1.4 Organization of this dissertation ...............................................................................6 Chapter 2: Background on Packet Switching......................................................................8 2.1 Packet switch buffering architectures .......................................................................8 2.2 Output queued switches ............................................................................................9 2.3 Shared-buffer switches............................................................................................10 2.4 Input queued switches.............................................................................................11 2.5 Virtual output queued IQ switches..........................................................................14 2.6 VOQ scheduling algorithms....................................................................................15 2.6.1 Maximum matching .........................................................................................17 2.6.2 Sequential matching algorithms.......................................................................18 2.6.2.1 Wave front arbiter and wrapped wave front arbiter ..................................19 2.6.2.2 Two-dimensional round-robin...................................................................21 2.6.3 Parallel matching algorithms............................................................................22 2.6.3.1 Parallel iterative matching.........................................................................22 2.6.3.2 Statistical matching ...................................................................................23 2.6.3.3 Weighted PIM ...........................................................................................23 i 2.6.3.4 Round-robin matching...............................................................................24 2.6.3.5 SLIP...........................................................................................................25 2.6.3.6 Iterative SLIP ............................................................................................27 2.6.3.7 FIRM .........................................................................................................27 2.6.3.8 Shakeup techniques...................................................................................28 2.6.3.9 Dual round-robin matching .......................................................................28 2.6.3.10 Load-balancing Birkhoff-von Neumann switch......................................29 2.7 Combined input and output queued switches..........................................................30 2.8 Crossbar queued switches .......................................................................................31 2.9 VOQ CICQ switches...............................................................................................34 Chapter 3: Performance Evaluation of the CICQ Switch .................................................37 3.1 The simulation model..............................................................................................37 3.1.1 Switch model....................................................................................................37 3.1.2 Stopping criteria...............................................................................................40 3.2 Traffic models for evaluating the CICQ switch......................................................41 3.2.1 Bernoulli and Interrupted Bernoulli Process arrival processes ........................41 3.2.2 USF synthetic traffic ........................................................................................43 3.3 Simulation experiments...........................................................................................44 3.4 Experiment results...................................................................................................45 Chapter 4: Eliminating Instability in IQ and CICQ Switches...........................................51 4.1 Unstable regions in VOQ switches .........................................................................51 4.2 An Erlang space model for unstable region ............................................................54 4.3 The new burst stabilization protocol.......................................................................55 4.4 Simulation evaluation of burst stabilization protocol .............................................56 4.5 An analytical model of burst stabilization ..............................................................60 4.5.1 Vacating server approximation ........................................................................62 4.5.2 Port 2 analysis ..................................................................................................64 4.5.3 Port 1 analysis ..................................................................................................65 4.5.4 Bounds on BURST............................................................................................67 4.5.5 Numerical results..............................................................................................68 ii Chapter 5: Switching Variable-Length Packets ................................................................70 5.1 Packet-to-cell segmentation schemes in IQ switches..............................................70 5.1.1 Models of quantized service time queues ........................................................72 5.1.1.1 Ceiling of well known distributions..........................................................72 5.1.1.2 M/G/1 analysis ..........................................................................................74 5.1.1.3 Application of models to packet-to-cell segmenting.................................75 5.1.2 Simulation of iSLIP with packet segmentation................................................77 5.1.2.1 Traffic model.............................................................................................77 5.1.2.2 Simulation experiments.............................................................................78 5.1.2.3 Experiment results.....................................................................................79
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