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Scalable Multi-Module Packet Switches with Quality of Service

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Scalable Multi-Module Packet Switches with Quality of Service Scalable Multi-module Packet Switches with Quality of Service Santosh Krishnan Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Graduate School of Arts and Sciences COLUMBIA UNIVERSITY 2006 c 2006 Santosh Krishnan All Rights Reserved ABSTRACT Scalable Multi-module Packet Switches with Quality of Service Santosh Krishnan The rapid growth in packet-based network traffic has resulted in a growing demand for network switches that can scale in capacity with increasing interface transmission rates and higher port counts. Furthermore, the continuing migration of legacy circuit-switched services to a shared IP/MPLS packet-based network requires such network switches to provide an adequate Quality of Service (QoS) in terms of traffic prioritization, as well as bandwidth and delay guarantees. While technology advances, such as the usage of faster silicon and optical switching components, pro- vide one dimension to address this demand, architectural improvements provide the other. This dissertation addresses the latter topic. Specifically, we address the subject of constructing and analyzing high-capacity QoS-capable packet switches using multiple lower-capacity modules. Switches with the output-queueing (OQ) discipline, in theory, provide the best perfor- mance in terms of throughput as well as QoS, but do not scale in capacity with increasing rates and port counts. Input-queued (IQ) switches, on the other hand, scale better but require complex arbitration procedures, sometimes impractical, to achieve the same level of performance. We leverage the state-of-the-art in OQ and IQ switching systems and establish a new taxonomy for a class of three-stage packet switches, which we call Buffered Clos Switches. The taxonomy is cre- ated by augmenting existing switching elements with aggregation, pipelining and parallelization techniques. This offers a switch designer several alternatives, each driven by specific design and re-use constraints, to build a high-capacity switch composed of lower-capacity basic elements. We also present a formal framework for optimal packet-switching performance, in order to uniformly characterize the capabilities of the switches in the class. The optimality is based on establishing functional equivalence of a given switch and its associated arbitration algorithms with a well-understood ideal switch. For the items in the above taxonomy, we demonstrate how some existing algorithms perform with respect to the optimality criteria, and then augment the state-of-the-art by presenting algorithms and analytical results for stricter equivalence with an ideal switch. Contents List of Figures v List of Tables ix Preface xi Chapter 1 Introduction 1 1.1 Motivation . 3 1.2 Contributions . 6 1.2.1 Applicability and Scope . 7 1.3 Organization . 9 Chapter 2 Switching Model 11 2.1 Switching Basics: Overview . 11 2.1.1 Circuits: Blocking . 11 2.1.2 Packets: QoS and Throughput . 13 2.2 Notions of Optimal Performance . 14 2.3 Forwarding Models . 18 2.4 Building Blocks . 21 2.5 Common Existing Switches . 26 Chapter 3 Formal Methods in Switching 30 3.1 Clos Network . 30 i 3.2 Matching Algorithms for Input-Queued Switches . 34 3.2.1 Switch Control Loop . 35 3.2.2 General Matching Techniques . 37 3.2.3 Deterministic Properties . 42 3.2.4 Stochastic Stability . 48 3.2.5 Work Conservation and Exact Emulation . 55 3.2.6 Low-complexity Matchings . 58 3.3 Throughput and QoS in Packet Switching . 63 3.3.1 Integrated Matchings . 63 3.3.2 Hierarchical Switch Scheduling . 65 3.3.3 Memory Element QoS . 68 3.4 Summary . 73 Chapter 4 Buffered Clos Switches: A Framework 75 4.1 BCS Taxonomy . 75 4.1.1 Multi-module Architecture . 78 4.1.2 Feasible Implementations . 81 4.2 Functional Equivalence . 88 4.2.1 Levels of Emulation . 89 4.2.2 Meaning of Equivalence . 91 4.2.3 Existing Results . 96 4.3 Summary . 97 Chapter 5 Combined Input-Output Queueing 98 5.1 Maximal Matching: Application to QoS . 99 5.1.1 Clos Networks: Space-Time Duality . 101 5.1.2 Packet-switching Equivalent . 104 5.1.3 Bandwidth and Delay Guarantees . 105 5.2 Critical Matching Algorithms . 109 5.2.1 Deterministic Properties . 110 ii 5.2.2 Stability without Speedup . 115 5.3 Uniform Traffic: Sub-maximal Perfect Sequence . 121 5.3.1 SPS Matching . 122 5.3.2 Online Variants . 124 5.4 Maximal Matching for Inadmissible Traffic . 126 5.4.1 Bounded Arrivals and Statistical Multiplexing . 127 5.4.2 Matching on Pruned Requests . 130 5.4.3 Stochastic Stability . 132 5.5 Strict Relative Stability . 135 5.5.1 Shortest Output-Queue First . 139 5.5.2 Alternative Approaches . 145 5.6 Putting it Together: Switched Fair-Airport Policies . 147 5.6.1 Multi-phase Combination . 148 5.6.2 Exclusive Combination . 150 5.7 Extensions to Multicast Traffic . 152 5.8 Summary . 155 Chapter 6 CIOQ: Aggregation and Pipelining 157 6.1 Aggregation . 158 6.1.1 Queueing Strategies . 159 6.1.2 Shadowing a CIOQ . 162 6.1.3 Low-complexity Matchings . 170 6.2 Spatial Pipelining . 183 6.2.1 Shadowing a CIOQ . 185 6.2.2 Concurrent Dispatch . 188 6.2.3 Balanced Matchings . 196 6.3 General MSM Switches . 206 6.3.1 Shadowing Approaches . 211 6.3.2 Matching on Virtual Element Queues . 215 6.3.3 Recursive G-MSM . 218 iii 6.4 Summary and Discussion . 221 6.4.1 Related Work . 224 Chapter 7 Parallel Packet Switches 226 7.1 Switch Architecture . 227 7.1.1 Benefits . 230 7.1.2 Queueing Strategies . 232 7.2 Flow-based PPS . 238 7.3 Cell-based PPS . 246 7.3.1 Envelope Striping . 248 7.3.2 Equal Dispatch . 253 7.3.3 Fractional Dispatch . 261 7.3.4 Related Work . 263 7.4 Sequence Control . 265 7.4.1 Simulation Results . 269 7.5 Summary and Discussion . 271 7.5.1 Alternative Multi-path Architectures . 273 Chapter 8 Conclusions 276 8.1 Summary of Contributions . 277 8.2 Topics for Further Research . 280 Bibliography 284 iv List of Figures 2.1 Forwarding models: (a) Centralized CPU, (b) Cut-through . 18 2.2 Pipeline of a cut-through forwarding path . 20 2.3 Forwarding elements: (a) memory element, (b) space element . 22 2.4 Memory element implementation example: Knockout configuration . 25 2.5 Common existing switching models: (a) Output-queued, (b) Input-queued . 27 2.6 A combined input-output queueing switch (CIOQ) . 28 3.1 An N × N Clos network . 31 3.2 Example of Slepian-Duguid-based circuit re-arrangement . 34 3.3 Control loop for an input-queued switch . 36 3.4 Maximum Size Matching using an equivalent flow network . 39 3.5 Maximum Size Matching versus Critical Matching . 40 3.6 Bandwidth and delay guarantees: Exact 100% throughput versus templates . 44 3.7 Fluid limits: Steps in analyzing queue stability . 50 3.8 Lowest Output Occupancy First: A maximal matching . 55 3.9 EREW Maximal Matching: A distributed implementation . 59 3.10 Parallel Iterative Matching: Example of an RGA algorithm . 60 3.11 Assembling large envelopes for low-frequency matchings . 62 3.12 A decision chart to select matchings based on requirements . 64 3.13 Throughput and QoS for input-queued switches using distributed scheduling . 66 3.14 GPS: Delays and backlog for a single flow . ..
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