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High Performance Queueing and Scheduling in Support of Multicasting in Input-Queued Switches

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High Performance Queueing and Scheduling in Support of Multicasting in Input-Queued Switches Old Dominion University ODU Digital Commons Electrical & Computer Engineering Theses & Dissertations Electrical & Computer Engineering Summer 2006 High Performance Queueing and Scheduling in Support of Multicasting in Input-Queued Switches Weiying Zhu Old Dominion University Follow this and additional works at: https://digitalcommons.odu.edu/ece_etds Part of the Computer Engineering Commons, and the Electrical and Computer Engineering Commons Recommended Citation Zhu, Weiying. "High Performance Queueing and Scheduling in Support of Multicasting in Input-Queued Switches" (2006). Doctor of Philosophy (PhD), Dissertation, Electrical & Computer Engineering, Old Dominion University, DOI: 10.25777/3hyz-5p33 https://digitalcommons.odu.edu/ece_etds/148 This Dissertation is brought to you for free and open access by the Electrical & Computer Engineering at ODU Digital Commons. It has been accepted for inclusion in Electrical & Computer Engineering Theses & Dissertations by an authorized administrator of ODU Digital Commons. For more information, please contact [email protected]. HIGH PERFORMANCE QUEUEING AND SCHEDULING IN SUPPORT OF MULTICASTING IN INPUT-QUEUED SWITCHES by Weiying Zhu B.S. July 1996, Xi’an Jiaotong University M.S. June 1999, Huazhong University of Science and Technology A Dissertation Submitted to the Faculty of Old Dominion University in Partial Fulfillment of the Requirement for the Degree of DOCTOR OF PHILOSOPHY ELECTRICAL AND COMPUTER ENGINEERING OLD DOMINION UNIVERSITY August 2006 Approved by: Min Song (Director) James FL Leathrum, Jr. (Member) Hussein Abdel-Wahab (Member) Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. ABSTRACT HIGH PERFORMANCE QUEUEING AND SCHEDULING IN SUPPORT OF MULTICASTING IN INPUT-QUEUED SWITCHES Weiying Zhu Old Dominion University, 2006 Director: Dr. Min Song Due to its mild requirement on the bandwidth of switching fabric and internal memory, the input-queued architecture is a practical solution for today’s very high-speed switches. One of the notoriously difficult problems in the design of input-queued switches with very high link rates is the high performance queueing and scheduling of multicast traffic. This dissertation focuses on proposing novel solutions for this problem. The design challenge stems from the nature of multicast traffic, i.e., a multicast packet typically has multiple destinations. On the one hand, this nature makes queueing and scheduling of multicast traffic much more difficult than that of unicast traffic. For example, virtual output queueing is widely used to completely avoid the head-of-line blocking and achieve 100% throughput for unicast traffic. Nevertheless, the exhaustive multicast virtual output queueing is impractical and results in out-of-order delivery. On the other hand, in spite of extensive studies in the context of either pure unicast traffic or pure multicast traffic, the results from a study in one context are not applicable to the other context due to the difference between the natures of unicast and multicast traffic. The design of integrated scheduling for both types of traffic remains an open issue. The main contribution of this dissertation is twofold: firstly, the performance of an interesting approach to efficiently mitigate head-of-line blocking for multicast traffic is theoretically analyzed; secondly, two novel algorithms are proposed to efficiently integrate unicast and multicast scheduling within one switching fabric. The research work presented in this dissertation concludes that (1) a small number of queues are sufficient to maximize the saturation throughput and delay performances of a large multicast switch with multiple first-in-first-out queues per input port; (2) the theoretical analysis results are indeed valid for practical large-sized switches; (3) for a Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. largeMx N multicast switch, the final achievable saturation throughput decreases as the ratio of MIN decreases; (4) and the two proposed integration algorithms exhibit promising performances in terms of saturation throughput, delay, and packet loss ratio under both uniform Bernoulli and uniform bursty traffic. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. To my parents, Yisheng and Suzhen, my husband, Chuan, and my daughter, Catherine. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. V ACKNOWLEDGMENTS I would like to express my gratitude to the many people who helped make this dissertation possible. In particular, I would like to thank: - my advisor, Dr. Min Song, for his guidance, enthusiasm and unfailing support, - the other members of my dissertation committee, Dr. Hussein Abdel-Wahab, Dr. K. Vijayan Asari, and Dr. James Leathrum, for many helpful comments on this dissertation and full support to my research work, - Dr. Steven Gray for his invaluable instructions and suggestions on both mathematics and career, - current and previous members of Networking Research Lab for many stimulating discussions and their friendship, and - all my friends and colleagues in the department of Electrical and Computer Engineering who made my time here become such a good memory. Last but not the least, I would like to thank my parents, my brother, and my husband for their love and support throughout all these years, and my little daughter for the great happiness brought by her charming smile and laugh. I would also like to acknowledge the financial support I received from the department of Electrical and Computer Engineering and Old Dominion University. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. TABLE OF CONTENTS Page LIST OF TABLES........................................................................................................................... viii LIST OF FIGURES.................................................................................................................ix CHAPTERS I Introduction ..........................................................................................................................1 1.1 Background and Motivation ............................................................................... 1 1.2 Performance Metrics for Input-Queued Switches ............................................. 3 1.3 Problem Statement ...............................................................................................5 1.4 Dissertation Outline .............................................................................................5 II Related Work ...................................................................................................................... 7 2.1 VOQ and Schedulers for VOQ-Based Unicast Switches .................................7 2.2 Mitigating HOL Blocking for Multicast Traffic in Input-Queued Switches ............................................................................................................. 10 2.3 Queueing and Scheduling in Input-Queued Switches for Hybrid Traffic ....13 III Performance Analysis of Large Multicast Switches with Multiple Queues per Input Port under Non-Gathered Traffic ......................................................................... 16 3.1 Switch Architecture under Non-Gathered Traffic: an N x N Switch ............. 16 3.2 Modeling for an N x N Switch .......................................................................... 17 3.2.1 Initial Model ....................................................................................... 18 3.2.2 Modified Model .................................................................................19 3.3 Saturation Throughput Analysis for an N xN Switch .....................................19 3.3.1 Scheduling in the First Round ..........................................................20 3.3.2 Scheduling in the Second Round .................................................... 21 3.3.3 Scheduling in the k-th Round ...........................................................23 3.4 Delay Analysis for an N x N Switch ...............................................................27 3.5 Numerical Results of Theoretical Analysis and Simulations .......................28 3.5.1 Verification to Analytical Results via Simulations .........................29 3.5.2 Performance Improvement Gained by Adding More Queues .......33 3.6 Summary............................................................................................................. 37 IV Performance Analysis of Large Multicast Switches with Multiple Queues per Input Port under Gathered Traffic ..................................................................................38 4.1 Generalization to an M x N Switch: Switch Architecture and Modeling 39 4.2 Availability of an Input Port in the k-th Round ...............................................40 4.3 Saturation Throughput Analysis for an M x N Switch ................................... 44 4.3.1 Scheduling in the First Round ..........................................................44 4.3.2 Scheduling in the k-th Round ...........................................................44 4.4 Delay Analysis for an M x N Switch ..............................................................46 4.5 Numerical Results of Theoretical Analysis and Simulations .......................48 Reproduced with permission of the copyright
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