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(Emips), the RECONFIGURABLE MICROPROCESSOR EXTENSIBLEMICROPROCESSORWITHOUTINTERLOCKED PIPELINESTAGES(eMIPS), THERECONFIGURABLEMICROPROCESSOR AThesis by RICHARDNEILPITTMAN SubmittedtotheOfficeofGraduateStudiesof TexasA&MUniversity inpartialfulfillmentoftherequirementsforthedegreeof MASTEROFSCIENCE May2007 MajorSubject:ComputerEngineering EXTENSIBLEMICROPROCESSORWITHOUTINTERLOCKED PIPELINESTAGES(eMIPS), THERECONFIGURABLEMICROPROCESSOR AThesis by RICHARDNEILPITTMAN SubmittedtotheOfficeofGraduateStudiesof TexasA&MUniversity inpartialfulfillmentoftherequirementsforthedegreeof MASTEROFSCIENCE Approvedby: ChairofCommittee, Jyh-CharnLiu CommitteeMembers, DuncanM.Walker NormanGuinasso HeadofDepartment, ValerieE.Taylor May2007 MajorSubject:ComputerEngineering iii ABSTRACT ExtensibleMicroprocessorwithoutInterlockedPipelineStages (eMIPS),theReconfigurableProcessor.(May2007) RichardNeilPittman,B.S.,TexasA&MUniversity ChairofAdvisoryCommittee:Dr.Jyh-CharnLiu In this thesis we propose to realize the performance benefits of application- specific hardware optimizations in a general-purpose, multi-user system environment using a dynamically extensible microprocessor architecture. We have called our dynamically extensible microprocessor design the Extensible Microprocessor without InterlockedPipelineStages,oreMIPS. The eMIPS architecture uses the interaction of fixedand configurable logic availableinmodernFieldProgrammableGateArray(FPGA).Thisinteractionisusedto address the limitations of current microprocessor architectures based solely on ApplicationSpecificIntegratedCircuits(ASIC).Theselimitationsincludeinflexibility, size, and application specific performance optimization. The eMIPS system allows multiplesecureextensionstoloaddynamicallyandtoplugintothestagesofapipelined centralprocessingunit(CPU)datapath,therebyextendingthecoreinstructionsetofthe microprocessor.Extensionscanalsobeusedtorealizeon-chipperipherals,andifarea permits, even multiple cores. Extension instructions reduce dramatically the execution time of frequently executed instruction patterns. These new functionalities we have iv developedcanbeexploitedbypatchingthebinariesofexistingapplications,withoutany changestothecompilers. A FPGA based workstation prototype and a flexible simulation system implementatingthisdesigndemonstratesspeedupsof2x-3xonasetofapplicationsthat includevideogames,real-timeprogramsandtheSPEC2000integerbenchmarks.eMIPS is the first realized workstation based entirely on a dynamically extensible microprocessorthatissafeforgeneralpurpose,multi-userapplications.Byexposingthe individualstagesofthedatapath,eMIPSallowsoptimizationsnotpreviouslypossible. Thisincludespermittingsafeandcoherentaccessestomemoryfromwithinanextension, optimizingmulti-branchedblocks,andthrowingpreciseandrestartableexceptionsfrom withinanextension. Thisworkdescribesasimplifiedimplementationofanextensiblemicroprocessor architecture based on the Microprocessor without Interlocked Pipeline Stages (MIPS) Reduced Instruction Set Computer (RISC) architecture. The concepts and methods contained within this thesis may be applied to other similar architectures. Given this simplifiedprototypewelookforwardtoproposehowthisarchitecturewillbeexpanded asitmatures. v DEDICATION Tomywife vi ACKNOWLEDGEMENTS I would like to thank my committee chair, Dr. Jyh-Charn (Steve) Liu, for his guidanceandsupportthroughoutthecourseofthisresearchandmyyearsinthegraduate program. I would also like to thank my committee, Dr. Duncan M. Walker and Dr. NormanGuinasso,fortheirhelpwiththiswork. Thank you to my friends, colleagues, faculty and staff of the Department of ComputerScienceatTexasA&MUniversityformakingthelasteightyearsofmylife somemorable.IhopethatIgavebackatleasthalfofwhatIreceivedinmyinteractions withallofyou. I would also like to extend my gratitude to Alessandro Forin of Microsoft Researchwhoprovidedtremendoussupportateverystageofthisresearchproject.The tools and previous work I had the privilege to build upon, allowed me to explore a problemthatmighthavebeenoverwhelmingotherwise. Finally,thankyoutomyfamilyfortheirsupportthroughitall.Thankyoutomy wifeforshowingmethatsometimeswhenyougetstuck,youtotakeafewstepsback. Thankyoutomymotherforalwaysbelievinginme.Thankyoutomybrotherandsister for supporting me as only they can. Thank you to my grandmother for always being therewhenIneedtosomeonetotalkto.Thankyoutomyin-lawsfortheiremotional supportformywifeandme. vii NOMENCLATURE ALU ArithmeticLogicUnit API ApplicationProgramInterface ASIC ApplicationSpecificIntegratedCircuit CAM ContentAddressableMemory CPU CentralProcessingUnit DPS DigitalSignalProcessor eMIPS ExtensibleMIPS GUI GraphicUserInterface FPGA FieldProgrammableGateArray FPU FloatingPointUnit HDL HardwareDescriptionLanguage IC IntegratedCircuit ID InstructionDecode IDE IntegratedDriveElectronics IE InstructionExecute IF InstructionFetch ISA InstructionSetArchitecture JTAG JointTestActionGroup LUT Look-upTable MA MemoryAccess viii MIC MicrosoftInvisibleComputing MIPS MicroprocessorwithoutInterlockedPipelineStages MMU MemoryManagementUnit OS OperatingSystem PC ProgramCounter PIO ParrallelInput/OutputInterface PLI ProgrammingLanguageInterface RAM RandomAccessMemory RI ReservedInstruction RISC ReducedInstructionSetComputer SRAM StaticRandomAccessMemory SystemACE SystemAdvancedConfigurationEnvironment TBUF TristateBuffer TISA TrustedInstructionSetArchitecture USART UniversalSerialSynchronousAsynchronousReceiverTransmitter VHDL VeryHighSpeedIntegratedCircuitHardwareDescription Language WB Writeback ix TABLEOFCONTENTS PAGE ABSTRACT ..................................................................................................................... iii DEDICATION................................................................................................................... v ACKNOWLEDGEMENTS.............................................................................................. vi NOMENCLATURE ........................................................................................................ vii TABLEOFCONTENTS ................................................................................................. ix LISTOFFIGURES .......................................................................................................... xi 1 INTRODUCTION..................................................................................................... 1 2 BACKGROUND....................................................................................................... 5 2.1 ShortcomingsofModernASICS....................................................................... 5 2.2 MIPSInstructionSet ....................................................................................... 10 2.3 FPGAArchitecture .......................................................................................... 12 2.3.1 PartialReconfigurationofXilinxFPGA................................................. 16 2.3.2 SystemACECompactFlashSolution..................................................... 23 2.3.3 eMIPSandtheFPGA .............................................................................. 25 2.4 ProfilingandIdentificationofBasicBlocks ................................................... 27 3 DYNAMICALLYEXTENSIBLEPROCESSORS ................................................ 33 3.1 The‘Classic’RISCCPU ................................................................................. 33 3.2 TheeMIPSArchitecture.................................................................................. 36 3.3 ExecutionDataPaths:MIPSvs.eMIPS.......................................................... 39 3.4 TheeMIPSWorkstation .................................................................................. 41 4 IMPLEMENTATION ............................................................................................. 47 4.1 Challenges ....................................................................................................... 48 4.1.1 Scaling ..................................................................................................... 48 4.1.2 AreaChallenges....................................................................................... 50 4.1.3 PipelineIssues ......................................................................................... 52 4.1.4 ExceptionProcessing............................................................................... 56 x PAGE 4.2 eMIPSSystemComponents ............................................................................ 57 4.2.1 PipelineDataPath ................................................................................... 58 4.2.2 Bootloader ............................................................................................... 59 4.2.3 Extensions................................................................................................ 60 4.2.4 PipelineArbiter........................................................................................ 67 4.2.5 MemoryMapandPeripherals ................................................................. 69 5 TESTINGANDVERIFICATION.......................................................................... 75 6 RESULTS................................................................................................................ 83 7 FUTUREOFeMIPS ............................................................................................... 88 7.1 CAMBasedDecoding....................................................................................
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