Computability and Computation Chris Lomont Jun 22,2012 What Is Computability?
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Global Properties of the Turing Degrees and the Turing Jump
Global Properties of the Turing Degrees and the Turing Jump Theodore A. Slaman¤ Department of Mathematics University of California, Berkeley Berkeley, CA 94720-3840, USA [email protected] Abstract We present a summary of the lectures delivered to the Institute for Mathematical Sci- ences, Singapore, during the 2005 Summer School in Mathematical Logic. The lectures covered topics on the global structure of the Turing degrees D, the countability of its automorphism group, and the definability of the Turing jump within D. 1 Introduction This note summarizes the tutorial delivered to the Institute for Mathematical Sciences, Singapore, during the 2005 Summer School in Mathematical Logic on the structure of the Turing degrees. The tutorial gave a survey on the global structure of the Turing degrees D, the countability of its automorphism group, and the definability of the Turing jump within D. There is a glaring open problem in this area: Is there a nontrivial automorphism of the Turing degrees? Though such an automorphism was announced in Cooper (1999), the construction given in that paper is yet to be independently verified. In this pa- per, we regard the problem as not yet solved. The Slaman-Woodin Bi-interpretability Conjecture 5.10, which still seems plausible, is that there is no such automorphism. Interestingly, we can assemble a considerable amount of information about Aut(D), the automorphism group of D, without knowing whether it is trivial. For example, we can prove that it is countable and every element is arithmetically definable. Further, restrictions on Aut(D) lead us to interesting conclusions concerning definability in D. -
PERL – a Register-Less Processor
PERL { A Register-Less Processor A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by P. Suresh to the Department of Computer Science & Engineering Indian Institute of Technology, Kanpur February, 2004 Certificate Certified that the work contained in the thesis entitled \PERL { A Register-Less Processor", by Mr.P. Suresh, has been carried out under my supervision and that this work has not been submitted elsewhere for a degree. (Dr. Rajat Moona) Professor, Department of Computer Science & Engineering, Indian Institute of Technology, Kanpur. February, 2004 ii Synopsis Computer architecture designs are influenced historically by three factors: market (users), software and hardware methods, and technology. Advances in fabrication technology are the most dominant factor among them. The performance of a proces- sor is defined by a judicious blend of processor architecture, efficient compiler tech- nology, and effective VLSI implementation. The choices for each of these strongly depend on the technology available for the others. Significant gains in the perfor- mance of processors are made due to the ever-improving fabrication technology that made it possible to incorporate architectural novelties such as pipelining, multiple instruction issue, on-chip caches, registers, branch prediction, etc. To supplement these architectural novelties, suitable compiler techniques extract performance by instruction scheduling, code and data placement and other optimizations. The performance of a computer system is directly related to the time it takes to execute programs, usually known as execution time. The expression for execution time (T), is expressed as a product of the number of instructions executed (N), the average number of machine cycles needed to execute one instruction (Cycles Per Instruction or CPI), and the clock cycle time (), as given in equation 1. -
Annals of Pure and Applied Logic Extending and Interpreting
View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Elsevier - Publisher Connector Annals of Pure and Applied Logic 161 (2010) 775–788 Contents lists available at ScienceDirect Annals of Pure and Applied Logic journal homepage: www.elsevier.com/locate/apal Extending and interpreting Post's programmeI S. Barry Cooper Department of Pure Mathematics, University of Leeds, Leeds LS2 9JT, UK article info a b s t r a c t Article history: Computability theory concerns information with a causal – typically algorithmic – Available online 3 July 2009 structure. As such, it provides a schematic analysis of many naturally occurring situations. Emil Post was the first to focus on the close relationship between information, coded as MSC: real numbers, and its algorithmic infrastructure. Having characterised the close connection 03-02 between the quantifier type of a real and the Turing jump operation, he looked for more 03A05 03D25 subtle ways in which information entails a particular causal context. Specifically, he wanted 03D80 to find simple relations on reals which produced richness of local computability-theoretic structure. To this extent, he was not just interested in causal structure as an abstraction, Keywords: but in the way in which this structure emerges in natural contexts. Post's programme was Computability the genesis of a more far reaching research project. Post's programme In this article we will firstly review the history of Post's programme, and look at two Ershov hierarchy Randomness interesting developments of Post's approach. The first of these developments concerns Turing invariance the extension of the core programme, initially restricted to the Turing structure of the computably enumerable sets of natural numbers, to the Ershov hierarchy of sets. -
Computer Architecture Basics
V03: Computer Architecture Basics Prof. Dr. Anton Gunzinger Supercomputing Systems AG Technoparkstrasse 1 8005 Zürich Telefon: 043 – 456 16 00 Email: [email protected] Web: www.scs.ch Supercomputing Systems AG Phone +41 43 456 16 00 Technopark 1 Fax +41 43 456 16 10 8005 Zürich www.scs.ch Computer Architecture Basic 1. Basic Computer Architecture Diagram 2. Basic Computer Architectures 3. Von Neumann versus Harvard Architecture 4. Computer Performance Measurement 5. Technology Trends 2 Zürich 20.09.2019 © by Supercomputing Systems AG CONFIDENTIAL 1.1 Basic Computer Architecture Diagram Sketch the basic computer architecture diagram Describe the functions of the building blocks 3 Zürich 20.09.2019 © by Supercomputing Systems AG CONFIDENTIAL 1.2 Basic Computer Architecture Diagram Describe the execution of a single instruction 5 Zürich 20.09.2019 © by Supercomputing Systems AG CONFIDENTIAL 2 Basic Computer Architecture 2.1 Sketch an Accumulator Machine 2.2 Sketch a Register Machine 2.3 Sketch a Stack Machine 2.4 Sketch the analysis of computing expression in a Stack Machine 2.5 Write the micro program for an Accumulator, a Register and a Stack Machine for the instruction: C:= A + B and estimate the numbers of cycles 2.6 Write the micro program for an Accumulator, a Register and a Stack Machine for the instruction: C:= (A - B)2 + C and estimate the numbers of cycles 2.7 Compare Accumulator, Register and Stack Machine 7 Zürich 20.09.2019 © by Supercomputing Systems AG CONFIDENTIAL 2.1 Accumulator Machine Draw the Accumulator Machine 8 Zürich -
Computers, Complexity, and Controversy
Instruction Sets and Beyond: Computers, Complexity, and Controversy Robert P. Colwell, Charles Y. Hitchcock m, E. Douglas Jensen, H. M. Brinkley Sprunt, and Charles P. Kollar Carnegie-Mellon University t alanc o tyreceived Instruction set design is important, but lt1Mthi it should not be driven solely by adher- ence to convictions about design style, ,,tl ica' ch m e n RISC or CISC. The focus ofdiscussion o09 Fy ipt issues. RISC should be on the more general question of the assignment of system function- have guided ality to implementation levels within years. A study of an architecture. This point of view en- d yield a deeper un- compasses the instruction set-CISCs f hardware/software tend to install functionality at lower mputer performance, the system levels than RISCs-but also JOCUS on rne assignment iluence of VLSI on processor design, takes into account other design fea- ofsystem functionality to and many other topics. Articles on tures such as register sets, coproces- RISC research, however, often fail to sors, and caches. implementation levels explore these topics properly and can While the implications of RISC re- within an architecture, be misleading. Further, the few papers search extend beyond the instruction and not be guided by that present comparisons with com- set, even within the instruction set do- whether it is a RISC plex instruction set computer design main, there are limitations that have or CISC design. often do not address the same issues. not been identified. Typical RISC As a result, even careful study of the papers give few clues about where the literature is likely to give a distorted RISC approach might break down. -
THERE IS NO DEGREE INVARIANT HALF-JUMP a Striking
PROCEEDINGS OF THE AMERICAN MATHEMATICAL SOCIETY Volume 125, Number 10, October 1997, Pages 3033{3037 S 0002-9939(97)03915-4 THERE IS NO DEGREE INVARIANT HALF-JUMP RODNEY G. DOWNEY AND RICHARD A. SHORE (Communicated by Andreas R. Blass) Abstract. We prove that there is no degree invariant solution to Post's prob- lem that always gives an intermediate degree. In fact, assuming definable de- terminacy, if W is any definable operator on degrees such that a <W (a) < a0 on a cone then W is low2 or high2 on a cone of degrees, i.e., there is a degree c such that W (a)00 = a for every a c or W (a)00 = a for every a c. 00 ≥ 000 ≥ A striking phenomenon in the early days of computability theory was that every decision problem for axiomatizable theories turned out to be either decidable or of the same Turing degree as the halting problem (00,thecomplete computably enumerable set). Perhaps the most influential problem in computability theory over the past fifty years has been Post’s problem [10] of finding an exception to this rule, i.e. a noncomputable incomplete computably enumerable degree. The problem has been solved many times in various settings and disguises but the so- lutions always involve specific constructions of strange sets, usually by the priority method that was first developed (Friedberg [2] and Muchnik [9]) to solve this prob- lem. No natural decision problems or sets of any kind have been found that are neither computable nor complete. The question then becomes how to define what characterizes the natural computably enumerable degrees and show that none of them can supply a solution to Post’s problem. -
Uniform Martin's Conjecture, Locally
Uniform Martin's conjecture, locally Vittorio Bard July 23, 2019 Abstract We show that part I of uniform Martin's conjecture follows from a local phenomenon, namely that if a non-constant Turing invariant func- tion goes from the Turing degree x to the Turing degree y, then x ≤T y. Besides improving our knowledge about part I of uniform Martin's con- jecture (which turns out to be equivalent to Turing determinacy), the discovery of such local phenomenon also leads to new results that did not look strictly related to Martin's conjecture before. In particular, we get that computable reducibility ≤c on equivalence relations on N has a very complicated structure, as ≤T is Borel reducible to it. We conclude rais- ing the question Is part II of uniform Martin's conjecture implied by local phenomena, too? and briefly indicating a possible direction. 1 Introduction to Martin's conjecture Providing evidence for the intricacy of the structure (D; ≤T ) of Turing degrees has been arguably one of the main concerns of computability theory since the mid '50s, when the celebrated priority method was discovered. However, some have pointed out that if we restrict our attention to those Turing degrees that correspond to relevant problems occurring in mathematical practice, we see a much simpler structure: such \natural" Turing degrees appear to be well- ordered by ≤T , and there seems to be no \natural" Turing degree strictly be- tween a \natural" Turing degree and its Turing jump. Martin's conjecture is a long-standing open problem whose aim was to provide a precise mathemat- ical formalization of the previous insight. -
Independence Results on the Global Structure of the Turing Degrees by Marcia J
TRANSACTIONS OF THE AMERICAN MATHEMATICAL SOCIETY Volume INDEPENDENCE RESULTS ON THE GLOBAL STRUCTURE OF THE TURING DEGREES BY MARCIA J. GROSZEK AND THEODORE A. SLAMAN1 " For nothing worthy proving can be proven, Nor yet disproven." _Tennyson Abstract. From CON(ZFC) we obtain: 1. CON(ZFC + 2" is arbitrarily large + there is a locally finite upper semilattice of size u2 which cannot be embedded into the Turing degrees as an upper semilattice). 2. CON(ZFC + 2" is arbitrarily large + there is a maximal independent set of Turing degrees of size w,). Introduction. Let ^ denote the set of Turing degrees ordered under the usual Turing reducibility, viewed as a partial order ( 6Î),< ) or an upper semilattice (fy, <,V> depending on context. A partial order (A,<) [upper semilattice (A, < , V>] is embeddable into fy (denoted A -* fy) if there is an embedding /: A -» <$so that a < ft if and only if/(a) </(ft) [and/(a) V /(ft) = /(a V ft)]. The structure of ty was first investigted in the germinal paper of Kleene and Post [2] where A -» ty for any countable partial order A was shown. Sacks [9] proved that A -» öDfor any partial order A which is locally finite (any point of A has only finitely many predecessors) and of size at most 2", or locally countable and of size at most u,. Say X C fy is an independent set of Turing degrees if, whenever x0, xx,...,xn E X and x0 < x, V x2 V • • • Vjcn, there is an / between 1 and n so that x0 = x¡; X is maximal if no proper extension of X is independent. -
Sets of Reals with an Application to Minimal Covers Author(S): Leo A
A Basis Result for ∑0 3 Sets of Reals with an Application to Minimal Covers Author(s): Leo A. Harrington and Alexander S. Kechris Source: Proceedings of the American Mathematical Society, Vol. 53, No. 2 (Dec., 1975), pp. 445- 448 Published by: American Mathematical Society Stable URL: http://www.jstor.org/stable/2040033 . Accessed: 22/05/2013 17:17 Your use of the JSTOR archive indicates your acceptance of the Terms & Conditions of Use, available at . http://www.jstor.org/page/info/about/policies/terms.jsp . JSTOR is a not-for-profit service that helps scholars, researchers, and students discover, use, and build upon a wide range of content in a trusted digital archive. We use information technology and tools to increase productivity and facilitate new forms of scholarship. For more information about JSTOR, please contact [email protected]. American Mathematical Society is collaborating with JSTOR to digitize, preserve and extend access to Proceedings of the American Mathematical Society. http://www.jstor.org This content downloaded from 131.215.71.79 on Wed, 22 May 2013 17:17:43 PM All use subject to JSTOR Terms and Conditions PROCEEDINGS OF THE AMERICAN MATHEMATICAL SOCIETY Volume 53, Number 2, December 1975 A BASIS RESULT FOR E3 SETS OF REALS WITH AN APPLICATION TO MINIMALCOVERS LEO A. HARRINGTON AND ALEXANDER S. KECHRIS ABSTRACT. It is shown that every Y3 set of reals which contains reals of arbitrarily high Turing degree in the hyperarithmetic hierarchy contains reals of every Turing degree above the degree of Kleene's 0. As an application it is shown that every Turing degrec above the Turing degree of Kleene's 0 is a minimal cover. -
Algebraic Aspects of the Computably Enumerable Degrees
Proc. Natl. Acad. Sci. USA Vol. 92, pp. 617-621, January 1995 Mathematics Algebraic aspects of the computably enumerable degrees (computability theory/recursive function theory/computably enumerable sets/Turing computability/degrees of unsolvability) THEODORE A. SLAMAN AND ROBERT I. SOARE Department of Mathematics, University of Chicago, Chicago, IL 60637 Communicated by Robert M. Solovay, University of California, Berkeley, CA, July 19, 1994 ABSTRACT A set A of nonnegative integers is computably equivalently represented by the set of Diophantine equations enumerable (c.e.), also called recursively enumerable (r.e.), if with integer coefficients and integer solutions, the word there is a computable method to list its elements. The class of problem for finitely presented groups, and a variety of other sets B which contain the same information as A under Turing unsolvable problems in mathematics and computer science. computability (<T) is the (Turing) degree ofA, and a degree is Friedberg (5) and independently Mucnik (6) solved Post's c.e. if it contains a c.e. set. The extension ofembedding problem problem by producing a noncomputable incomplete c.e. set. for the c.e. degrees Qk = (R, <, 0, 0') asks, given finite partially Their method is now known as the finite injury priority ordered sets P C Q with least and greatest elements, whether method. Restated now for c.e. degrees, the Friedberg-Mucnik every embedding ofP into Rk can be extended to an embedding theorem is the first and easiest extension of embedding result of Q into Rt. Many of the most significant theorems giving an for the well-known partial ordering of the c.e. -
Programmable Digital Microcircuits - a Survey with Examples of Use
- 237 - PROGRAMMABLE DIGITAL MICROCIRCUITS - A SURVEY WITH EXAMPLES OF USE C. Verkerk CERN, Geneva, Switzerland 1. Introduction For most readers the title of these lecture notes will evoke microprocessors. The fixed instruction set microprocessors are however not the only programmable digital mi• crocircuits and, although a number of pages will be dedicated to them, the aim of these notes is also to draw attention to other useful microcircuits. A complete survey of programmable circuits would fill several books and a selection had therefore to be made. The choice has rather been to treat a variety of devices than to give an in- depth treatment of a particular circuit. The selected devices have all found useful ap• plications in high-energy physics, or hold promise for future use. The microprocessor is very young : just over eleven years. An advertisement, an• nouncing a new era of integrated electronics, and which appeared in the November 15, 1971 issue of Electronics News, is generally considered its birth-certificate. The adver• tisement was for the Intel 4004 and its three support chips. The history leading to this announcement merits to be recalled. Intel, then a very young company, was working on the design of a chip-set for a high-performance calculator, for and in collaboration with a Japanese firm, Busicom. One of the Intel engineers found the Busicom design of 9 different chips too complicated and tried to find a more general and programmable solu• tion. His design, the 4004 microprocessor, was finally adapted by Busicom, and after further négociation, Intel acquired marketing rights for its new invention. -
ABSTRACT Virtualizing Register Context
ABSTRACT Virtualizing Register Context by David W. Oehmke Chair: Trevor N. Mudge A processor designer may wish for an implementation to support multiple reg- ister contexts for several reasons: to support multithreading, to reduce context switch overhead, or to reduce procedure call/return overhead by using register windows. Conventional designs require that each active context be present in its entirety, increasing the size of the register file. Unfortunately, larger register files are inherently slower to access and may lead to a slower cycle time or additional cycles of register access latency, either of which reduces overall performance. We seek to bypass the trade-off between multiple context support and register file size by mapping registers to memory, thereby decoupling the logical register requirements of active contexts from the contents of the physical register file. Just as caches and virtual memory allow a processor to give the illusion of numerous multi-gigabyte address spaces with an average access time approach- ing that of several kilobytes of SRAM, we propose an architecture that gives the illusion of numerous active contexts with an average access time approaching that of a single active context using a conventionally sized register file. This dis- sertation introduces the virtual context architecture, a new architecture that virtual- izes logical register contexts. Complete contexts, whether activation records or threads, are kept in memory and are no longer required to reside in their entirety in the physical register file. Instead, the physical register file is treated as a cache of the much larger memory-mapped logical register space. The implementation modifies the rename stage of the pipeline to trigger the movement of register val- ues between the physical register file and the data cache.