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Recent Advances and Outlook for Heterogeneous Integration

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Recent Advances and Outlook for Heterogeneous Integration IEEE/EPS Chapter Lecture Silicon Valley Area (SCV, SF, OEB) Recent Advances and Outlook for Heterogeneous Integration John H Lau Unimicron Technology Corporation [email protected] SEMI World HQ, February 28, 2020 1 This Presentation is supported by the IEEE Electronics Packaging Society’s Distinguished Lecturer Program eps.ieee.org 2 IEEE at a Glance Our Global Reach 423,000+ 46 160+ Members Technical Societies and Countries Councils Our Technical Breadth 1,800+ 4,200,000+ 190+ Annual Conferences Technical Documents Top-cited Periodicals 3 IEEE Electronics Packaging Society (EPS ) A Global Society …With Chapters spanning the world Over 30 Chapters Worldwide …12 Technical Committees Over 2,500 Members Worldwide …Over 25 Conferences and Workshops …Peer Reviewed Publication …Professional Awards & Recognition 35 Local Chapters Bangalore Hungary/Romania Shanghai Beijing Japan Singapore Benelux Korea Switzerland Bulgaria Malaysia Taiwan Canada Nordic (United Kingdom & France (Sweden, Denmark, Republic of Ireland) Germany Finland, Norway, Estonia) Ukraine Hong Kong United States Poland CONTENTS Introduction System-on-Chip (SoC) A10 A11 A12 A13 Heterogeneous Integrations or SiPs (System-in-Packages) Definitions Classifications Heterogeneous Integrations vs. SoC Heterogeneous Integrations on Organic Substrates Heterogeneous Integrations on Silicon Substrates (TSV-Interposers) Heterogeneous Integrations on Silicon Substrates (TSV-less Interposers) Heterogeneous Integrations on Fan-Out RDL Substrates Heterogeneous Integrations on Ceramic Substrates Heterogeneous Integrations Trends Q&A Moore’s Law - Apple’s Application Processors (AP): A10, A11, A12, and A13 A10 A11 A12 A13 A13 consists of: A10 consists of: A11 consists of: A12 consists of: Eight-core Neural 6-core GPU (graphics More functions, e.g., Eight-core Neural Engine with processor unit) 2-core Neural Engine with AI Machine Learning 2 dual-core CPU Engine for Face ID capabilities Four-core GPU (central processing Apple designed tri- Four-core GPU (20% faster > A12) unit) core GPU (faster) Six-core CPU (20% 2 blocks of SRAMs 10nm process Six-core CPU faster and 35% save (static random access technology (better energy > A12) memory), etc. Transistors = 4.3 performance ) 7nm process 16nm process billion 7nm process technology with technology Chip area ~ 89mm2 technology EUV Transistors = 3 billion Transistors = 6.9 Transistors = 8.5 Chip area ~ 125mm2 billion Chip area = 83mm2 billion Chip area ~ 100mm2 (9.26mmx10.8mmm) Definition of Heterogeneous Integration Chip-1 (SiP) FAB-1 7nm Packaged 12”-wafer Heterogeneous memory stack integration or SiP Chip-1 PBGA Time-to-market CPU Memory Less IP issues Chip-2 Stack Flexibility FAB-2 Low cost alternative 64nm Chip-2 3 than SoC 8”-wafer GaAs Optimized signal MEMS Chip- integrity and power Chip-3 Heterogeneous integration uses packaging FAB-3 technology to integrate dissimilar chips, 100nm photonic devices, or components (either side- 6”-wafer by-side, stack, or both) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. Lau, ECTC2016-PDC Heterogeneous Integration vs. Moore’s Law Why Heterogeneous Integration? This is because of the end of the Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration is going to take some of the market shares away from SoC. What are Heterogeneous Integration for? For the next five years, we will see more of a higher level of heterogeneous integration, whether it is for: Time-to-market Performance Form factor Power consumption Cost Lau, ECTC2016-PDC Classification of Heterogeneous Integrations Heterogeneous Integrations on Organic Substrates Heterogeneous Integrations of Silicon Substrates (TSV Interposers) Heterogeneous Integrations on Silicon Substrate (TSV-less Interposers) Heterogeneous Integrations on Fan-Out RDL-Substrates Heterogeneous Integrations on Ceramic Substrates Lau, ECTC2016-PDC Amkor Automotive SiP Heterogeneous Integration on organic-substrate Lau, ECTC2016-PDC The Apple Watch is SiP and was Assembled by ASE (Universal Scientific Industrial – Shanghai) Broadcom BCM15920 Custom Sensing ASIC Apple Application Broadcom BCM59356 Processor with SK Wireless Charging Hynix LPDDR4 SDRAM Power Management Unit Apple 338S00348W2 Chip Toshiba NAND Flash Qualcomm MDM9635M LTE Modem with Samsung K4P1G324EH SDRAM Apple/Dialog PMIC Qualcomm PMD9645 PMIC Heterogeneous Integration on Organic-Substrate Lau, ECTC2019-PDC Three Substrate-Like PCBs in iPhone XS and XS Max 3D Sensors Dual Rear Camera C B A Battery Battery B: Front PCB1 (2-sided assembly) Taptic Speaker Engine A: Rear PCB C: Front PCB2 (1-sided assembly) (2-sided assembly) Lau, ECTC2019-PDC SiP in the Rear PCB of iPhone XS and XS Max 4 C B A 5 4 4 7 [1] Intel Baseband Chipset 8 [2] Intel PM IC 1 2 [3] Intel RF Transceiver [4] Skyworks RF FEM 6 [5] Murata RF FEM (front-end module) [6] USI WiFi/BT Module 4 5 [7] Broadcom Wireless Charger [8] NXP NFC Controller 4 4 3 Rear PCB (A) 8L HDI, 4mSAP layers, 16cm2 Single-Sided Assembly Baseband, RF, WiFi/BT All components face inward Lau, ECTC2019-PDC SiPs in the Front PCB1 and Front PCB2 5 C B 4 A 8 8 1 2 8 [1] Apple A12 Chipset 3 7 6 [2] Flash Memory Front PCB 1 (B) [3] Power Manager 10L HDI, 6 mSAP layers, 10cm2 [4] ST Power Manager Double-Sided Assembly [5] Power Manager A12 CPU, Memory, Connectors A12 CPU faces inward [6] TI Battery Charger [7] Audio Codec [8] Audio Amplification 10 9 [9] Avago RF FEM [10] Skyworks RF FEM Front PCB 2 (C) 6L HDI, 2 mSAP layers, 2cm2 Double-Sided Assembly RF FEM, Connectors RF FEM face inward Lau, ECTC2019-PDC Heterogeneous Integration (Flip Chip) on Organic Substrate (2D IC Integration) 2D IC Integration 2D IC Integration (Top-View) (Bottom-View) Solder Ball Package Substrate Chip1 Chip2 Package Substrate Solder Joint PCB Lau, ECTC2012-PDC Heterogeneous Integration of 4 Chips and 4 Capacitors (Fan-Out) on PCB (2D IC Integration) EMC 3mmx3mm 3mmx3mm PCB Cross Section 3mmx3mm Capacitor EMC 300mm Solder crack 3x3 3x3 Void Chip Chip Cu-Pad VIP PCB 5x5 3x3 Chip Chip EMC Reconstituted Wafer 5mmx5mm5mmx5m EMC5mmx5 m PC mm PCB B Cross Section 5mmx5mm EMC EMC Chip RDL1 Solder crack VC1 RDL2 V12 UBM-less pad Cu-Pad VIP EM PCB Solder Ball C Thermal Cycling Test Results IEEE Trans. CPMT 2018, pp. 1544-1560 Shinko’s i-THOP Substrate for Heterogeneous Integration (2.1D IC Integration) Underfill Microbump CHIP-1 CHIP-2 Thin-film layers Build-up Core layers i-THOP (integrated thin-film high density organic package) Lau, PDC, ECTC2015 Shinko’s i-THOP Substrate φ 25µm-pad 40µm pad-pitch Cu-pad thickness φ 25µm Cu-pad = 11.8µm Line width and spacing = 2µm 2µm Thin-film Φ 10µm Build-up Build-up via = 50µm Core Thin-film Build-up Core Build-up Lau, PDC, ECTC2015 3D SiP with Organic Interposer for ASIC and Memory Integration (2.3D IC Integration) Li Li, Pierre Chia, Paul Ton, Mohan Nagar, Sada Patil, Jie Xue Cisco Systems, Inc. San Jose, CA 95134, U.S.A., e-mail: [email protected] HBM_Functional HBM_Mechanical Interposer . µbump-pillar C4 Bumps Organic Interposer ASIC/FPGA Build-up Substrate Heterogeneous Integration on Organic-Substrate IEEE/ECTC2017 Classification of Heterogeneous Integrations Heterogeneous Integrations on Organic Substrates Heterogeneous Integrations of Silicon Substrates (TSV Interposers) Heterogeneous Integrations on Silicon Substrate (TSV-less interposers) Heterogeneous Integrations on Fan-Out RDL-Substrates Heterogeneous Integrations on Ceramic Substrates Leti’s Heterogeneous Integration: System-on-Wafer (SoW) (2.5D IC Integration) Energy source MEMS ASIC + memories TSV Si Interposer Embedded passives Heterogeneous Integration on Si-substrate (TSMC called this: CoWoS) IEEE/ECTC2006 IME’s Heterogeneous Integration of RF Chip, Logic chip, and Memory chips Logic RF Chip Memory Chip Chips Molding RF Chip Molding Logic Memory PCB Logic RF Chip RF Logic Memory Chip Chip Chips Chips Memory Memory Carrier 1 Carrier 2 IEEE Trans. on CPMT, 2010. ITRI’s 2.5D IC Integration TSV:10μm Stress sensor RDL Mechanical Thermal 100μm TSV:15μm TSV:10μm 50μm TSV:15μm IPD TSV/RDL/IPD 100μm Interposer TSV:15μm RDL ` ` 80μm Ordinary bumps Organic (BT) substrate I/O:400 ball array, pitch:450μm Solder 350μm balls IMAPS Trans. PCB 2011. I/O:400 ball array, pitch:1mm PCB ITRI/Rambus’ Heterogeneous Integration of Chips Ordinary RDL TSV Interposer solder TSV bumps Chip-1 Chip-2 Chip- 3 Organic package substrate Solder balls Underfill TSV Interposer Chip-1 Underfill Chip-2 4-2-4 Substrate Chip-3 Chip-1 Chip-1 Underfill Chip-2 Interposer Interposer Chip-3 4-2-4 substrate IEEE/ECTC2012 Xilinx/TSMC’s 2.5D IC Integration with FPGA Chip Chip TSV-Interposer Metal C4 Bumps Layers Metal PTH Build-up Package Devices Contacts Core Layers Substrate (Cannot see) Si Solder Cu Balls Micro Pillar Bump Solder 4RDLs TSV CoWoS Si-Interposer (chip on wafer on substrate) Homogeneous Integration on Si-substrate RDLs: 0.4μm-pitch line width and spacing Each FPGA has >50,000 μbumps on 45μm pitch Interposer is supporting >200,000 μbumps IEEE/ECTC2013 AMD’s GPU (Fiji), Hynix’s HBM, and UMC’s Interposer 1st DRAM 2nd DRAM 3rd DRAM th HBM HBM 4 DRAM TSV-Interposer TSV Cu GPU C4 HBM HBM 4-2-4 Build-up PTH substrate TSV-Interposer GPU with microbumps Cu-Pillar with solder Cap TSV- TSV TSV Interposer C4 Solder Build-up organic Cu substrate
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