Recent Advances and Outlook for Heterogeneous Integration

IEEE/EPS Chapter Lecture Silicon Valley Area (SCV, SF, OEB)

John H Lau Unimicron Technology Corporation [email protected]

SEMI World HQ, February 28, 2020 1 This Presentation is supported by the IEEE Electronics Packaging Society’s Distinguished Lecturer Program eps.ieee.org

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CONTENTS

Introduction System-on-Chip (SoC) A10 A11 A12 A13 Heterogeneous Integrations or SiPs (System-in-Packages) Definitions Classifications Heterogeneous Integrations vs. SoC Heterogeneous Integrations on Organic Substrates Heterogeneous Integrations on Silicon Substrates (TSV-Interposers) Heterogeneous Integrations on Silicon Substrates (TSV-less Interposers) Heterogeneous Integrations on Fan-Out RDL Substrates Heterogeneous Integrations on Ceramic Substrates Heterogeneous Integrations Trends Q&A

Moore’s Law - Apple’s Application Processors (AP): A10, A11, A12, and A13 A10 A11 A12 A13

A13 consists of: A10 consists of: A11 consists of: A12 consists of:  Eight-core Neural  6-core GPU (graphics  More functions, e.g.,  Eight-core Neural Engine with processor unit) 2-core Neural Engine with AI Machine Learning  2 dual-core CPU Engine for Face ID capabilities  Four-core GPU (central processing  Apple designed tri-  Four-core GPU (20% faster > A12) unit) core GPU (faster)  Six-core CPU (20%  2 blocks of SRAMs  10nm process  Six-core CPU faster and 35% save (static random access technology (better energy > A12) memory), etc.  Transistors = 4.3 performance )  7nm process  16nm process billion  7nm process technology with technology  Chip area ~ 89mm2 technology EUV  Transistors = 3 billion  Transistors = 6.9  Transistors = 8.5  Chip area ~ 125mm2 billion  Chip area = 83mm2 billion  Chip area ~ 100mm2 (9.26mmx10.8mmm) Definition of Heterogeneous Integration

 Chip-1 (SiP)  FAB-1  7nm Packaged  12”-wafer Heterogeneous memory stack integration or SiP

Chip-1 PBGA  Time-to-market CPU Memory  Less IP issues  Chip-2 Stack  Flexibility  FAB-2  Low cost alternative  64nm Chip-2 than SoC  8”-wafer GaAs  Optimized signal MEMS Chip- 3 integrity and power

 Chip-3 Heterogeneous integration uses packaging  FAB-3 technology to integrate dissimilar chips,  100nm photonic devices, or components (either side-  6”-wafer by-side, stack, or both) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. Lau, ECTC2016-PDC Heterogeneous Integration vs. Moore’s Law

Why Heterogeneous Integration? This is because of the end of the Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration is going to take some of the market shares away from SoC.

What are Heterogeneous Integration for? For the next five years, we will see more of a higher level of heterogeneous integration, whether it is for: Time-to-market Performance Form factor Power consumption Cost

Lau, ECTC2016-PDC Classification of Heterogeneous Integrations

 Heterogeneous Integrations on Organic Substrates  Heterogeneous Integrations of Silicon Substrates (TSV Interposers)  Heterogeneous Integrations on Silicon Substrate (TSV-less Interposers)  Heterogeneous Integrations on Fan-Out RDL-Substrates  Heterogeneous Integrations on Ceramic Substrates

Lau, ECTC2016-PDC Amkor Automotive SiP

Heterogeneous Integration on organic-substrate Lau, ECTC2016-PDC The Apple Watch is SiP and was Assembled by ASE (Universal Scientific Industrial – Shanghai)

Broadcom BCM15920 Custom Sensing ASIC Apple Application Broadcom BCM59356 Processor with SK Wireless Charging Hynix LPDDR4 SDRAM Power Management Unit

Apple 338S00348W2 Chip Toshiba NAND Flash

Qualcomm MDM9635M LTE Modem with Samsung K4P1G324EH SDRAM

Apple/Dialog PMIC Qualcomm PMD9645 PMIC Heterogeneous Integration on Organic-Substrate

Lau, ECTC2019-PDC Three Substrate-Like PCBs in iPhone XS and XS Max

3D Sensors Dual Rear Camera C B A

Battery

B: Front PCB1 (2-sided assembly) Taptic Speaker Engine

A: Rear PCB C: Front PCB2 (1-sided assembly) (2-sided assembly) Lau, ECTC2019-PDC SiP in the Rear PCB of iPhone XS and XS Max

4 C B A 5 4 4 7 [1] Intel Baseband Chipset 8 [2] Intel PM IC 1 2 [3] Intel RF Transceiver [4] Skyworks RF FEM 6 [5] Murata RF FEM (front-end module) [6] USI WiFi/BT Module 4 5 [7] Broadcom Wireless Charger [8] NXP NFC Controller

4 4 3

Rear PCB (A)  8L HDI, 4mSAP layers, 16cm2  Single-Sided Assembly  Baseband, RF, WiFi/BT  All components face inward Lau, ECTC2019-PDC SiPs in the Front PCB1 and Front PCB2

5 C B 4 A 8 8 1

2 8 [1] Apple A12 Chipset 3 7 6 [2] Flash Memory Front PCB 1 (B) [3] Power Manager  10L HDI, 6 mSAP layers, 10cm2 [4] ST Power Manager  Double-Sided Assembly [5] Power Manager  A12 CPU, Memory, Connectors  A12 CPU faces inward [6] TI Battery Charger [7] Audio Codec [8] Audio Amplification 10 9 [9] Avago RF FEM [10] Skyworks RF FEM Front PCB 2 (C)  6L HDI, 2 mSAP layers, 2cm2  Double-Sided Assembly  RF FEM, Connectors  RF FEM face inward

Lau, ECTC2019-PDC Heterogeneous Integration (Flip Chip) on Organic Substrate (2D IC Integration)

2D IC Integration 2D IC Integration (Top-View) (Bottom-View)

Solder Ball

Package Substrate Chip1 Chip2

Package Substrate Solder Joint

PCB

Lau, ECTC2012-PDC Heterogeneous Integration of 4 Chips and 4 Capacitors (Fan-Out) on PCB (2D IC Integration)

EMC 3mmx3mm 3mmx3mm

PCB Cross Section 3mmx3mm Capacitor EMC 300mm Solder crack 3x3 3x3 Void Chip Chip Cu-Pad VIP PCB 5x5 3x3 Chip Chip EMC Reconstituted Wafer 5mmx5mm5mmx5m EMC5mmx5 m PC mm PCB B Cross Section 5mmx5mm EMC EMC Chip RDL1 Solder crack VC1 RDL2 V12 UBM-less pad Cu-Pad VIP EM PCB Solder Ball C Thermal Cycling Test Results

IEEE Trans. CPMT 2018, pp. 1544-1560 Shinko’s i-THOP Substrate for Heterogeneous Integration (2.1D IC Integration)

Underfill Microbump CHIP-1 CHIP-2 Thin-film layers

Build-up Core layers

i-THOP (integrated thin-film high density organic package)

Lau, PDC, ECTC2015 Shinko’s i-THOP Substrate

φ 25µm-pad 40µm pad-pitch

Cu-pad thickness φ 25µm Cu-pad = 11.8µm

Line width and spacing = 2µm 2µm

Thin-film Φ 10µm Build-up Build-up via = 50µm Core

Thin-film

Build-up

Core Build-up Lau, PDC, ECTC2015 3D SiP with Organic Interposer for ASIC and Memory Integration (2.3D IC Integration)

Li Li, Pierre Chia, Paul Ton, Mohan Nagar, Sada Patil, Jie Xue Cisco Systems, Inc. San Jose, CA 95134, U.S.A., e-mail: [email protected] HBM_Functional HBM_Mechanical Interposer . µbump-pillar C4 Bumps

Organic Interposer

ASIC/FPGA Build-up Substrate

Heterogeneous Integration on Organic-Substrate IEEE/ECTC2017 Classification of Heterogeneous Integrations

 Heterogeneous Integrations on Organic Substrates  Heterogeneous Integrations of Silicon Substrates (TSV Interposers)  Heterogeneous Integrations on Silicon Substrate (TSV-less interposers)  Heterogeneous Integrations on Fan-Out RDL-Substrates  Heterogeneous Integrations on Ceramic Substrates

Leti’s Heterogeneous Integration: System-on-Wafer (SoW) (2.5D IC Integration)

Energy source MEMS

ASIC + memories TSV Si Interposer

Embedded passives

Heterogeneous Integration on Si-substrate (TSMC called this: CoWoS) IEEE/ECTC2006 IME’s Heterogeneous Integration of RF Chip, Logic chip, and Memory chips

Logic RF Chip Memory Chip Chips Molding RF Chip Molding Logic Memory

PCB

Logic RF Chip

RF Logic Memory Chip Chip Chips Chips Memory Memory

Carrier 1 Carrier 2

IEEE Trans. on CPMT, 2010. ITRI’s 2.5D IC Integration

TSV:10μm

Stress sensor RDL Mechanical Thermal 100μm TSV:15μm TSV:10μm 50μm TSV:15μm IPD

TSV/RDL/IPD 100μm Interposer TSV:15μm RDL ` ` 80μm Ordinary bumps

Organic (BT) substrate I/O:400 ball array, pitch:450μm

Solder 350μm balls

IMAPS Trans. PCB 2011. I/O:400 ball array, pitch:1mm PCB ITRI/Rambus’ Heterogeneous Integration of Chips Ordinary RDL TSV Interposer solder TSV bumps Chip-1 Chip-2

Chip- 3

Organic package substrate Solder balls

Underfill TSV Interposer Chip-1 Underfill Chip-2

4-2-4 Substrate Chip-3

Chip-1 Chip-1 Underfill Chip-2

Interposer Interposer Chip-3 4-2-4 substrate

IEEE/ECTC2012 Xilinx/TSMC’s 2.5D IC Integration with FPGA

Chip Chip TSV-Interposer Metal C4 Bumps Layers Metal PTH Build-up Package Devices Contacts Core Layers Substrate (Cannot see) Si

Solder Cu Balls Micro Pillar Bump Solder

4RDLs TSV CoWoS Si-Interposer (chip on wafer on substrate) Homogeneous Integration on Si-substrate RDLs: 0.4μm-pitch line width and spacing Each FPGA has >50,000 μbumps on 45μm pitch Interposer is supporting >200,000 μbumps

IEEE/ECTC2013 AMD’s GPU(Fiji), Hynix’sandHBM, UMC’s Interposer -Pillar Cu-Pillar with solder Cap Solder TSV-Interposer Cu

HBM HBM GPU

HBM HBM

3 2 4 1 rd nd th st GPU with GPU with microbumps DRAM DRAM DRAM DRAM TSV C4

TSV TSV-Interposer C4 PTH

4-2-4 Build- 4-2-4 substrate Lau, PDC, ECTC2016 ECTC2016 PDC, Lau, Interposer substrate Build-up organic up TSV- Cu

TSMC’s CoWoS-2

µSolder µSolder Joints Joints Cu Cu-C4 Memory Cube TSV Solder µSolder Joints Joints SoC TSV CPU/GPU/FPGA/ASIC Cu Cu Logic C4 RDLs

TSV TSV-interposer C4 Cu

Solder Build-upBuild-up PackagePackage Substrate Substrate Joint

PCB PCB IEEE2017 Semiconductors for HPC applications driven by AI and 5G NVidia’s P100 with TSMC’s CoWoS-2 and Samsung’s HBM2

HBM2 HBM2 GPU

HBM2 HBM2

HBM2 by Samsung HBM2 4DRAMs GPU µbump Base logic die

TSV Interposer (CoWoS-2) Build-up Package Substrate C4 bump

Lau, PDC, ECTC2017 HeterogeneousSolder Ball Integration on Si-Substrate Xilinx’s HPC Applications Driven by AI and 5G

μJoint

C4-Cu Solder Joint μSolder Joint

Cu Cu Si-interposer Ni SnAg C4

SnAg Si-interposer Ni Cu Cu

IEEE/ECTC2018 3D IC Integration HBM2 DRAM8

HBM (high bandwidth memory) DRAM7

DRAM4 DRAM6 DRAM5 DRAM3 TSV DRAM4 DRAM2 μSolder DRAM3 DRAM1 Joint DRAM2 Logic Base Chip DRAM1 HBM2 Evolutionary (HBM2E) Logic Base Chip IME’s MEMS Based Tunable Laser Source, Gain Chip, and Si- Modulator on Si-Substrate

Optical MEMS Cross-Sectional View: MEMS Isolator Grating/Mirror Ball Si Actuator Lens Modulator III-IV Ball Lens Polymer Polymer Gain Chip Fiber SOA 1µm Coupler 500µm Coupler 100µm 500µm λ

500µm 6µm Silicon substrate

Thermo Electric Cooler

3-Dimensional View: Waveguide Monitor Optical MEMS PD Thermistor MEMS Isolator Grating/Mirror Polymer Actuator Coupling Fiber Coupler

λ SOA Ball Si Polymer Gain Ball Lens Modulator Coupler Chip Lens

Silicon substrate Thermo Electric Cooler

Heterogeneous Integration on Silicon Optical Bench IME, 2007 Lau, PDC, ECTC2016 AMD: A Future System might Contain a CPU Chiplet and Several GPU Chiplets all Attached to the same Piece of Network-Enabled Silicon – Heterogeneous Integration

CPU Chiplet

GPU Chiplet

CHIPLETS

IEEE/ICCAD2017 Intel’s FOVEROS Technology The key difference between the 2.5D IC Integration (CoWoS) and the FOVEROS is:  The TSV-interposer for 2.5D IC integration (CoWoS) is a passive interposer (a dummy piece of silicon)  The TSV-interposer for FOVEROS is an active interposer (with devices), just like a chip

FOVEROS (it is Greek for awesome) December 2018 Intel’s FOVEROS Technology The SoC/chiplets and the base logic die can be face-to-face by thermal compression bonding with non-conductive film or paste

SoC/Chiplets SoC/Chiplets

Base Logic Die (Active Interposer)

December 2018 ODI (Omni-Directional Interconnect) TYPE-1

 First of all, it should be emphasized that the “bridge” is not buried in the organic substrate.  Also, the bridge is not a piece of dummy silicon (like EMIB) but with devices, just like a semiconductor chip with TSVs.

TYPE-1 The bridges (chips) with TSVs are underneath the big chip (e.g., CPU, GPU, FPGA,..). The bridges are not buried in the organic package substrate.

SEMICON West, July 2019 ODI (Omni-Directional Interconnect) TYPE-2

TYPE-2 The bridge (chip) with TSVs is underneath and connecting the two big chips (e.g., CPU, GPU, FPGA, …). The bridge is not buried in the organic package substrate. They called it Type 2.

SEMICON West, July 2019 ODI (Omni-Directional Interconnect) TYPE-3

TYPE3 The base logic chip with TSVs is considered as the active bridge and connecting the two big chips (e.g., CPU, GPU, and FPGA…). This is a special case of Type 2.

SEMICON West, July 2019 Classification of Heterogeneous Integrations

C4 or C2 bumps CHIP CHIP CHIP

Embedded Bridge Embedded Bridge Package Substrate

Solder Ball

Embedded Multi-die Interconnect Bridge (EMIB) Heterogeneous Integration: Intel’s CPU (Kaby Lake) and AMD’s GPU (Radeon) HBM2 GPU PCle CPU EMIB PCB

DRAM High Bandwidth Memory-2 (HBM2) DRAM DRAM GPU DRAM AMD/GPU DRAM

GPUHMB2 (Radeon) DRAM DRAM

Solder-cap Cu-pillar DRAM Logic Base Cu-pillar Solder-cap Logic Base Build-up Layers Build-up Layers RDLs Embedded Multi-die Interconnect Bridge (EMIB) Embedded Silicon Bridge Cu-pillar PCB PCB Intel’s FPGA (Agilex) with EMIB FPGA

C4 bumps

Microbumps

Micro Solder Joint Micro Solder Joint C4 Solder Joint C4 Solder Joint HBM HBM FPGA RDL RDL EMIB Package Substrate EMIB Via Solder Joint

PCB

September 2019 Advances in Temporary Carrier Technology for High- Density Fan-Out Device Build-up Arnita Podpod, Alain Phommahaxay, Pieter Bex, John Slabbekoorn, Julien Bertheau, Abdellah Salahouelhadj, Erik Sleeckx, Andy Miller, Gerald Beyer and Eric Beyne1 Imec, Leuven, Belgium [email protected] Alice Guerrero, Kim Yess, Kim Arnold Brewer Science, Inc. Rolla, MO, USA [email protected] BRIDGE + Fan-Out (RDLs)

Wide I/O DRAM Flash Memory 200 - 300µm

TPV Logic Chip TPV 100µm Bridge with RDLs Bridge with RDLs 300µm

 No TSVs on Devices Chips  TPV is a piece of Si with TSVs

IEEE/ECTC2019 IRTI’s Heterogeneous Integration which Consists of a TSH Interposer (Bridge) Supporting Chips with Cu pillars on its Top Side and Chips with Solder Bumps on its Bottom Side

A Si-Bridge without TSVs Non-metallization holes on Through-Si Holes (TSH) the TSH interposer Interposer chip Micro Solder joints chip

RDL RDL RDL RDL RDL Solder RDL Solder chip bump Cu wire or pillar chip bump

Organic Package Substrate

Solder Solder ball ball

Printed Circuit Board Not-to-Scale

Underfill is needed between the TSH interposer and package substrate. Underfill may be needed between the TSH interposer and chips. IEEE/ECTC 2013, also, IEEE Trans. CPMT 2014 IEEE IEEE Trans. CPMT 2014 IEEE/ECTC 2013, also, consists chip, of the top TSH interposer bottom package (bridge), chip, substrate, SEM image showing SEM image showing across-section the which of heterogeneousintegration TSHInterposer Solder Bump (Bridge) Hole partially filled filled with underfill

Microbump

Cu Pillar and PCB Package Substrate Bottom Chip

Bottom Chip Interposer PCB Top Chip Top Chip TSH

Microbump

Cu Pillar

Interposer Solder Ball Underfill TSH Underfill

Classification of Heterogeneous Integrations

 Heterogeneous Integrations on Organic Substrates  Heterogeneous Integrations of Silicon Substrates (TSV Interposers)  Heterogeneous Integrations on Silicon Substrate (TSL-less interposers)  Heterogeneous Integrations on Fan-Out RDL-Substrates  Heterogeneous Integrations on Ceramic Substrates

Fanout Flipchip eWLB (embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solutions

Seung Wook Yoon, Patrick Tang, Roger Emigh, Yaojian Lin, Pandi C. Marimuthu, and Raj Pendse STATSChipPAC Ltd., 5 Yishun Street 23, Singapore 768442

TSV interposer µbump Underfill-2 Underfill-1 Logic Analog C4 bump

Solder Ball Organic Substrate  The µbump, underfill-1, and TSV-interposer are eliminated.  The RDLs are made by fan-out technology. EMC RDLs Underfill-2 Logic Analog C4 bump

IEEE/ECTC2013 Solder Ball Organic Substrate Wafer Warpage Experiments and Simulation for Fan-out Chip on Substrate (FOCoS) Yuan-Ting Lin, Wei-Hong Lai, Chin-Li Kao, Jian-Wen Lou, Ping-Feng Yang, Chi-Yu Wang, and Chueh-An Hseih* Advanced Semiconductor Engineering (ASE), Inc. e-mail: [email protected] CoWoS ASE’s FOCoS EMC Microbumps EMC Die1 Die2 + Underfill

TSV-interposer + RDLs Die1 Die2 RDLs Package Substrate Package Substrate

Solder Balls C4 bumps C4 bumps Solder Balls Underfill Underfill EMC EMC Chip1 Chip2 Chip1 Chip2 RDLs C4 bumps RDLs

RDLs C4 bumps Package Solder Underfill Package Substrate Balls Substrate

48 IEEE/ECTC2016 Samsung’s Si-less RDL Interposer for Heterogeneous Integrations C4 Bump TSV-Interposer Underfill EMC HBM Logic µBump (a) RDLs HBM2 HBM2 Package Substrate GPU µBump C4 Solder Bump Solder Ball Package Substrate

HBM2 HBM2

C4 bump (b) RDL Formation Grinding & bump attach

µbump Package Underfill substrate

Solder ball Multichip bonding RDL on substrate / ball mount

EMC

Encapsulation Lid attaching IEEE/ECTC2018 TSMC’s TSV-less Interposer (InFO_MS) for Heterogeneous Integrations

Memory Cube *Memory Cube with TSVs TSV without TSV EMC EMC Logic Logic RDLs

C4 Bump Package Substrate Package Substrate

PCB

InFO_MS (Integrated Fan-Out with Memory on Substrate) InFO_oS (Integrated Fan-Out on Substrate)

March 2019 Classification of Heterogeneous Integrations

MCM (Multichip Module) on Ceramic Substrate

CHIP5

CHIP6 CHIP2

CHIP1 CHIP4 CHIP3

MCM on Ceramic Substrate IBM 9121 TCM (Thermal Conduction Module)  TCM weighs 2.2Kg  Contains up to 121 chips about 8-10mm square  Each chip has a spring-loaded Cu piston to remove heat  Up to 10W dissipation per chip  Up to 600W dissipation per TCM Ceramic substrate has:  63 layers  Up to 400m of wirings  Up to 2 million vias  5Kg air-cooled heatsink to remove heat from TCM

Lau, ECTC2017-PDC SUMMARY and RECOMMENDATIONS In the next few years, we’ll see more of a higher-level of heterogeneous integrations, whether it is for:  time-to-market  performance  form factor  power consumption  signal integrity  cost  etc.

SUMMARY and RECOMMENDATIONS  In order to promote the heterogeneous integrations, standards are necessary! The Defense Advanced Research Projects Agency (DARPA) program called Common Heterogeneous Integration and Intellectual Property Reuse Strategies (CHIPS) is heading into the right direction.  EDA (electronic design automation) tools for automating system partitioning and design are desperately needed for complex heterogeneous integration systems.  Heterogeneous integrations is classified as: (1) heterogeneous integrations on organic substrates (2) heterogeneous integrations on silicon substrates (TSV-interposers) (3) heterogeneous integrations on silicon substrates (TSV-less interposers) (4) heterogeneous integrations on fan-out RDL substrates (5) heterogeneous integrations on ceramic substrates  75% of the heterogeneous integrations will be on organic substrates. (Actually most are SiPs).  25% of the heterogeneous integrations will be on other substrates such as silicon (TSV-interposers), silicon (TSV-less interposers), fan-out RDLs, and ceramic.  How to select different types of heterogeneous integrations? It depends on the applications. The most important indicator (selection criterion) is the metal line width and spacing of the RDLs for the substrates being used for the heterogeneous integrations.

54 Heterogeneous Integration on Various Substrates with Different Sizes, Pin-Count, and Metal Line Width and Spacing

Can be > 100,000 6500

6000

5500

5000 Heterogeneous Integrations on 4500 FO_RDL (Chip-Last) (L/S ≥ 2µm) 4000

3500

3000

PIN-COUNT PIN-COUNT 2500

2000

1500 Heterogeneous 1000 Integrations on FO_RDL 500 (Chip-First) L/S ≥ 5µm) 0 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000

SIZE (mm2) Lau, ECTC2017 , PDC

Thank You Very Much for Your Attention! 