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Single Chip and Multi Chip Integration 2019 Edition Chapter 8: Single Chip and Multi-Chip Integration http://eps.ieee.org/hir The HIR is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment. We acknowledge with gratitude the use of material and figures in this Roadmap that are excerpted from original sources. Figures & tables should be re-used only with the permission of the original source. October, 2019 Table of Contents To download additional chapters, please visit Table of Contents http://eps.ieee.org/hir CHAPTER 1: HETEROGENEOUS INTEGRATION ROADMAP: OVERVIEW .......................................................................... 1 CHAPTER 2: HIGH PERFORMANCE COMPUTING AND DATA CENTERS ............................................................................. 1 CHAPTER 3: THE INTERNET OF THINGS (IOT) .................................................................................................................. 1 CHAPTER 4: MEDICAL, HEALTH & WEARABLES ............................................................................................................... 1 CHAPTER 5: AUTOMOTIVE ............................................................................................................................................ 1 CHAPTER 6: AEROSPACE AND DEFENSE ......................................................................................................................... 1 CHAPTER 7: MOBILE ...................................................................................................................................................... 1 CHAPTER 8: SINGLE CHIP AND MULTI CHIP INTEGRATION .............................................................................................. 1 1. EXECUTIVE SUMMARY AND SCOPE ............................................................................................................................................ 1 2. ELECTRICAL ANALYSIS AND SYSTEM REQUIREMENTS ..................................................................................................................... 9 3. THERMAL MANAGEMENT ...................................................................................................................................................... 16 4. MECHANICAL REQUIREMENTS ................................................................................................................................................ 17 5. WAFER THINNING AND SINGULATION ...................................................................................................................................... 22 6. WIRE BONDING FOR MULTI‐CHIP AND SYSTEM‐IN‐PACKAGE DEVICES ........................................................................................... 26 7. FLIP CHIP AND INTERCONNECTS .............................................................................................................................................. 32 8. SUBSTRATES ....................................................................................................................................................................... 37 9. BOARD ASSEMBLY ............................................................................................................................................................... 41 10. ADDITIVE MANUFACTURING ................................................................................................................................................ 45 11. ELECTROMIGRATION ........................................................................................................................................................... 50 12. RELIABILITY ....................................................................................................................................................................... 55 13. SUMMARY AND DIFFICULT CHALLENGES ................................................................................................................................. 62 CHAPTER 9: INTEGRATED PHOTONICS ........................................................................................................................... 1 CHAPTER 10: INTEGRATED POWER ELECTRONICS .......................................................................................................... 1 CHAPTER 11: MEMS AND SENSOR INTEGRATION ........................................................................................................... 1 CHAPTER 12: 5G COMMUNICATIONS ............................................................................................................................. 1 CHAPTER 13: CO DESIGN FOR HETEROGENEOUS INTEGRATION ..................................................................................... 1 CHAPTER 14: MODELING AND SIMULATION .................................................................................................................. 1 CHAPTER 15: MATERIALS AND EMERGING RESEARCH MATERIALS ................................................................................. 1 CHAPTER 16: EMERGING RESEARCH DEVICES ................................................................................................................ 1 CHAPTER 17: TEST TECHNOLOGY ................................................................................................................................... 1 CHAPTER 18: SUPPLY CHAIN .......................................................................................................................................... 1 CHAPTER 19: SECURITY ................................................................................................................................................. 1 CHAPTER 20: THERMAL ................................................................................................................................................. 1 CHAPTER 21: SIP AND MODULE SYSTEM INTEGRATION ................................................................................................. 1 CHAPTER 22: INTERCONNECTS FOR 2D AND 3D ARCHITECTURES ................................................................................... 1 CHAPTER 23: WAFER‐LEVEL PACKAGING (WLP) ............................................................................................................. 1 HIR Version 1.0 (eps.ieee.org/hir) Page ii Heterogeneous Integration Roadmap August, 2019 Single Chip and Multi Chip Integration Chapter 8: Single Chip and Multi Chip Integration Section 1: Executive Summary and Scope 50-plus years after the invention of integrated circuits, there have been periodic predictions of the end of Moore’s Law. While significant innovations in design and process technologies are ongoing, to continue the drive to the next nodes, Moore’s Law economics are coming to an end and some key performance metrics at advanced nodes are plateauing, as described in an article “The future of computing” in the business magazine The Economist as “Moore’s Law Saturation” (Figure 1). The semiconductor industry is implementing EUV and FinFET technology at the 7 nm node. The 5 nm half-node and 3 nm node are in sight. The message in the March 2016 article is as relevant as ever today. Figure 1. Moore’s Law Saturation – Performance & Economics. (Source: The Economist March 12, 2016) We are entering the era of the digital economy and massive connectivity, with data migration to the cloud, smart devices everywhere, Internet of Things to Internet of Everything, the introduction of 5G, and the emergence of autonomous vehicles. The business landscape is seeing great changes with the rise of technology companies – social media, cloud, search, online commerce, big data, artificial intelligence – leading to integrated hardware-software driven applications and unprecedented growth of application spaces. Figure 2 listed the top 10 publicly traded companies by market capitalization in 2006 and again in 2019. While there was only one technology company in 2006 in that list, in 2019 the top 5 of the 10 are all technology companies, signifying this transition to the digital age. HIR version 1.0 (eps.ieee.org/hir) Chapter 8, Page 1 Heterogeneous Integration Roadmap August, 2019 Single Chip and Multi Chip Integration Figure 2. Rise of the tech companies (Source: www corporateinformation.com, Feb. 2019) At this triple inflection point of plateauing of CMOS’s scaling advantage, the transition to big data analytics and artificial intelligence in the digital economy, and the explosive expansion of electronic products into our global society, continued progress requires a different phase of electronics innovations. In Gordon Moore’s celebrated 1965 paper, “Cramming More Components onto Integrated Circuits”[1], his first focus was integration of transistors into integrated circuits – “The future of integrated electronics is the future of electronics itself. The advantages of integration will bring about a proliferation of electronics, pushing this science into many new areas.” In this task our industry has succeeded tremendously well indeed, in investment, technology and science of scaling, “cramming” billions of transistors into integrated circuits from wafers to chips and chips to products, fostering a global electronics industry for the benefit of society. In the same 1965 paper, Dr. Moore turn to a system focus: “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined
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