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Heterogeneous Integration

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Heterogeneous Integration 2.0 INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2.0 2015 EDITION HETEROGENEOUS INTEGRATION THE ITRS 2.0 IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT. ITRS 2.0 HETEROGENEOUS INTEGRATION CHAPTER: 2015 i ITRS 2.0 HETEROGENEOUS INTEGRATION CHAPTER: 2015 1 Table of Contents 01. Introduction.....................................................................................................................1614 12. Scope .............................................................................................................................1624 2Mission Statement .......................................................................................................................... 1636 33. Difficult Challenges.........................................................................................................1646 44. Single and Multi- Chip Packaging Overall Requirements ...............................................1658 5Electrical Requirements.................................................................................................................. 1668 6Interconnect................................................................................................................................................. 1679 7Cross Talk................................................................................................................................................... 1689 8Power Integrity.......................................................................................................................................... 16910 9Thermal Requirements ................................................................................................................. 17010 10Single Chip Package Thermal Management............................................................................................ 17110 11Hot Spots.................................................................................................................................................. 17212 12Mechanical Requirements............................................................................................................ 17313 13Mechanical Modeling and Simulation........................................................................................................ 17413 14Cost .............................................................................................................................................. 17513 15Reliability ...................................................................................................................................... 17613 16Chip to Package Substrate........................................................................................................... 17713 17Interconnect Technologies for Single Chip Package.................................................................... 17814 18Wire Bonding............................................................................................................................................ 17914 19Package Substrate to Board Interconnect.................................................................................... 18015 20For Low-Cost Applications—Laminate for PBGA (Table HI-6) ................................................................. 18115 21Mobile Applications—Build-up Substrate for SiP (HI-7)............................................................................ 18215 22Cost Performance Applications—Build-up Substrate for FCBGA (table HI-8).......................................... 18315 23High Performance—Low κ Dielectric Substrate for FCBGA (Table HI-9)................................................. 18415 24High Performance (LTCC) (table HI-10).................................................................................................... 18515 255. Wafer Level Packaging................................................................................................. 18616 26Overview ...................................................................................................................................... 18716 27Embedded Wafer Level Packaging .............................................................................................. 18819 28Wafer Level Package Developments and Trends ........................................................................ 18922 29Future Trends for Wafer Level Packaging ................................................................................................ 19023 30Examples for Emerging Wafer Level Package Technologies....................................................... 19124 31Fan Out WLP Using Reconfigured Wafer Level Technologies ................................................................. 19224 32Difficult Challenges for WLP..................................................................................................... 19325 336. 2.5 D Integration...........................................................................................................19426 347. 3D integration ...............................................................................................................19527 35Difficult Challenges for 3D integration .......................................................................................... 19629 363D Integration Definition of Terms................................................................................................ 19729 37Processes for 3D-TSV integration................................................................................................ 19830 38Technology Requirements............................................................................................................ 19931 39TSV Formation ............................................................................................................................. 20031 40TSV Interconnect Methods........................................................................................................... 20132 ITRS 2.0 HETEROGENEOUS INTEGRATION CHAPTER: 2015 1 ITRS 2.0 HETEROGENEOUS INTEGRATION CHAPTER: 2015 41Wafer/Device Stacking ................................................................................................................. 20232 42Micro Bump Formation Process ................................................................................................................ 20335 43Requirements for high k dielectrics with high breakdown field ................................................................. 20436 443D Issues................................................................................................................................................... 20536 45Heterogeneous 3D stacking process ........................................................................................................ 20637 46Emerging inter-die interconnect and bonding technology ............................................................ 20738 473D Integration of Logic and Memory ............................................................................................ 20840 48Power Integrity.............................................................................................................................. 20941 49Thermal Management .................................................................................................................. 21041 50Test for 3D Integration.................................................................................................................. 21144 51Reliability in 3D Integration........................................................................................................... 21244 528. System Level Integration in Package (SiP) ..................................................................21345 53SiP versus SoC ............................................................................................................................ 21446 54Definition of SiP............................................................................................................................ 21546 55SiP Implementations and Package on Package ....................................................................................... 21647 56Package-on-Package (PoP)...................................................................................................................... 21750 57Future Complex 3D SiP............................................................................................................................. 21851 58SiP-Level System Design versus Board-Level System Design.................................................... 21952 59Difficult Challenges for SiP........................................................................................................... 22053 60Thermal Management for SiP....................................................................................................... 22153 61Thermal Challenge of Hot Spots in SiP.................................................................................................... 22253 62Cooling Solution Design Requirements for SiP........................................................................................ 22353 63Thermal Challenges of Processor and Memory Die Stacked SiP............................................................ 22454 64Power delivery/power integrity.....................................................................................................
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