DOCSLIB.ORG

Appendix 1 -The MC68020

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Appendix 1 -The MC68020 Appendix 1 - The MC68020 This appendix contains fuller details of the instructions, addressing modes and hardware of the 68020, providing the extra details omitted from chapters 8, 11, 13 and 14, in which the 68020 microprocessor was introduced. 68020 structure The 68020 can operate in user mode or supervisor mode. User mode is where the processor is running an application program typically written by a user of the computer. Supervisor mode is where the processor is running 'system software', for example the operating system. In supervisor mode the processor can access all resources of the device, both hardware and software. In user mode, certain facilities are inaccessible. This allows some protection of the computer system; making it more difficult for the user program to crash the computer. Figure Al.l shows the registers available in the different modes. 31.----------,.-----.----. D7 .. DO, Data Registers A6 .. AO, Address Registers A7, (USP), User Stack Pointer PC, Program Counter 7! CCR, Condition Code Register a) User programming model .----------l_;SI~=:=:=::C::C::R=:I SR, Status Register ISP, Interrupt SP MSP, Master SP VBR, Vector Base Register SFC,} Alternate Function DFC, Code Registers CACR, Cache Control Register CAAR, Cache Address Register b) Supervisor programming model supplement c) Status I Condition Code Register Figure Al.l Registers in the 68020 In user mode, the 68020 has eight 32-bit data registers, D7 .. DO; seven 32-bit address registers, A6 .. AO; the user stack pointer, USP, also called A7; a 32-bit program counter, PC; and an 8-bit condition code register, CCR. The flags in the CCR are shown in figure Al.lc and described in chapter 8. 254 Appendix 1 - The MC68020 255 The 68020 has extra registers accessible in supervisor mode, as shown in figure Al.lb. These are the master stack pointer, MSP, the stack pointer used in supervisor mode; the interrupt stack pointer, ISP, which is used when an interrupt occurs; the vector base register, VBR, which contains the address of memory in which the addresses of routines for exceptions are stored; two alternative function registers, SFC and DFC; and two cache memory registers, CACR and CAAR, for controlling the cache memory which is used to speed operation of the processor by acquiring information in preparation for the time when the 68020 is ready to use it. In addition there is the 16-bit status register, SR, the lower byte of which is the condition code register, and the upper byte specifies various aspects; this is shown in figure Al.lc. Bits I2, 11 and 10 are the interrupt mask; an interrupt is requested when an external 3-bit number is specified, and this request will be serviced only of the number exceeds that on the interrupt mask. The bits S and M specify the mode of the 68020; S = 0 for user mode; S = 1, M = 1 for supervisor master mode; and S = 1, M = 0 for supervisor interrupt mode. Bits Tl-TO indicate the trace mode, in which part of the user program is obeyed and then the program stops, by calling an exception which typically allows the state of the machine to be examined. If T1 = 1 and TO = 0, then only one instruction of the user program is obeyed before the 68020 stops. If T1 = 0 and TO = 0, then the processor obeys a sequence of instructions; a typical end of sequence is a branch to subroutine instruction. The 68000 has only the first trace mode and thus one trace bit in the status register. Format of68020 instructions Instructions on the 68020 are of the form: INSTR SIZE OPERANDS where INSTR is the mnemonic for the instructions SIZE is the optional field indicating that byte (.B), word (.W) or longword (.L) data are to be processed; if SIZE is omited, then word data is assumed. OPERANDS are the zero, one or two addressing modes. Addressing modes The 68020 has 14 addressing modes which can be applied in general to both the source and destination operands. Some of these modes are complicated and will be used rarely by the assembly language programmer. However, these complicated modes were designed to allow efficient implementation of some high level language statements. The addressing modes are listed below, where the name is given, followed by its syntax and then an explanation with appropriate examples. (68020) next to a mode means that the mode is available on the 68020 and subsequent processors, but not the 68000. 256 Microprocessor Systems Immediate Syntax: #data The addressing mode contains the data, the size of which is determined by the size associated with the instruction. Absolute Address Syntax: (xxx) The address of the data is the value given by xxx. If xxx is a 16-bit value then the assembler generates for the instruction a 16-bit value, which the processor 'sign extends' to a 32-bit value; that is, bits 31..16 have the same value as bit 15; so xxx is in the range $8000 .. $7FFF which will be extended to a value in the range $FFFF8000 .. $00007FFF. If xxx is a 32-bit value, then that 32-bit value is encoded in full into the instruction. Absolute Short Address Syntax: (xxx).W Here the .W is forcing the assembler to generate a 16-bit value for the address. The assembler also checks to see that xxx is in the correct range. Absolute Long Address Syntax: (xxx).L Here the .L forces the assembler to generate a 32-bit address. Data Register Dir~ct Syntax: Dn This specifies the nth data register, n is in the range 0 .. 7. Address Register Direct Syntax: An This specifies the nth address register, n is in the range 0 .. 7. Address Register Indirect Syntax: (An) The contents of the address register specify the address. Address Register Indirect with Postincrement Syntax: (An)+ The data at the address stored in An are specified, then An is incremented. The amount by which the register is incremented is I, 2 or 4 bytes, depending on whether the instruction was processing 8, I6 or 32 bits of data, except if the address register is the stack pointer (A 7) and I byte is specified, the register is incremented by 2, so that the stack pointer remains on an even boundary. Address Register Indirect with Predecrement Syntax: -(An) The address register is decremented, then the data at the address specified by the register are specified. The amount by which the register is decremented is determined by the rules given above. Appendix 1 - The MC68020 257 Address Register Indirect with Displacement Syntax: (d16,An) or d16(An) where d 16 is a 16-bit signed number. Here the address is that found in the address register to which d16 is added; if A1 contains 2000, then (100,A1) specifies address 2100. Address Register Indirect with Index Syntax: (d8,An,Xn,SIZE) or d8(An,Xn,SIZE) where d8 is a signed 8-bit number, Xn is the nth address register or data register, and SIZE specifies the size of Xn, being .W or .L (.W is assumed if it is omitted). The address is found by d8 + An + Xn. Both d8 and Xn are sign extended to 32-bit numbers. If A1 contains 2000 and D3 contains 100, then ($FF,A1,D3.W) specifies address 2099 (that is -1 + 2000 + 100). Address Register Indirect with Scaled Index Syntax: (d8,An,Xn,SIZE*SCALE) or d8(An,Xn,SIZE*SCALE) This is the same as the previous mode, except the value SCALE, which can be 1, 2, 4 or 8, and this is the value by which the contents of the register Xn is multiplied after being sign extended. If AI contains 2000, and D2 contains 100 and AO contains $FFFF then (10,A1,D2,.L*2) specifies address 10 + 2000 + 100*2 = 2210; and (10,A1,AO,.W*4) is address 10 + 2000 + ($FFFFFFFF)*4 = 2006. Address Register Indirect with Base Displacement (68020) Syntax: (bd,An,Xn,SIZE*SCALE) where bd is the 16- or 32-bit signed base displacement whose size and scale are specified by the last parameter. The address is found by bd + An + Xn. Note, in this mode, bd, An, Xn and size and scale are all optional. If A5 contains 4000, A1 contains 255 and D4 contains 200, then (1 OO,A5,A1 ,.W*2) specifies address 100*2 + 4000 + 255 = 4455; (D4) specifies address 200. Memory Indirect (68020) Syntax: ([bd,An],od) where bd and od are the 16-bit or 32-bit base and outer displace­ ments, both of which may be omitted. The address is (value found at bd + An) + od. If A5 contains 2000, and 4000 is at address 2010, then ([ 1O,A5],45) is address 4045. Memory Indirect Postlndexed (68020) Syntax ([bd,An],Xn,SIZE*SCALE,od) Address is (value found at bd +An) + Xn*SCALE + od Again, SIZE and SCALE specify the size of the index register Xn and its scale factor, which can be 1, 2 or 4. bd, An and od are optional. If A5 contains 2000, the value at address 2010 is 4000 and D6 contains 100, then ([10,A5],D6,.W*4,50) specifies the address 4000 + 100*4 + 50 = 4450 258 Microprocessor Systems Memory Indirect Preindexed (68020) Syntax ([bd,An,Xn,SIZE*SCALE],od) Address is (value at bd + An + Xn * SCALE) + od bd and od are optional. This is like the previous mode except the index register is used to calculate the address prior to the indirection. The modes 'Address Register Indirect with Displacement' onwards can also be used with the program counter instead of an address register.
Load more

Recommended publications
  • Chapter 5 the LC-3
    Instruction Set Architecture ISA = Programmer-visible components & operations • Memory organization Address space -- how may locations can be addressed? Addressibility -- how many bits per location? • Register set Chapter 5 How many? What size? How are they used? • Instruction set The LC-3 Opcodes Data types Addressing modes All information needed to write/gen machine language program Based on slides © McGraw-Hill Additional material © 2004/2005 Lewis/Martin CSE 240 5-2 LC-3 Overview: Memory and Registers LC-3 Overview: Instruction Set Memory Opcodes • Address space: 216 locations (16-bit addresses) • 16 opcodes • Addressibility: 16 bits • Operate instructions: ADD, AND, NOT, (MUL) • Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI Registers • Control instructions: BR, JSR, JSRR, RET, RTI, TRAP • Temporary storage, accessed in a single machine cycle • Some opcodes set/clear condition codes, based on result Memory access generally takes longer N = negative (<0), Z = zero (=0), P = positive (> 0) • Eight general-purpose registers: R0 - R7 Data Types Each 16 bits wide • 16-bit 2’s complement integer How many bits to uniquely identify a register? Addressing Modes • Other registers • How is the location of an operand specified? Not directly addressable, but used by (and affected by) • Non-memory addresses: register, immediate (literal) instructions PC (program counter), condition codes, MAR, MDR, etc. • Memory addresses: base+offset, PC-relative, indirect CSE 240 5-3 CSE 240 5-4 1 LC-3 Instruction Summary Operate Instructions (inside back cover) Only three operations • ADD, AND, NOT Source and destination operands are registers • Do not reference memory • ADD and AND can use “immediate” mode, (i.e., one operand is hard-wired into instruction) Will show abstracted datapath with each instruction • Illustrate when and where data moves to accomplish desired op.
    [Show full text]
  • Instruction Set Architecture
    Instruction Set Architecture EE3376 1 –Adapted from notes from BYU ECE124 Topics to Cover… l MSP430 ISA l MSP430 Registers, ALU, Memory l Instruction Formats l Addressing Modes l Double Operand Instructions l Single Operand Instructions l Jump Instructions l Emulated Instructions – http://en.wikipedia.org/wiki/TI_MSP430 2 –Adapted from notes from BYU ECE124 Levels of Transformation –Problems –Algorithms – C Instructions –Language (Program) –Programmable –Assembly Language – MSP 430 ISA –Machine (ISA) Architecture –Computer Specific –Microarchitecture –Manufacturer Specific –Circuits –Devices 3 –Adapted from notes from BYU ECE124 Instruction Set Architecture l The computer ISA defines all of the programmer-visible components and operations of the computer – memory organization l address space -- how may locations can be addressed? l addressibility -- how many bits per location? – register set (a place to store a collection of bits) l how many? what size? how are they used? – instruction set l Opcodes (operation selection codes) l data types (data types: byte or word) l addressing modes (coding schemes to access data) l ISA provides all information needed for someone that wants to write a program in machine language (or translate 4 from a high-level language to machine language). –Adapted from notes from BYU ECE124 MSP430 Instruction Set Architecture l MSP430 CPU specifically designed to allow the use of modern programming techniques, such as: – the computation of jump addresses – data processing in tables – use of high-level languages such as C. l 64KB memory space with 16 16-bit registers that reduce fetches to memory. l Implements RISC architecture with 27 instructions and 7 addressing modes.
    [Show full text]
  • X86 Instruction Set 4.2 Why Learn Assembly
    4.1 CS356 Unit 4 Intro to x86 Instruction Set 4.2 Why Learn Assembly • To understand something of the limitation of the HW we are running on • Helpful to understand performance • To utilize certain HW options that high-level languages don't allow (e.g. operating systems, utilizing special HW features, etc.) • To understand possible security vulnerabilities or exploits • Can help debugging 4.3 Compilation Process CS:APP 3.2.2 void abs(int x, int* res) • Demo of assembler { if(x < 0) *res = -x; – $ g++ -Og -c -S file1.cpp else *res = x; • Demo of hexdump } Original Code – $ g++ -Og -c file1.cpp – $ hexdump -C file1.o | more Disassembly of section .text: 0000000000000000 <_Z3absiPi>: 0: 85 ff test %edi,%edi 2: 79 05 jns 9 <_Z3absiPi+0x9> • Demo of 4: f7 df neg %edi 6: 89 3e mov %edi,(%rsi) 8: c3 retq objdump/disassembler 9: 89 3e mov %edi,(%rsi) b: c3 retq – $ g++ -Og -c file1.cpp Compiler Output – $ objdump -d file1.o (Machine code & Assembly) Notice how each instruction is turned into binary (shown in hex) 4.4 Where Does It Live • Match (1-Processor / 2-Memory / 3-Disk Drive) where each item resides: – Source Code (.c/.java) = 3 – Running Program Code = 2 – Global Variables = 2 – Compiled Executable (Before It Executes) = 3 – Current Instruction Being Executed = 1 – Local Variables = 2 (1) Processor (2) Memory (3) Disk Drive 4.5 BASIC COMPUTER ORGANIZATION 4.6 Processor • Performs the same 3-step process over and over again – Fetch an instruction from Processor Arithmetic 3 Add the memory Circuitry specified values Decode 2 It’s an ADD – Decode the instruction Circuitry • Is it an ADD, SUB, etc.? 1 Fetch – Execute the instruction Instruction System Bus • Perform the specified operation • This process is known as the ADD SUB Instruction Cycle CMP Memory 4.7 Processor CS:APP 1.4 • 3 Primary Components inside a processor – ALU – Registers – Control Circuitry • Connects to memory and I/O via address, data, and control buses (bus = group of wires) Bus Processor Memory PC/IP 0 Addr Control 0 op.
    [Show full text]
  • V850e/Ms1 , V850e/Ms2
    User’s Manual V850E/MS1TM, V850E/MS2TM 32-Bit Single-Chip Microcontrollers Architecture V850E/MS1: V850E/MS2: µPD703100 µPD703130 µPD703100A µPD703101 µPD703101A µPD703102 µPD703102A µPD70F3102 µPD70F3102A Document No. U12197EJ6V0UM00 (6th edition) Date Published November 2002 N CP(K) 1996 Printed in Japan [MEMO] 2 User’s Manual U12197EJ6V0UM NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry.
    [Show full text]
  • UNIT 2 Q.1 Explain Addressing Modes of PIC Microcontroller. the PIC 18 Microcontroller Supports Following Addressing Modes. 1. Immediate Addressing Mode 2
    UNIT 2 Q.1 Explain addressing modes of PIC microcontroller. The PIC 18 microcontroller supports following addressing modes. 1. Immediate addressing mode 2. Direct addressing mode 3. Register addressing mode 4. Indexed ROM addressing mode 1. Immediate addressing mode: In immediate addressing mode, the immediate data is specified in the instruction. The immediate addressing mode is used to load the data into PIC registers and WREG register. However, it cannot use to load data into any of the file register. Example: 1. MOVLW 50H 2. ANDLW 40H 3. IORLW 60H 2. Direct addressing mode: In direct addressing mode, the 8- bit data in RAM memory location whose address is specified in the instruction. This mode is used for accessing the RAM file register. Example: 1. MOVWF 0X10 2. MOVFF PORTB, POTRC 3. MOVFF 0X30, PORTC 3. Register indirect addressing mode: Register indirect addressing mode is used for accessing data stored in the RAM part of file register. In this addressing mode a register is used as pointer to the memory location of the file register. Three file select registers are used. They are FSR0, FSR1 and FSR2. Example: 1. LFSR1,0X55 2. MOVWF INDF2 4. Indexed ROM addressing mode: This addressing mode is used for accessing the data from look up tables that reside in the PIC18 program ROM. Q.2 Explain following instructions: 1. ADDLW ADD literal to W Syntax: ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (WREG) + k → WREG Status Affected: N, OV, C, DC, Z Description: The contents of WREG are added to the 8-bit literal ’k’ and the result is placed in WREG.
    [Show full text]
  • Addressing Modes of Computer - Ii
    ADDRESSING MODES OF COMPUTER - II INDEXING AND ARRAYS:- A different kind of flexibility for accessing operands is useful in dealing with lists and arrays. Index mode – the effective address of the operand is generated by adding a constant value to the contents of a register. The register use may be either a special register provided for this purpose, or, more commonly, it may be any one of a set of general-purpose registers in the processor. In either case, it is referred to as index register. We indicate the Index mode symbolically as X (Ri) Where X denotes the constant value contained in the instruction and Ri is the name of the register involved. The effective address of the operand is given by EA = X + [Rj] The contents of the index register are not changed in the process of generating the effective address. In an assembly language program, the constant X may be given either as an explicit number or as a symbolic name representing a numerical value. Fig a illustrates two ways of using the Index mode. In fig a, the index register, R1, contains the address of a memory location, and the value X defines an offset (also called a displacement) from this address to the location where the operand is found. An alternative use is illustrated in fig b. Here, the constant X corresponds to a memory address, and the contents of the index register define the offset to the operand. In either case, the effective address is the sum of two values; one is given explicitly in the instruction, and the other is stored in a register.
    [Show full text]
  • Module 1 Introduction
    MODULE 1 TOPICS COVERED:- 1. Introduction to the general concept of microprocessor 2. I/O subsystem , programming the system 3. ALU 4. Instruction execution, instruction word format 5. Addressing modes 6. Address/data/control bus 7. Tristate bus 8. Interfacing i/o device 9. Data transfer scheme 10. Architectural advancement of microprocessor 11. Evolution of processor INTRODUCTION A computer basically consists of the following parts:- 1. I/O devices 2. Memory 3. CPU The CPU is the brain of the computer irrespective of its size. The CPU normally consists of a large scale integrationcircuit called Microprocessor and works as central processing unit of a microcomputer. Input Devices give data or information as an input to the CPU and it processes the data or information given by the devices. Memory stores the data or information, Output Devices give the required data as output to the user. A digital component in which one microprocessor has been provided to act as a CPU is known as Microcomputer. Desktop computer, laptop computer, palm computer, notebook are the ones which contain only one microprocessor to act as a CPU. Microprocessor:- Definition- A microprocessor is a multipurpose programmable, clock driven, semiconductor device consisting of electronic logic circuit manufactured by using very large scale integration (VLSI) technique. • The Microprocessor is capable of performing various computing functions and making decisions to change the sequence of program executions. • The microprocessor application are classified primarily into two categories:- 1. Reprogrammable systems 2. Embedded System • Microprocessor can perform the following operations:- 1. Read data from memory 2. Write data into memory 3.
    [Show full text]
  • COSC 6385 Computer Architecture Instruction Set Architectures
    COSC 6385 Computer Architecture Instruction Set Architectures Edgar Gabriel Spring 2011 Edgar Gabriel Instruction Set Architecture (ISA) • Definition on Wikipedia: “Part of the Computer Architecture related to programming” • Defines – set of operations, – instruction format, – hardware supported data types, – named storage, – addressing modes, – sequencing • Includes a specification of the set of opcodes (machine language) - native commands implemented by a particular CPU design COSC 6385 – Computer Architecture Edgar Gabriel Instruction Set Architecture (II) • ISA to be distinguished from the micro-architecture – set of processor design techniques used to implement an ISA • Example: Intel Pentium and AMD Athlon support a nearly identical ISA, but have completely different micro-architecture COSC 6385 – Computer Architecture Edgar Gabriel ISA Specification • Relevant features for distinguishing ISA’s – Internal storage – Memory addressing – Type and size of operands – Operations – Instructions for Flow Control – Encoding of the IS COSC 6385 – Computer Architecture Edgar Gabriel Internal storage • Stack architecture: operands are implicitly on the top of the stack • Accumulator architecture: one operand is implicitly the accumulator • General purpose register architectures: operands have to be made available by explicit load operations – Dominant form in today’s systems COSC 6385 – Computer Architecture Edgar Gabriel Internal storage (II) • Example: C= A+B Stack: Accumulator: Load-Store: Push A Load A Load R1,A Push B Add B Load R2,B Add
    [Show full text]
  • Cpe 323 Instruction Set Architecture: an Introduction
    CPE 323 INSTRUCTION SET ARCHITECTURE: AN INTRODUCTION Aleksandar Milenkovic Computers cannot execute high-level language constructs like ones found in C. Rather they execute a relatively small set of machine instructions, such as addition, subtraction, Boolean operations, and data transfers. The statements from high-level language are translated into sequences of machine code instructions by a compiler. A machine code instruction is represented by a binary string which is hard to be read by humans. A human-readable form of the machine code is assembly language. However, assembly language may also include some constructs that serve only to help programmers write a better and more efficient code, faster. These constructs may translate into a sequence of machine code instructions. Instruction set architecture, or ISA for short, refers to a portion of a computer that is visible to low-level programmers, such as assembly language programmers or compiler writers. It is an abstract view of the computer describing what it does rather than how it does. Note: computer organization describes how the computer achieves the specified functionality is out of scope in this course. The ISA aspects include (a) class of ISA, (b) memory model, (c) addressing modes, (d) types and sizes of operands, (e) data processing and control flow operations supported by machine instructions, and (f) instruction encoding. Class of ISA. Virtually all recent instruction set architectures have a set of general- purpose registers visible to programmers. These architectures are known as general- purpose register architectures. Machine instructions in these architectures specify all operands in memory or general-purpose registers explicitly.
    [Show full text]
  • Addressing Mode
    Central Processing Unit Addressing modes Numerical example Immediate Mode Indirect Mode Indexing Mode Relative Mode The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed. Computers use addressing mode techniques for the purpose of accommodating one of the following provisions: 1. To give programming versatilities to the user to be more flexible. 2. To reduce the number of bits in the addressing field of the instruction. In some some computers, the addressing mode of the instruction is specified with distinct binary code. Instruction format with mode field Opcode Mode Address 3 Other computers use a single binary for operation & Address mode. The mode field is used to locate the operand. Address field may designate a memory address or a processor register. There are 2 modes that need no address field at all (Implied & immediate modes). 4 The most well known addressing mode then are: Implied mode. Immediate mode Register mode Register Indirect mode Auto-increment or Auto-decrement mode Direct Mode Indirect Mode Relative Address Mode Index Addressing Mode 5 PC=200 R1=400 Address Memory XR=100 AC 200 Load to AC Mode 201 Address=500 202 Next Instruction Addressing mode eff. Add Content of AC ----------------------------------------------------------- 399 450 Direct Address 500 800 400 700 Immediate operand 201 500 Indirect Address 800 300 500 800 Relative Address 702 (PC=PC+2) 325 Indexes Address 600 (XR+500) 900 600 900 Register --- 400 702 325 Register Indirect 400 700 Auto-increment 400 700 800 300 Auto-decrement 399 450 Tabular list 6 Different ways in which the address of an operand in specified in an instruction is referred to as addressing modes.
    [Show full text]
  • VAX MACRO and Instruction Set Reference Manual
    VAX MACRO and Instruction Set Reference Manual Order Number: AA–PS6GD–TE April 2001 This document describes the features of the VAX MACRO instruction set and assembler. It includes a detailed description of MACRO directives and instructions, as well as information about MACRO source program syntax. Revision/Update Information: This manual supersedes the VAX MACRO and Instruction Set Reference Manual, Version 7.1 Software Version: OpenVMS VAX Version 7.3 Compaq Computer Corporation Houston, Texas © 2001 Compaq Computer Corporation Compaq, VAX, VMS, and the Compaq logo Registered in U.S. Patent and Trademark Office. OpenVMS is a trademark of Compaq Information Technologies Group, L.P. in the United States and other countries. All other product names mentioned herein may be trademarks of their respective companies. Confidential computer software. Valid license from Compaq required for possession, use, or copying. Consistent with FAR 12.211 and 12.212, Commercial Computer Software, Computer Software Documentation, and Technical Data for Commercial Items are licensed to the U.S. Government under vendor’s standard commercial license. Compaq shall not be liable for technical or editorial errors or omissions contained herein. The information in this document is provided "as is" without warranty of any kind and is subject to change without notice. The warranties for Compaq products are set forth in the express limited warranty statements accompanying such products. Nothing herein should be construed as constituting an additional warranty. ZK4515 The Compaq OpenVMS documentation set is available on CD-ROM. This document was prepared using DECdocument, Version 3.3-1b. Contents Preface ............................................................ xv VAX MACRO Language 1 Introduction 2 VAX MACRO Source Statement Format 2.1 Label Field .
    [Show full text]
  • Appendix E Another Alternative to RISC: the VAX Architecture
    E.1 Introduction E-2 E.2 VAX Operands and Addressing Modes E-2 E.3 Encoding VAX Instructions E-5 E.4 VAX Operations E-6 E.5 An Example to Put It All Together: swap E-10 E.6 A Longer Example: sort E-13 E.7 Fallacies and Pitfalls E-18 E.8 Concluding Remarks E-19 E.9 Historical Perspective and Further Reading E-20 Exercises E-21 E Another Alternative to RISC: The VAX Architecture In principle, there is no great challenge in designing a large virtual address minicomputer system. The real challenge lies in two areas: compatibility—very tangible and important; and simplicity— intangible but nonetheless important. William Strecker “VAX-11/780—A Virtual Address Extension to the PDP-11 Family,” AFIPS Proc., National Computer Conference, 1978. Entities should not be multiplied unnecessarily. William of Occam Quodlibeta Septem, 1320 (This quote is known as “Occam’s Razor.”) © 2003 Elsevier Science (USA). All rights reserved. E-2 I Appendix E Another Alternative to RISC: The VAX Architecture E.1 Introduction To enhance your understanding of instruction set architectures, we chose the VAX as the representative Complex Instruction Set Computers (CISC) because it is so different from MIPS and yet still easy to understand. By seeing two such divergent styles, we are confident that you will be able to learn other instruction sets on your own. At the time the VAX was designed, the prevailing philosophy was to create instruction sets that were close to programming languages in order to simplify compilers. For example, because programming languages had loops, instruction sets should have loop instructions.
    [Show full text]