Appendix 1 - The MC68020 This appendix contains fuller details of the instructions, addressing modes and hardware of the 68020, providing the extra details omitted from chapters 8, 11, 13 and 14, in which the 68020 microprocessor was introduced. 68020 structure The 68020 can operate in user mode or supervisor mode. User mode is where the processor is running an application program typically written by a user of the computer. Supervisor mode is where the processor is running 'system software', for example the operating system. In supervisor mode the processor can access all resources of the device, both hardware and software. In user mode, certain facilities are inaccessible. This allows some protection of the computer system; making it more difficult for the user program to crash the computer. Figure Al.l shows the registers available in the different modes. 31.----------,.-----.----. D7 .. DO, Data Registers A6 .. AO, Address Registers A7, (USP), User Stack Pointer PC, Program Counter 7! CCR, Condition Code Register a) User programming model .----------l_;SI~=:=:=::C::C::R=:I SR, Status Register ISP, Interrupt SP MSP, Master SP VBR, Vector Base Register SFC,} Alternate Function DFC, Code Registers CACR, Cache Control Register CAAR, Cache Address Register b) Supervisor programming model supplement c) Status I Condition Code Register Figure Al.l Registers in the 68020 In user mode, the 68020 has eight 32-bit data registers, D7 .. DO; seven 32-bit address registers, A6 .. AO; the user stack pointer, USP, also called A7; a 32-bit program counter, PC; and an 8-bit condition code register, CCR. The flags in the CCR are shown in figure Al.lc and described in chapter 8. 254 Appendix 1 - The MC68020 255 The 68020 has extra registers accessible in supervisor mode, as shown in figure Al.lb. These are the master stack pointer, MSP, the stack pointer used in supervisor mode; the interrupt stack pointer, ISP, which is used when an interrupt occurs; the vector base register, VBR, which contains the address of memory in which the addresses of routines for exceptions are stored; two alternative function registers, SFC and DFC; and two cache memory registers, CACR and CAAR, for controlling the cache memory which is used to speed operation of the processor by acquiring information in preparation for the time when the 68020 is ready to use it. In addition there is the 16-bit status register, SR, the lower byte of which is the condition code register, and the upper byte specifies various aspects; this is shown in figure Al.lc. Bits I2, 11 and 10 are the interrupt mask; an interrupt is requested when an external 3-bit number is specified, and this request will be serviced only of the number exceeds that on the interrupt mask. The bits S and M specify the mode of the 68020; S = 0 for user mode; S = 1, M = 1 for supervisor master mode; and S = 1, M = 0 for supervisor interrupt mode. Bits Tl-TO indicate the trace mode, in which part of the user program is obeyed and then the program stops, by calling an exception which typically allows the state of the machine to be examined. If T1 = 1 and TO = 0, then only one instruction of the user program is obeyed before the 68020 stops. If T1 = 0 and TO = 0, then the processor obeys a sequence of instructions; a typical end of sequence is a branch to subroutine instruction. The 68000 has only the first trace mode and thus one trace bit in the status register. Format of68020 instructions Instructions on the 68020 are of the form: INSTR SIZE OPERANDS where INSTR is the mnemonic for the instructions SIZE is the optional field indicating that byte (.B), word (.W) or longword (.L) data are to be processed; if SIZE is omited, then word data is assumed. OPERANDS are the zero, one or two addressing modes. Addressing modes The 68020 has 14 addressing modes which can be applied in general to both the source and destination operands. Some of these modes are complicated and will be used rarely by the assembly language programmer. However, these complicated modes were designed to allow efficient implementation of some high level language statements. The addressing modes are listed below, where the name is given, followed by its syntax and then an explanation with appropriate examples. (68020) next to a mode means that the mode is available on the 68020 and subsequent processors, but not the 68000. 256 Microprocessor Systems Immediate Syntax: #data The addressing mode contains the data, the size of which is determined by the size associated with the instruction. Absolute Address Syntax: (xxx) The address of the data is the value given by xxx. If xxx is a 16-bit value then the assembler generates for the instruction a 16-bit value, which the processor 'sign extends' to a 32-bit value; that is, bits 31..16 have the same value as bit 15; so xxx is in the range $8000 .. $7FFF which will be extended to a value in the range $FFFF8000 .. $00007FFF. If xxx is a 32-bit value, then that 32-bit value is encoded in full into the instruction. Absolute Short Address Syntax: (xxx).W Here the .W is forcing the assembler to generate a 16-bit value for the address. The assembler also checks to see that xxx is in the correct range. Absolute Long Address Syntax: (xxx).L Here the .L forces the assembler to generate a 32-bit address. Data Register Dir~ct Syntax: Dn This specifies the nth data register, n is in the range 0 .. 7. Address Register Direct Syntax: An This specifies the nth address register, n is in the range 0 .. 7. Address Register Indirect Syntax: (An) The contents of the address register specify the address. Address Register Indirect with Postincrement Syntax: (An)+ The data at the address stored in An are specified, then An is incremented. The amount by which the register is incremented is I, 2 or 4 bytes, depending on whether the instruction was processing 8, I6 or 32 bits of data, except if the address register is the stack pointer (A 7) and I byte is specified, the register is incremented by 2, so that the stack pointer remains on an even boundary. Address Register Indirect with Predecrement Syntax: -(An) The address register is decremented, then the data at the address specified by the register are specified. The amount by which the register is decremented is determined by the rules given above. Appendix 1 - The MC68020 257 Address Register Indirect with Displacement Syntax: (d16,An) or d16(An) where d 16 is a 16-bit signed number. Here the address is that found in the address register to which d16 is added; if A1 contains 2000, then (100,A1) specifies address 2100. Address Register Indirect with Index Syntax: (d8,An,Xn,SIZE) or d8(An,Xn,SIZE) where d8 is a signed 8-bit number, Xn is the nth address register or data register, and SIZE specifies the size of Xn, being .W or .L (.W is assumed if it is omitted). The address is found by d8 + An + Xn. Both d8 and Xn are sign extended to 32-bit numbers. If A1 contains 2000 and D3 contains 100, then ($FF,A1,D3.W) specifies address 2099 (that is -1 + 2000 + 100). Address Register Indirect with Scaled Index Syntax: (d8,An,Xn,SIZE*SCALE) or d8(An,Xn,SIZE*SCALE) This is the same as the previous mode, except the value SCALE, which can be 1, 2, 4 or 8, and this is the value by which the contents of the register Xn is multiplied after being sign extended. If AI contains 2000, and D2 contains 100 and AO contains $FFFF then (10,A1,D2,.L*2) specifies address 10 + 2000 + 100*2 = 2210; and (10,A1,AO,.W*4) is address 10 + 2000 + ($FFFFFFFF)*4 = 2006. Address Register Indirect with Base Displacement (68020) Syntax: (bd,An,Xn,SIZE*SCALE) where bd is the 16- or 32-bit signed base displacement whose size and scale are specified by the last parameter. The address is found by bd + An + Xn. Note, in this mode, bd, An, Xn and size and scale are all optional. If A5 contains 4000, A1 contains 255 and D4 contains 200, then (1 OO,A5,A1 ,.W*2) specifies address 100*2 + 4000 + 255 = 4455; (D4) specifies address 200. Memory Indirect (68020) Syntax: ([bd,An],od) where bd and od are the 16-bit or 32-bit base and outer displace­ ments, both of which may be omitted. The address is (value found at bd + An) + od. If A5 contains 2000, and 4000 is at address 2010, then ([ 1O,A5],45) is address 4045. Memory Indirect Postlndexed (68020) Syntax ([bd,An],Xn,SIZE*SCALE,od) Address is (value found at bd +An) + Xn*SCALE + od Again, SIZE and SCALE specify the size of the index register Xn and its scale factor, which can be 1, 2 or 4. bd, An and od are optional. If A5 contains 2000, the value at address 2010 is 4000 and D6 contains 100, then ([10,A5],D6,.W*4,50) specifies the address 4000 + 100*4 + 50 = 4450 258 Microprocessor Systems Memory Indirect Preindexed (68020) Syntax ([bd,An,Xn,SIZE*SCALE],od) Address is (value at bd + An + Xn * SCALE) + od bd and od are optional. This is like the previous mode except the index register is used to calculate the address prior to the indirection. The modes 'Address Register Indirect with Displacement' onwards can also be used with the program counter instead of an address register.