Driving Transistors and Thyristors
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145 Driving transistors and thyristors 7.1 Application of the power MOSFET and IGBT The MOSFET gate is isolated electrically from the source by a layer of silicon dioxide. 7 Theoretically no current flows into the gate when a dc voltage is applied to it. In practice, gate current is required to charge device capacitances and a small leakage current of the order of nano-amps does flow in order to maintain the gate voltage. Driving Transistors and When no voltage is applied between the gate and source terminals, the drain-to- source impedance is very high and only a small leakage current of less than a milli-amp Thyristors flows in the drain, until the applied voltage exceeds the drain-to-source avalanche voltage, V . DSS When a positive gate voltage is applied, an electric field is produced which modulates the drain-to-source resistance. When a gate voltage exceeds the threshold The thyristor, being a multiple bipolar junction device, is essentially a current- voltage level the channel resistance reduces to a low resistance and drain current flows. controlled device. As illustrated in figure 7.la, a current must be supplied between the The maximum drain current depends on the gate voltage magnitude, assuming that the gate and cathode terminals to produce anode current flow, provided the anode is impedance of the external drain circuit is not current-limiting. forward biased. The magnitude of gate drive current determines the delay time and the Turnoff - reducing the drain current to the leakage level - is achieved by reducing anode current rise time. In gate commutated thyristors, a negative gate current must be the gate voltage to below the gate threshold voltage level. The drain switching speeds produced, the magnitude determining the turn-off delay time and anode current fall are essentially determined by that speed at which the gate voltage can reach a level time. above the threshold voltage (for turn-on) or below the threshold voltage (for turn-off). The power MOSFET and IGBT are voltage controlled devices and are fundamentally Although the gate-to-source capacitance is an important parameter, the gate-to-drain different to bipolar devices. With the n-channel enhancement-mode power MOSFET capacitance is more significant because of the Miller effect, as considered in section and IGBT, a positive voltage must be applied between the gate and source terminals to 4.4.2. During switching the dynamic gate-to-drain capacitance can be effectively much produce a drain current, if the drain is positively biased with respect to the source, as larger than the gate-to-source capacitance. The Miller capacitance typically requires shown in figure 7.lb. Generally the MOSFET and IGBT are easier to drive than the more charge for switching than the gate-to-source capacitance. bipolar thyristor, and only a few basic considerations are required for MOSFET and IGBT gate circuit implementation. 7.1.1 Gate drive circuits The n-channel enhancement-mode power MOSFET (or IGBT) with a low threshold Gate current voltage interfaces easily with logic level integrated circuits. This allows low-power IA produces digital logic circuits to control directly high-power levels. Figure 7.2 shows a series of anode current + + ttl and cmos circuits driving power MOSFETs, each circuit offering different levels of switching speed and performance. MOSFET iG When driving a MOSFET directly from a cmos gate output, as shown in figure 7.2a, only modest rise and fall times can be expected because of the limited source and sink current available from a cmos gate. Figure 7.3a illustrates the output configuration of a typical cmos output stage, which consists of a series-connected p and n-channel MOSFET with the gates connected together. The cmos totem pole output stage is driven by a common signal, hence the name complementary mos - cmos - and when the input is high the n-channel device is on and the p-channel off, while when the input is low, Figure 7.1. Transistor and thyristor drive requirements: (a) current drive for the bipolar junction thyristor and (b) voltage drive for the the p-channel turns on and the n-channel turns off. However, cmos has a limited MOSFET and IGBT. current output capability as shown in the source-to-sink output characteristics in figure 7.3b and c. The cmos gate output has to drive as a load the power MOSFET capacitive Power electronics 146 147 Driving transistors and thyristors gate. In this configuration, the turn-on current is supplied from the p-channel fet, which has the poorer characteristics of the cmos pair. The turn-off current is sunk by the n- channel fet. Table 7.1 shows cmos typical current source and sink capabilities, switching speeds, and output impedance. It will be seen that the best performance, by far, is achieved from the 4049 and 4050 buffers. Figure 7.2. Gate drive circuits for the MOSFET and IGBT: (a) driven from cmos; (b) driven from cmos and an emitter follower; (c) driven from ttl with pull-up resistor which increases sourcing capability; (d) driven from open collector ttl with an external current source; (e) driven from a high-current cmos clock driver; (f) opto-isolated driver circuit; (g) drive circuits for a totem pole connected p and n-channel MOSFET leg; (h) driven from a pulse transformer; and (i) fibre optic translation stage. If shorter delays and faster drain rise and fall times are required there are several ways to obtain them. The simplest is to parallel a number of identical cmos inputs and outputs as shown dotted in figure 7.2a. The additional current capability, with the six parallel connected gates of the 4049, will significantly improve MOSFET switching performance. dv/dt=15kV/µs In figure 7.2b the gate drive current is the output current of the cmos gate multiplied by td>=0.1µs io=±2A the gain β of the bipolar transistors. No bipolar saturation times are incurred since the 15V-30V transistors are operating as emitter followers, which cannot saturate. The operating frequency is no longer restricted by the cmos output current limitations. MOSFETs can also be driven directly from ttl gates. Table 7.2 shows ttl typical current source and sink capabilities and switching speeds. Low supply voltage, typically 5V, and high internal sourcing impedance characteristics, restrict MOSFET switch-on speed HCPL3210 and gate voltage level. The ttl sink capability is significantly higher than source capability, hence a pull-up resistor as shown in figure 7.2c enables the sinking Power electronics 148 149 Driving transistors and thyristors capability to be exploited at turn-on, as well as at turn off. A limitation of using ttl for driving MOSFETs is that the gate voltage is restricted to less than 5V, hence if the drain current is not to be restricted, low gate threshold voltage trench gate MOSFETs and IGBTs are used. An open collector ttl drive technique as shown in figure 7.2d overcomes the gate voltage limitation as well as improving the current source limit. (a) (b) (c) Figure 7.3. CMOS inverter output: (a) output cmos totem pole; (b) p-channel drain sourcing; and (b) n-channel drain sinking, both at 25°C. Power electronics 150 151 Driving transistors and thyristors Very fast switching speeds are attained with the capacitive driver shown in figure 7.2e. Such drivers can both source and sink typically 1.5 A in tens of nanoseconds. An isolated gate-to-source drive version is shown in figure 7.2f, where a floating 15 V rail is used and the gate control signal is optically transmitted with high dv/dt capability. The driver incorporates high current output, with modest propagation delays. Drive circuits for p-channel MOSFETs may be complicated by the reference signal voltage level, as shown in the series n and p-channel totem pole in figure 7.2g. This figure illustrates how the p-channel drive may be derived by means of a level shifter. The emitter follower, pnp transistor used for turn-on must have a breakdown voltage rating in excess of the totem pole rail voltage. Above 300 V the pnp transistor can be replaced by a diode as shown in figure 7.2d, or a low current high voltage MOSFET. Restricted charging of the translation MOSFET output capacitance can lead to increased delay times. The resistor divider, R1-R2, ensures that the p-channel gate voltage limit is not exceeded. In order to increase gate drive capability R2 can be decreased provided a 15 V Zener is used across the p-channel MOSFET gate to source. The low-voltage npn transistor in the p-channel driver stage is used for fast turn-off, shorting the p-channel source to its gate. A simple method of driving an n-channel MOSFET, with its source not referenced to ground, is shown in figure 7.2h. Electrical (galvanic) isolation is achieved by means of a pulse transformer. The internal parasitic diode in Q1 provides the path for the n- channel MOSFET gate to charge. When the pulse transformer saturates, Q1 blocks any discharge of the gate until turn-off, when a negative transformer pulse turns on Q1, thereby discharging the n-channel gate charge. An alternative translation method using a fibre optic stage is shown in figure 7.2i. The temperature-independent, high threshold characteristics of 74AC technology is used for a simple detector comparator. A Schmitt input (hysteresis) gate improves noise immunity. Translation from ttl levels can be achieved with Zener diode bias circuits. From the circuits in figure 7.2 it is seen that there are two basic types of gate drives.