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A New Self-Firing MOS-Thyristor Device : Optimization of the Turn-Off Performanceand Experimental Results

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A New Self-Firing MOS-Thyristor Device : Optimization of the Turn-Off Performanceand Experimental Results A new self-firing MOS-Thyristor device : optimization of the turn-off performanceand experimental results M. Breil, J-L. Sanchez, P. Austin, J-P. Laur Laboratoire d'Analyse et d'Architecture des Systemes du CNRS (LAAS-CNRS) Toulouse, FRANCE Abstract: In this paper, a new integrated self-firing and controlled turn-off MOS-thyristor structure is investigated. An analytical model describing the turn-off operation and parasitic latch-up has been developped, allowing to highlight and optimize the physical and geometrical parameters acting upon main electrical characteristics. The analytical modelis validated by 2D simulations using PISCES. The technological fabrication process is optimized by 2D simulations using SUPREM IV. Electrical characterization results of fabricated test structures are presented. Keywords : high voltage integrated switch, functional integration, MOS-thyristor associations, high voltage MOS-thyristor technological process, Z.V.S applications. INTRODUCTION In the field of power electronics, numerous applications using resonant converters are based on the Zero Voltage Switching mode (ZVS). For applications in the 800-1400 Volts voltage range, the use of a thyristor structure provides very low on-state voltage drops because of its two injecting junctions. Using the concept of functional integration [1,2], it is very interesting to develop MOS-thyristor devices which can be automatically turned on upon zero voltage crossing and have a controlled turn-off. The spontaneously-firing operation and the controlled turn-off are obtained by integrating MOS sections in a thyristor structure. Thus, MOS-gated thyristor structures such as MCT [3], BRT [4], EST [5], DGMOT [6] are of great interest because a MOS gate provides high input impedance and simple driving capability. In this paper, a self-firing and controlled turn-off MOS-thyristor structure [7] for ZVS applications is designed and optimized. An N-channel depletion mode MOSFET allows the thyristor to be turned on. Turn-off is achieved by an NMOS transistor so that the device relies on a four-layered structure, which can be fabricated using an IGBT like process. An analytical model has been developed [7] in order to optimize the turn-off performance of this MOS-thyristor device. The analytical results are compared with numerical data obtained from the 2D device simulator PISCES. The technological steps of the fabrication process are defined using SUPREM IV and experimental results allow to validate this optimization. DEVICE STRUCTURE AND OPERATION A cross-sectional view of the device structure is shown in Fig. 1 and a simple equivalent circuit representation is given in Fig. 2. The device consists of a vertical thyristor including an N-channel depletion mode MOSFET Ml and an N-channel enhancement mode MOSFET M2. (M2) (Ml) Cathode _ VG1=° K N+ Anode Parasitic thyristor Main thyristor Figure 1 : Cross section of the device structure DISCLAIMER Portions of this document may be illegible in electronic image products. Images are produced from the best available original document. Parasitic thyristor Main thyristor Figure 2 : Equivalent circuit of the structure Turn-on operation When the anode voltage is positive relative to the cathode, the drain current of the N-channel depletion mode MOSFET allows the thyristor to be turned on. Electrons from the cathode flow through the preformed channel into the N" drift region providing the base current of the PNP transistor, holes are injected from the P+ anode into the drift region and collected in the P-base by the reverse biased P-base/N" junction. The holes collected below the turn-on gate region flow laterally into the P-base region and spontaneously produce a voltage drop that is sufficient to forward bias the P/N+ junction of the N+PN section. Then the KfPN transistor begins to inject electrons into the P-base region so that the regenerative action of the thyristor sets in and the thyristor latches up. The spontaneous turn-on operation has been simulated using PISCES and the electrical characteristic is shown in Fig. 3. 120 _ Anode-cathode voltage Vak (V) Fig. 3 : Tum-on characteristic obtained from PISCES Turn-offoperation A positive bias applied to the gate of the lateral MOSFET M2 turns it on and a short occurs between the N+ emitter and the P-base through a floating metal. Then the device turns off. Integration of the lateral MOSFET requires an additional N+ region to form its drain. This constitutes the emitter of a vertical parasitic thyristor which may occur when applying the turn-off command of the main thyristor. The P+ region shorted with the drain of M2 (short named C.C. in Fig. 1) desensitizes this parasitic thyristor. DEVICE OPTIMIZATION cathode 0 5 10 15 20 25 30 Microns Figure 4 : Current flowlines during the turn-off phase (obtained from PISCES) An analytical model based on the equivalent circuit representation (Fig. 5) corresponding to the turn-off phase has been presented [7]. This model, which carefully takes into account the various current components (Fig. 4) in the different portions of the cross-section, allows calculation of the maximum turn-off current density and the parasitic thyristor latching current density as a function of the geometrical and technological parameters. Analytical model of the maximum turn-off current density For applications, it is essential that the device be able to turn-off a high current density when the gate bias is applied to the turn-off MOSFET M2 (while having a low holding current density in the absence of the gate bias). The maximum turn-off current density of the thyristor, or the maximum controllable current density, is defined as the highest current density that can be tumed-off by applying the gate bias to the MOSFET M2. The magnitude of this current density depends not only upon the MOSFET M2 channel resistance but also upon the design of the device cell because of additional resistances in the turn-off path. The analytical model we present in this paper is based on the equivalent circuit representation corresponding to the turn-off phase (Fig. 5) and rigorously takes into account all the various current components in the different portions of the cross-section of the structure (Fig. 6) [4]. K V (x=0) Fig. 5 : Equivalent circuit of the structure used for modeling the turn-off current density VG2 » Vn Cathode <*lJA N+ (1-«I)Ja Anode Figure 6 : Direction of current flow when applying the gate bias to the turn-off MOSFET M2. When the main thyristor is in its ON-state mode of operation, and when the gate bias is applied to the MOSFET M2, it shorts the P-base region and the cathode region. It reduces the current gain of the NPN transistor, increasing the holding current of the thyristor. The device enters its turn-off phase when the holding current is higher than the conduction current. The short resistance between the P-base and the cathode regions is made up of the ON resistance cf MOSFET M2, the P+ region resistance, the P-base resistance that can be separated into three terms (corresponding to the region situated under the N+ emitter, to the region under the turn-off MOSFET channel and finally to that under the drain region of M2). So, the highest voltage developed in the P region is the one which is the furthest from the short. This is why the voltage developed in the P-base region must be calculated at x=0 : j*L 2 (*L2+L ch2 j* L2 + Lch2 + L0 j»L2 + L,+L4 v (x = 0) = «!jaPs2(L, +x)dx+ ttiJAActLi+x)dx+ a,JAps3(L, +x)dx+ a,JAps4(L, +x)dx + VMQS2 ° Ll *^ L2+Lch2 *T-2 +L3 (1) Where : - JA (A/cm2): anode current density, - ps2 (Q/D): sheet resistance of P-base under N+ emitter - psc (Q/D): sheet resistance of P-base under MOSFET M2 channel, - pS3 (Q/D): sheet resistance of P-base under N+ drain region of MOSFET M2, - pS4 (£2/D): sheet resistance of P+ base under N+ drain region of MOSFET M2, - «i : current gain of the PNP transistor, - Vm0S2 (V): voltage drop accross MOSFET M2, which is given by : 0fiJAXLch2 VMOS2 - Ron lMOS2 — P-on <Z] J azX ' ^invQx(%32 ~ VT2) (2) Here, X is the half-cell width (cm), z the device length in z direction (cm), pinv the inversion layer mobility of the channel (cm2/(v.s)), Cox the gate oxide capacitance (F/cm2), VG2 and VT2 the gate bias and the threshold voltage respectively of MOSFET M2 (V). By integrating equation (1) and by substituting equation (2) into equation (1), the potential drop at x=0 is obtained : Ps2L2 <L1 + -----) 2 "*ch2 + PscLch2 (L1 + L2 + + Ps3L0(Li + L2 + Lch2 + °) V 0H>) “ alJA A + Ps4^4 (Iq + L2 + L3 + ) _ Pinv Cox (VG2 VT2^ (3) The maximum turn-off current density can be calculated using the above equation by assuming that the potential V(x=0) where the P/N+ junction stops being forward biased is 0.7 V. Then the maximum turn-off current density is given by : T______________________ 0/7 ____________________ max ’ l L Ps2L2(L1 +/T') + PscLch2(Ll +L2 +~r^) z l +Ps3Lo(Ll +L2 +Lch2 +_^") +ps4L4(Li +l2 +l3 + -~) 1 Lch2X 2 Pinv Cox( VG2 _ VT2 ) (4) Optimizing the turn-off performance Equation (4) allows calculation of the maximum turn-off current density as a function of the geometrical and technological parameters, highlighting those that mainly act upon turn-off performance. For each calculation, only one parameter is varied, while all the others are kept unchanged as in the baseline device. These reference values are : L2=15 pm, Lch2=2 pm, L4+L5=8 pm, L0=5 pm, L,=5 pm, L5=3.4 pm, CsP=4* 1017 cm-3 (surface concentration in the P region), CsP+=T.2*10 19 cm-3 (surface concentration in the P+ region).
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