A new self-firing MOS-Thyristor device : optimization of the turn-off performanceand experimental results
M. Breil, J-L. Sanchez, P. Austin, J-P. Laur Laboratoire d'Analyse et d'Architecture des Systemes du CNRS (LAAS-CNRS) Toulouse, FRANCE
Abstract: In this paper, a new integrated self-firing and controlled turn-off MOS-thyristor structure is investigated. An analytical model describing the turn-off operation and parasitic latch-up has been developped, allowing to highlight and optimize the physical and geometrical parameters acting upon main electrical characteristics. The analytical modelis validated by 2D simulations using PISCES. The technological fabrication process is optimized by 2D simulations using SUPREM IV. Electrical characterization results of fabricated test structures are presented. Keywords : high voltage integrated switch, functional integration, MOS-thyristor associations, high voltage MOS-thyristor technological process, Z.V.S applications.
INTRODUCTION In the field of power electronics, numerous applications using resonant converters are based on the Zero Voltage Switching mode (ZVS). For applications in the 800-1400 Volts voltage range, the use of a thyristor structure provides very low on-state voltage drops because of its two injecting junctions. Using the concept of functional integration [1,2], it is very interesting to develop MOS-thyristor devices which can be automatically turned on upon zero voltage crossing and have a controlled turn-off. The spontaneously-firing operation and the controlled turn-off are obtained by integrating MOS sections in a thyristor structure. Thus, MOS-gated thyristor structures such as MCT [3], BRT [4], EST [5], DGMOT [6] are of great interest because a MOS gate provides high input impedance and simple driving capability. In this paper, a self-firing and controlled turn-off MOS-thyristor structure [7] for ZVS applications is designed and optimized. An N-channel depletion mode MOSFET allows the thyristor to be turned on. Turn-off is achieved by an NMOS transistor so that the device relies on a four-layered structure, which can be fabricated using an IGBT like process. An analytical model has been developed [7] in order to optimize the turn-off performance of this MOS-thyristor device. The analytical results are compared with numerical data obtained from the 2D device simulator PISCES. The technological steps of the fabrication process are defined using SUPREM IV and experimental results allow to validate this optimization.
DEVICE STRUCTURE AND OPERATION A cross-sectional view of the device structure is shown in Fig. 1 and a simple equivalent circuit representation is given in Fig. 2. The device consists of a vertical thyristor including an N-channel depletion mode MOSFET Ml and an N-channel enhancement mode MOSFET M2.
(M2) (Ml) Cathode _ VG1=°
K N+
Anode
Parasitic thyristor Main thyristor
Figure 1 : Cross section of the device structure DISCLAIMER
Portions of this document may be illegible in electronic image products. Images are produced from the best available original document. Parasitic thyristor Main thyristor Figure 2 : Equivalent circuit of the structure Turn-on operation When the anode voltage is positive relative to the cathode, the drain current of the N-channel depletion mode MOSFET allows the thyristor to be turned on. Electrons from the cathode flow through the preformed channel into the N" drift region providing the base current of the PNP transistor, holes are injected from the P+ anode into the drift region and collected in the P-base by the reverse biased P-base/N" junction. The holes collected below the turn-on gate region flow laterally into the P-base region and spontaneously produce a voltage drop that is sufficient to forward bias the P/N+ junction of the N+PN section. Then the KfPN transistor begins to inject electrons into the P-base region so that the regenerative action of the thyristor sets in and the thyristor latches up. The spontaneous turn-on operation has been simulated using PISCES and the electrical characteristic is shown in Fig. 3.
120 _
Anode-cathode voltage Vak (V) Fig. 3 : Tum-on characteristic obtained from PISCES Turn-offoperation A positive bias applied to the gate of the lateral MOSFET M2 turns it on and a short occurs between the N+ emitter and the P-base through a floating metal. Then the device turns off. Integration of the lateral MOSFET requires an additional N+ region to form its drain. This constitutes the emitter of a vertical parasitic thyristor which may occur when applying the turn-off command of the main thyristor. The P+ region shorted with the drain of M2 (short named C.C. in Fig. 1) desensitizes this parasitic thyristor.
DEVICE OPTIMIZATION
cathode
0 5 10 15 20 25 30 Microns Figure 4 : Current flowlines during the turn-off phase (obtained from PISCES) An analytical model based on the equivalent circuit representation (Fig. 5) corresponding to the turn-off phase has been presented [7]. This model, which carefully takes into account the various current components (Fig. 4) in the different portions of the cross-section, allows calculation of the maximum turn-off current density and the parasitic thyristor latching current density as a function of the geometrical and technological parameters.
Analytical model of the maximum turn-off current density For applications, it is essential that the device be able to turn-off a high current density when the gate bias is applied to the turn-off MOSFET M2 (while having a low holding current density in the absence of the gate bias). The maximum turn-off current density of the thyristor, or the maximum controllable current density, is defined as the highest current density that can be tumed-off by applying the gate bias to the MOSFET M2. The magnitude of this current density depends not only upon the MOSFET M2 channel resistance but also upon the design of the device cell because of additional resistances in the turn-off path. The analytical model we present in this paper is based on the equivalent circuit representation corresponding to the turn-off phase (Fig. 5) and rigorously takes into account all the various current components in the different portions of the cross-section of the structure (Fig. 6) [4].
K
V (x=0)
Fig. 5 : Equivalent circuit of the structure used for modeling the turn-off current density
VG2 » Vn Cathode
<*lJA N+ (1-«I)Ja
Anode
Figure 6 : Direction of current flow when applying the gate bias to the turn-off MOSFET M2. When the main thyristor is in its ON-state mode of operation, and when the gate bias is applied to the MOSFET M2, it shorts the P-base region and the cathode region. It reduces the current gain of the NPN transistor, increasing the holding current of the thyristor. The device enters its turn-off phase when the holding current is higher than the conduction current. The short resistance between the P-base and the cathode regions is made up of the ON resistance cf MOSFET M2, the P+ region resistance, the P-base resistance that can be separated into three terms (corresponding to the region situated under the N+ emitter, to the region under the turn-off MOSFET channel and finally to that under the drain region of M2). So, the highest voltage developed in the P region is the one which is the furthest from the short. This is why the voltage developed in the P-base region must be calculated at x=0 : j*L 2 (*L2+L ch2 j* L2 + Lch2 + L0 j»L2 + L,+L4 v (x = 0) = «!jaPs2(L, +x)dx+ ttiJAActLi+x)dx+ a,JAps3(L, +x)dx+ a,JAps4(L, +x)dx + VMQS2 ° Ll *^ L2+Lch2 *T-2 +L3
(1) Where : - JA (A/cm2): anode current density, - ps2 (Q/D): sheet resistance of P-base under N+ emitter - psc (Q/D): sheet resistance of P-base under MOSFET M2 channel, - pS3 (Q/D): sheet resistance of P-base under N+ drain region of MOSFET M2, - pS4 (£2/D): sheet resistance of P+ base under N+ drain region of MOSFET M2, - «i : current gain of the PNP transistor, - Vm0S2 (V): voltage drop accross MOSFET M2, which is given by :
0fiJAXLch2 VMOS2 - Ron lMOS2 — P-on Ps2L2 + Ps3L0(Li + L2 + Lch2 + °) V 0H>) “ alJA A + Ps4^4 (Iq + L2 + L3 + ) _ Pinv Cox (VG2 VT2^ (3) The maximum turn-off current density can be calculated using the above equation by assuming that the potential V(x=0) where the P/N+ junction stops being forward biased is 0.7 V. Then the maximum turn-off current density is given by : T______0/7 ______max ’ l L Ps2L2(L1 +/T') + PscLch2(Ll +L2 +~r^) z l +Ps3Lo(Ll +L2 +Lch2 +_^") +ps4L4(Li +l2 +l3 + -~) 1 Lch2X 2 Pinv Cox( VG2 _ VT2 ) (4) Optimizing the turn-off performance Equation (4) allows calculation of the maximum turn-off current density as a function of the geometrical and technological parameters, highlighting those that mainly act upon turn-off performance. For each calculation, only one parameter is varied, while all the others are kept unchanged as in the baseline device. These reference values are : L2=15 pm, Lch2=2 pm, L4+L5=8 pm, L0=5 pm, L,=5 pm, L5=3.4 pm, CsP=4* 1017 cm-3 (surface concentration in the P region), CsP+=T.2*10 19 cm-3 (surface concentration in the P+ region). Junction depths for N+, P and P+ regions are : XjN+=l,25 pm, XjP=4,3 pm and XjP+=5 pm. The N" drift region exhibits a resistivity of 40 £2.cm and a thickness of 270 pm. The gate bias applied for the turn-off command is 20 V and the gate oxide thickness is 550 A. The behaviour of the turn-off characteristics as a function of various device parameters is discussed. The analytical model is corroborated with 2D simulations using PISCES. Optimization of the turn-off performance relies on the decrease in the entire P+ and P base resistance. • The turn-off current density is found to decrease when the cathode length L2 is increased, as shown in Fig. 7. It clearly appears that turn-off current density is reduced by half when the cathode length increases from 15 to 27 pm. This is due to an increase in the P-base resistance with increasing N+ emitter length. Then, the current required to sustain the forward bias across the N+/P junction is reduced and the turn-off current density decreases. —•— Analytical results b-- 2D simulation results Cathode length : L (|im) Figure 7 : Calculated and simulated maximum turn-off current densities versus cathode length. • The P base region should have a small sheet resistance (ps2, psc, ps3 parameters). For the junction depths fixed by the device fabrication process, doping of the P region has to be increased. However Fig. 9 clearly shows that, for a given junction depth of the P base region, there exists a surface concentration optimal value. In fact, an increase in the surface concentration of the P region results in an increase in the threshold voltage of the turn-off MOSFET (Fig. 8) and thus, an increase in its ON-state resistance, which has to be reduced as much as possible. So, two opposite effects act upon the behaviour of the turn-off current density when increasing surface concentration. For a junction depth of the P base region equal to 4.3 pm, the optimal value of surface concentration is found to be close to 9.1017 cm* 3, corresponding to a threshold voltage of MOSFET M2 of 9.3V (Fig. 11(b)), which is much higher than the usual threshold voltage range of a conventional MOSFET (about 3 or 4 V). Surface concentration in the P region : C (At./cm3) Figure 8 : Simulated threshold voltage versus surface concentration in the P region. 1 80 -4- Analytical results 2D simulated values Surface concentration in the P base region : C_p (At./cm3) Figure 9 : Calculated and simulated maximum turn-off current densities versus surface concentration in the P base region. —X =4,3 gm X =5 gm ■X =6 gm -X =8 gm Surface concentration in the P base region : C (At./cm3) Figure 10 : Maximum turn-off current density versus surface concentration in the P base region. Calculated values for different junction depths of the P region. It is worth pointing out that this optimal value corresponding to 200 A/cm2 can be improved by increasing the P junction depth, as shown in Fig. 10. It reduces the P-base resistance (see Fig.l 1), and then increases the turn-off current level. The term due to the P-base resistance ((pP) and the term due to the equivalent resistance to the turn-off MOSFET channel (tpwosz) can be expressed as : Pp = Ps2L2j L! + -y-j + PscLch2^Ll + L2 + -y-j + Ps3Lo(Li + L2 + Lch2 + "y +PS4L4^L| + L2 + Lj + -y (ID ^-Ch2^ <5°MOS2 - PinvC ox (VG2 VT2) (12) tp? and (pwos2 are both represented versus surface concentration in the P region and threshold voltage cf MOSFET M2 (Fig. 11). As the term due to the channel equivalent resistance keeps the same variation profile when increasing the P region junction depth, the optimal point is obtained for a lower surface concentration in the P region (Fig. 11(a)), allowing to obtain lower threshold voltage of the lateral MOSFET (Fig. 11(b)). However there exists a limit to the increase in the junction depth, where the cell size should be increased, so that the turn-off current density decreases. Optimization results concerning the P region junction depth are reported in Table 1. MOS2V(X jP"=8 um) (X =6 gm) Surface concentration in the P base region : C_p (At./cm3) (a) ,=4,3 pm and X =5 jun ) Threshold voltage of turn-off MOSFET : Vy2 (V) (b) Figure 11 : Term due to the P base resistance (cpp) and term due to the equivalent resistance to the turn-off MOSFET channel ( P region junction depth : XjP (pm) 4,3 5 6 8 half-cell width : X (pm) 35 35 36 38 Surface concentration in the P region : 9.10" 6 ,6 .10" 4,5.10" 3,1.10" Csp (At./cm3) P region optimal dose (At./cm') 1,16. 1014 9,85.10" 8,2.10" 7,5.10" sheet resistance of the P base under the 1130 870 700 525 cathode region ps2 (£2/111) Threshold voltage of MOSFET M2 : V-n 9,3 7,9 6,6 5,5 (V) Maximum turn-off current density 190 235 285 310 optimal value : Jmax (A/cm2) Table 1 : Evaluation of the maximum turn-off current density optimal value for different junction depths (analytical results) • The resistance of the P+ region has to be as low as possible in order to improve the short between the N+ drain and the P+ base region. This can be achieved by increasing the doping of the P+ region (i.e reducing the parameter) and/or reducing the L0 P-base segment relative to the merged P+ diffusion region under the N+ drain (L4 segment). The effect of the first solution upon the maximum turn-off current density can be observed in Fig. 12(a), but it can also be seen in Fig. 12(b) thatthe increase in Jmax due to a larger P+ region is more sensitive. The turn-off current density increases by 30 % when the P+ region length (L4+L5) is increased from 4 to 12 pm. ----- Analytical results —b— 2D simulation results Surface concentration in the P+ region (At./cm3) (a) 220 2D simulation results i Analytical results I I i E i s P+region length : L,+L5 (pm) (b) ------Analytical results —b— 2D simulation results Channel length of turn-off MOSFET M2 : L^(pm) (c) Figure 12 : Calculated and simulated maximum turn-off current densities versus surface concentration in the P+ region (a), versus P+ length (b) and channel length (c). • In Fig. 12(c), the turn-off current density appears highly dependent upon the turn-off channel length : it increases by 25 % with a decrease in channel length from 4 to 2 pm. Of course, the voltage drop across MOSFET M2 has to be reduced. Worthy of note is the good agreement between the calculated values and the simulated data. To conclude, the most important parameters for optimizing the turn-off device performance are : cathode length, surface concentration in the P region for a given junction depth (sheet resistance of the P region), channel length and threshold voltage of the lateral turn-off MOSFET, sheet resistance and length of the P+ region. Modeling the parasitic latching current density As mentioned above, this four-layered structure contains a parasitic thyristor. Considering the phase in which the main thyristor is in the forward conduction mode, a positive bias is applied to the turn-off MOSFET to turn it on so that the parasitic thyristor emitter is connected to the device cathode and the parasitic region operates like an IGBT. Thus, at high current level, the current flowing under the N+ drain can forward bias the junction fonned by the N+ drain and the P region, resulting in the latch-up of the parasitic thyristor. Gate control over the thyristor current is then lost. The parasitic latching level is higher than the main thyristor latching level because of the short between the N+ drain and the P region, but this can degrade the turn-off performance of the device if the structure is not well-optimized. Thus, this study also led us to the establishment of the latch-up condition of the parasitic thyristor as a function of the device parameters. Optimizing these parameters allows to desensitize the parasitic thyristor relative to the main thyristor and to increase highly its latch-up current level beyond the maximum turn-off current level of the main thyristor. VG2 » VT2 Cathode > P+ l5 ' L4 , Lo ,Lch2 Anode IGBT region Thyristor region Figure 13 : Direction of current flow during the turn-off phase. Considering the phase in which the main thyristor is in the forward conduction mode, a positive bias is applied to the turn-off MOSFET to turn it on so that the parasitic thyristor emitter is connected to the device cathode and the parasitic region operates like an IGBT. The parasitic latching current density is the anode current density at which the N+PN transistor of the parasitic thyristor begins to inject electrons into the P base region. The current flowing through the thyristor region (1) (corresponding to segment L]+L2) and the IGBT region (2) (corresponding to segment L3+L4+L5) can be written as : I] = Ji(Lj + L2)z (7) I2 = J2(L3+L4+L5)z (8) Where J, and J2 are the anode current densities in regions (1) and (2) respectively (see Fig. 13). Using the same kind of analysis as that related to the maximum turn-off current density, the potential drop developed in the p base region at x=0 (corresponding to the point where the parasitic phenomenon may first occur) is given by : ( \ eNPN1 V a,I, (L, + L2) - (1 - a2) Pd +a,J2(Lcll2 + x) (9) Where cq is thecurrent gain of the PNP transistor forming the main thyristor after latch-up and 012 the current gain of the NPN transistor forming the main thyristor. The first two terms in each integral are due to the P base current in the region of the main thyristor (1). The third term accounts for the P base current due to the IGBT region (2). We note that : IEnpn , = -Imos2- Otherwise, the collector current of the NPN transistor, or the base current of the PNP transistor, can be expressed as : ^NPNl ^ “zIenpn, =_0f2iMOS2 = (1~ «l)(Il +h) (10) Then, the current flowing through the lateral MOSFET M2 can be written as : (1 - «i)(Ii +12) MOS2 “2 (11) Considering eqns (4) and (5) and assuming that the current density close to the P+/N junction is uniform (J]=J2=JaX the following relationship is obtained : 2 (12) Then integrating equation (9), the voltage developed in the P base region is given by : Ps3Lo(L1 + L2 + Lch2 + —) OC] jjZ (x=0) +Ps4L4(L1 + L2 + Lj +_~) (13) “2 The parasitic thyristor will turn-on when the junction formed by the N+ drain region and the P base region becomes sufficiently forward biased (V (x =0) = 0.7 V ). Based on this, the parasitic latching current density of our four-layered structure can be calculated : 0.7 J LP ’ (14) Ps3 Lo( Li + L2 + Lch2 +-^) Of] +Ps4L4(L1 + L2 + L3 + —) a2 Desensitizing the parasitic latch-up Using equation (14), the variation of the parasitic latching current density as a function of the device geometrical and material parameters can be predicted. The effects of varying the surface concentrations in the P and P+ regions and the N+ drain region length (in particular the length of the merged P+ region under the N+ drain) are calculated by changing the ps3, ps4, L0 and L4 parameters. For each parameter variation, the other parameters are kept equal to the reference values, as explained before. Figs. 14 show that the P-base resistance, involved in the short resistance between base and cathode, has to be reduced to increase the parasitic latching current level. This can be achieved by choosing shorter cathode lengths (Fig. 14(a)) or increasing doping in the P region (Fig. 14(b)). Even more, increasing the P junction depth (for a given doping level of the P region) rises the parasitic latching current level because it reduces the P- base sheet resistance (ps3 and p„ parameters). The parasitic latch-up can also be desensitized by reducing as much as possible the injection efficiency cf the N+P+N transistor. Thus, a higher parasitic latch-up level is obtained with a highly doped P+ region (Fig. 15(b)) and with an increase in the merged P+ region length under the N+drain region (Fig. 15(a)). We must point out that the high latch-up level obtained from a P+ region length of 12 pm is difficult to achieve without affecting the channel region doping. Figs. 14(b) and 15(b) show that changing surface concentration in the P region is even more important than in the P+ region. 1100 ioooy Cathode length : L2 (pm) (a) 2500 I g I? Surface concentration in the P region : Csp (At./cm3) (b) Figure 14 : Parasitic latching current density versus cathode length (a) and versus surface concentration in the P region (b). Calculated values for two different P region junction depths. 4000 3500 3000 2500 2000 1500 1000 P+ region length: L4+L$ (pm) (a) —X P=4,3 pm, X =5 pm X =5 pm, X =5,7 pm Surface concentration in the P+ region : Csp+ (At./cm3) (b) Figure 15 : Parasitic latching current density versus P+ region length (a) and surface concentration in the P+ region (b). Calculated values for two different P region junction depths. The main parameters found to be optimized to avoid the parasitic latch-up are : the P region depth and doping, and the P+ region length as well. For a P junction depth equal to 5 pm, for the optimal surface concentration (cf Fig. 10), for a P+ surface concentration of 1019 cm"3 and a P length of 10 pm, the latching current density is higher than 1500 A/cm2 (six times higher than the maximum turn-off current density). Parameters optimization and structure design The technological constraints allow us to obtain a N+ junction depth of 1.25 pm. We opted for a P junction depth of 5 pm. The turn-off performance optimization should then lead to a P-base surface concentration value of 7. 1017 cm"3, corresponding to a threshold voltage of 8 V. Then the optimal P sheet resistance (ps2) under the cathod region is about 870 Q/D, corresponding to a final implanted dose of 1014 cm"2. Then the maximum turn-off current density should be 230 A/cm2, without any risk cf parasitic latch-up. Figs 12(a) and 15(b) indicate that the surface concentration in the P+ region must be at least 1019 cm"3. The P+ region has to be merged under the N+ drain region as closed as possible to the bi- channel region. Finally, this N-channel should not be larger than 2 pm. FABRICATED TEST DEVICES AND EXPERIMENTAL RESULTS Based upon these considerations, in order to obtain these parameters leading to the optimized performance, the technological steps of the fabrication process have been defined using SUPREM IV. The boron implanted dose is 4.1014 cm"2. For this dose, the arsenic implant dose has been adjusted to form the N-channel, which provides the turn-on current of the thyristor. Using the design rules defined in Fig. 16, test devices with different cathode lengths (Table 2) have been fabricated, from a high voltage MOS- bipolar technological process based on 9 mask levels and a multicellular parallel strips geometry (Fig. 17). The gate oxide thickness is 555 A. Preformed N-channel mask fn°6 ) Figure 16 : Design rules (for the 66 pm cell) Mask cell width (pm) 42 58 78 Mask intercellular distance (pm) 50 50 50 Mask cathode length (pm) 8 12 20 Mask channel length (pm) 4 4 4 Final cell width (pm) 50 66 86 Final intercellular distance (pm) 42 42 42 Final cathode length (pm) 10 14 22 Final channel length (pm) 2 2 2 Table 2 : Main geometrical characteristics of the technological process Figure 17 : multicellular parallel strips geometry (MEB) Fig. 18: Microsection of the MOS-thyristor structure (M.E.B.) Figure 19 : device I(V) static characteristic ■ Figure 20 : Current and voltage characteristics during turn-off phase 1 80 • • 1 1 i i .1 1 ' ■ Experimental results | ■ 160 ■F 140 "C E 120 1 1 00 I 8 0 6 0 .h ■ • i —■ ' L-■ . ■ ■ 1 . . . i ■ . ■ i ■■ 10 12 14 16 18 20 22 24 Cathode length : L^fim) Figure 21 : Experimental maximum turn-off current density versus cathode length. Physical characterization results (Fig. 18) show the presence of the preformed channel. The P+ region has almost diffused up to the MOSFET M2 channel region, as it was predicted by the theorical optimization. The spontaneous turn-on function is verified (Fig. 19). The threshold voltage of MOSFET M2 is found to be 8 V. We also check the turn-off operation (Fig. 20) (the gate bias applied to MOSFET M2 is 20 V) and present the maximum turn-off current density as a function of cathode length (Fig. 21), corroborating the analytical and 2D simulation results. CONCLUSION A new self-firing MOS-thyristor device is optimized in this paper. The analytical model describing the turn-off behavior has highlighted the technological and geometrical parameters that have to be optimized to arrive at a good design of the device structure. In fact, the most important parameters for the optimization of the turn-off device performance are the cathode length, surface concentration in the P region for a given junction depth (sheet resistance of the P region), channel length and threshold voltage of the lateral turn-off MOSFET, sheet resistance and length of the P1" region. It has been shown that there exists an optimal value for the surface concentration in the P region, which is an important feature for the device design. It is also observed that a non conventional value of threshold voltage is required for the turn-off MOSFET. Otherwise, a high parasitic latch-up current level is obtained from highly doped P and P+ regions and from a high value of the merged P+ region length. But the doping increase of the P region has to be limited because of the optimal value of thesurface concentration in the P region observed in the turn-off current variation profile. The effect of parametric variations upon the turn-off characteristics taken into account in the model have been corroborated by the simulated data obtained from PISCES. Test devices with different cathode lengths have been fabricated using a high voltage MOS-bipolar technological process based on 9 mask levels and a multicellular parallel strips geometry. SUPREM IV 2D simulations allowed us to define the technological steps leading to the optimized parameters. Turn-on and turn-off operations have been verified. Analytical and simulated trends are confirmed by the characterizations. In particular, we show that cathode length has to be reduced as much as possible to obtain a high turn-off current density. References [1] Sanchez, J-L., Austin, P. , Berriane, R., Marmouget, M. : Trends in design and technology for new power integrated devices based on functional integration, European Power Electronics and Applications (EPE’97), Trondheim (Norway), September 8-10, 1997, Vol. 3, pp. 1302-1307. [2] Pezzani, R.; Quoirin, J-B. : « Functional integration of power devices : a new approach », 6 th European Conference on Power Electronics and Applications (EPE’95), Sevilla (Spain), September 19-21, 1995 [2] Temple, V.A.K. : MOS Controlled Thyristors (MCT's), IEDM Tech, dig., 1984, pp 282. [3] Nandakumar, M., Baliga, B.J., Shekar, M.S., Tandon, S., Reisman, A. : The Base Resistance controlled Thyristor (BRT), a new MOS gated power thyristor, IEEE 1991. [4] Shekar, M.S., Baliga, B.J. : Modeling the on-state characteristics of the emitter switched thyristor, Solid- State electronics, 1994, Vol. 37, No. 7, pp 1403-1412. [5] Seki, Y., Iwamuro, N. : Dual Gate MOS Thyristor (DGMOT), ISPSD 1993, Monterey. [6 ] Breil, M., Sanchez, J-L. : Analytical model for the optimization of the turn-off performance of a self-firing MOS-thyristor device, European Power Electronics (EPE’97), Trondheim (Norway), September 8-10, 1997, Vol. 3, pp. 042-048. Address of the authors 7, Avenue du Colonel Roche, 31077 Toulouse Cedex 4, France e-mail : [email protected], [email protected]