FPGA Based Lane Tracking System for Autonomous Vehicles

Total Page:16

File Type:pdf, Size:1020Kb

FPGA Based Lane Tracking System for Autonomous Vehicles DEGREE PROJECT IN ELECTRICAL ENGINEERING, SECOND CYCLE STOCKHOLM, SWEDEN 2019 FPGA Based Lane Tracking system for Autonomous Vehicles ROHITH RAJ RAM PRAKASH KTH ROYAL INSTITUTE OF TECHNOLOGY ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Abstract The application of Image Processing to Autonomous driving has drawn significant attention in recently. However, the demanding nature of the image processing algorithms conveys a considerable burden to any conventional real- time implementation. On the other hand, the emergence of FPGAs has brought numerous facilities toward fast prototyping and implementation of ASICs so that an image processing algorithm can be designed, tested and synthesized in a relatively short period in comparison to traditional approaches. This thesis investigates the best combination of current algorithms to reach an optimum solution to the problem of lane detection and tracking, while aiming to fit the design to a minimal system. The proposed structure realizes three algorithms, namely Edge Detector, Hough Transform, and Kalman filter. For each module, the theoretical background is investigated and a detailed description of the realization is given followed by an analysis of both achievements and shortages of the design. It is concluded by describing the advantages of implementing this architecture and the use of these kinds of systems. Keywords Autonomous drive, Image processing, FPGA, Sobel Edge detector, Hough Transform. i Sammanfattning Tillämpningen av bildbehandling inom autonoma fordon har fått stor uppmärksamhet den senaste tiden. Emellertid förmedlar den krävande karaktären hos bildbehandlingsalgoritmerna en stor belastning på vilken konventionell realtidsimplementering som helst. Å andra sidan har framväxten av FPGAer medfört många möjligheter till snabb prototypering och implementering av ASICar så att en bildbehandlingsalgoritm kan utformas, testas och syntetiseras på relativt kort tid jämfört med traditionella tillvägagångssätt. Denna avhandling undersöker den bästa kombinationen av nuvarande algoritmer för att uppnå en optimal lösning på problemet med spårning och fildetektering, med målet att krympa designen till ett minimalt system. Den föreslagna strukturen realiserar tre algoritmer, nämligen Edge Detector, Hough Transform och Kalman filter. För varje modul undersöks den teoretiska bakgrunden och en detaljerad beskrivning av realiseringen ges följd av en analys av både fördelar och brister i konstruktionen. Avhandlingen avslutas med en beskrivning av fördelarna med att implementera lösningen på det sätt den görs och hur dessa system kan användas. Nyckelord Autonoma enheter, Bildbehandling, FPGA, Sobel Edge Detector, Hough Transform. ii Acknowledgements First of all, I would like to thank my Industrial supervisors Gunnar Stjernberg and Adrian Sparrenborn at Synective Labs AB who was greatly involved in all the discussions and decisions related to specifications and scope of the project. Next, I would like to extend a note of thanks to Synective Labs AB for allowing me to work on such an interesting and challenging project. I would like to thank my examiner Prof. Johnny Öberg for the constant feedback and patience. And last but not least, I would like to gratefully express my thanks and love to my family and friends who have always been supporting me unconditionally. iii Contents List of Figures vi List of Tables 1 1 Introduction 2 1.1 Background ................................ 2 1.2 Thesis Goal ................................ 2 1.3 Outline .................................. 2 2 Related Work 4 2.1 Role of FPGA in Autonomous systems ................. 4 2.2 Literature Survey on the Conventional Design Methodologies on FPGAs for image processing ....................... 4 2.3 Detection of lines ............................. 5 2.4 Detection of circles ............................ 6 2.5 Active driver assistance system ..................... 7 2.6 Sobel Edge Detection System Design and Integration on an FPGA . 8 3 Methodology 10 3.1 Edge Detection .............................. 10 3.1.1 Theory ............................... 10 3.1.2 Matlab Simulation ........................ 11 3.2 Lane Detection .............................. 12 3.2.1 Theory ............................... 12 3.2.2 Implementation ......................... 13 3.3 MATLAB Simulation ........................... 14 4 Architecture 17 4.1 Hardware Architecture of the Line Detection System . 17 4.1.1 Camera Unit ........................... 17 4.1.2 Edge Extraction Unit ...................... 18 4.1.3 Hough Transform Unit ..................... 19 4.1.4 Line Identification Unit ..................... 21 4.2 System Architecture in FPGA ...................... 24 iv 4.2.1 Camera Pass-through Design . 24 4.2.2 Sobel Edge Detector Design ................... 35 4.2.3 Hough Transform Design .................... 36 5 Result and Analysis 37 5.1 Hardware Specification ......................... 38 5.2 Hardware test and Analysis ....................... 39 5.2.1 Edge detection test ........................ 39 5.2.2 Hough Transform Test ..................... 41 5.2.3 Resource Usage ......................... 43 5.2.4 Prototype ............................. 44 6 Conclusions 45 6.1 Conclusion ................................ 45 6.2 Future work ................................ 46 6.2.1 Insights and suggestions for further work . 46 6.2.2 Cost analysis ........................... 46 References 47 A MATLAB codes 51 A.1 MATLAB code for Sobel, Canny, Roberts and Prewitt filters . 51 A.2 MATLAB code for Hough Transform . 52 v List of Figures 3.1 Image input image to the filter ..................... 11 3.2 Sobel filter ................................ 12 3.3 Canny filter ................................ 12 3.4 Roberts filter ............................... 12 3.5 Prewitt filter ............................... 12 3.6 Hough transform lines ......................... 13 3.7 Sobel filter output / Hough Transform input . 15 3.8 Hough transform space ......................... 16 3.9 Hough transform lines ......................... 16 4.1 Configuration of Line Detection System . 17 4.2 FMC-IMAGEON Hardware – Connectivity Diagram [21] . 18 4.3 FMC-IMAGEON Hardware – Block Diagram [21] . 18 4.4 Configuration of Hough Transform Unit . 20 4.5 Configuration of Peak Detector ..................... 21 4.6 The Memory Controller ......................... 23 4.7 The architecture of Camera Pass-through Block Design . 24 4.8 Channel Architecture of Reads [26] . 25 4.9 Channel Architecture of Writes [26] . 25 4.10 Block Diagram of Video In to AXI4-Stream Core with the Video Timing Controller [27] ......................... 27 4.11 RGB and CMY Bayer CFA Patterns [28] . 28 4.12 Block Diagram of Color Filter Array Interpolation [28] . 29 4.13 AXI Interconnect Core Diagram [29] . 30 4.14 AXI IIC Bus Interface Top-Level Block Diagram [30] . 31 4.15 AXI4-Stream to Video Out core with the Video Timing Controller [34] .................................... 34 4.16 The architecture of Sobel Edge filter Design . 35 4.17 The architecture of the Hough Transform Design . 36 5.1 Zedboard and FMC camera setup with JTAG programmer . 38 5.2 Implemented Sobel Edge detector in FPGA . 39 5.3 Camera pass through Implemented . 39 vi 5.4 Sobel filter implemented ........................ 40 5.5 Implemented random XY lines in FPGA . 41 5.6 Implemented random XY lines with Video stream in FPGA . 41 5.7 Implemented Hough Transform in FPGA . 42 5.8 Implemented Hough Transform in MATLAB . 42 5.9 Prototype of miniature scale Autonomous car . 44 vii List of Tables 3.1 Filter masks ................................ 10 5.1 Design resource summary ........................ 43 1 1 Introduction 1.1 Background Nowadays the role of image processing is demanded in a wide range of industry and day to day applications. Image processing units are embedded in many devices ranging from mobile phones to Autonomous cars in the streets. However, the processing speed of some complex algorithms puts a barrier in a real-world implementation. FPGAs, on the other hand, are more flexible and handles these complex algorithms better in real-time environment that make a good choice for Autonomous driving. Most autonomous cars these days use GPUs as the brain for image processing and this thesis describes the real-world implementation of FPGAs for Autonomous cars. 1.2 Thesis Goal This thesis project aims to design and implement a miniature autonomous car that can detect, track lanes and move around in a controlled environment. The challenging task is extracting the required information from a video stream, which is performed by pre-processing extraction algorithms. There are external noises in the environment in which the experiment is conducted, like lighting, uneven lane marking etc., which must be kept in mind while deciding the optimal algorithm and designing the controller for this platform. Hence it must be decided which controller design has minimal resource utilization and power consumption. 1.3 Outline • chapter 2 conveys the results of the conducted survey on the conventional approaches already practiced by the expert toward implementing lane detection on the FPGA. • chapter 3 explains the theory behind the Edge detection and Steerable filters used for Autonomous driving. Then the advantages brought to the 2 design by applying this approach along with its disadvantages is explained. Finally, the MATLAB simulations of these filters are plotted and explained. • chapter 4 explains Architecture of the design implemented in FPGA. All the
Recommended publications
  • Computer Graphics on Mobile Devices
    Computer Graphics on Mobile Devices Bruno Tunjic∗ Vienna University of Technology Figure 1: Different mobile devices available on the market today. Image courtesy of ASU [ASU 2011]. Abstract 1 Introduction Computer graphics hardware acceleration and rendering techniques Under the term mobile device we understand any device designed have improved significantly in recent years. These improvements for use in mobile context [Marcial 2010]. In other words this term are particularly noticeable in mobile devices that are produced in is used for devices that are battery-powered and therefore physi- great amounts and developed by different manufacturers. New tech- cally movable. This group of devices includes mobile (cellular) nologies are constantly developed and this extends the capabilities phones, personal media players (PMP), personal navigation devices of such devices correspondingly. (PND), personal digital assistants (PDA), smartphones, tablet per- sonal computers, notebooks, digital cameras, hand-held game con- soles and mobile internet devices (MID). Figure 1 shows different In this paper, a review about the existing and new hardware and mobile devices available on the market today. Traditional mobile software, as well as a closer look into some of the most important phones are aimed at making and receiving telephone calls over a revolutionary technologies, is given. Special emphasis is given on radio link. PDAs are personal organizers that later evolved into de- new Application Programming Interfaces (API) and rendering tech- vices with advanced units communication, entertainment and wire- niques that were developed in recent years. A review of limitations less capabilities [Wiggins 2004]. Smartphones can be seen as a that developers have to overcome when bringing graphics to mobile next generation of PDAs since they incorporate all its features but devices is also provided.
    [Show full text]
  • Comparative Study of Various Systems on Chips Embedded in Mobile Devices
    Innovative Systems Design and Engineering www.iiste.org ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol.4, No.7, 2013 - National Conference on Emerging Trends in Electrical, Instrumentation & Communication Engineering Comparative Study of Various Systems on Chips Embedded in Mobile Devices Deepti Bansal(Assistant Professor) BVCOE, New Delhi Tel N: +919711341624 Email: [email protected] ABSTRACT Systems-on-chips (SoCs) are the latest incarnation of very large scale integration (VLSI) technology. A single integrated circuit can contain over 100 million transistors. Harnessing all this computing power requires designers to move beyond logic design into computer architecture, meet real-time deadlines, ensure low-power operation, and so on. These opportunities and challenges make SoC design an important field of research. So in the paper we will try to focus on the various aspects of SOC and the applications offered by it. Also the different parameters to be checked for functional verification like integration and complexity are described in brief. We will focus mainly on the applications of system on chip in mobile devices and then we will compare various mobile vendors in terms of different parameters like cost, memory, features, weight, and battery life, audio and video applications. A brief discussion on the upcoming technologies in SoC used in smart phones as announced by Intel, Microsoft, Texas etc. is also taken up. Keywords: System on Chip, Core Frame Architecture, Arm Processors, Smartphone. 1. Introduction: What Is SoC? We first need to define system-on-chip (SoC). A SoC is a complex integrated circuit that implements most or all of the functions of a complete electronic system.
    [Show full text]
  • Innovative AMD Handheld Technology – the Ultimate Visual Experience™ Anywhere –
    MEDIA BACKGROUNDER Innovative AMD Handheld Technology – The Ultimate Visual Experience™ Anywhere – AMD Vision AMD has a vision of a new era of mobile entertainment, bringing all the capabilities of a camera, camcorder, music player and 3D gaming console to mobile phones, smart phones and tomorrow’s converged portable devices. This vision is quickly becoming reality. Mass adoption of image and video sharing sites like YouTube, as well as the growing popularity of camera phones and personalized media services, are several trends that demonstrate ever-increasing consumer demand for “always connected” multimedia. And consumers have demonstrated a willingness to pay for sophisticated devices and services that deliver immersive, media-rich experiences. This increasing appetite for mobile multimedia makes it more important than ever for device manufacturers to quickly deliver the latest multimedia features – without significantly increasing design and manufacturing costs. AMD in Mobile Multimedia With the acquisition of ATI Technologies in 2006, AMD expanded beyond its traditional realm of PC computing to become a powerhouse in multimedia processing technologies. Building on more than 20 years of graphics and multimedia expertise, AMD is a leading supplier of media processors to the handheld market with nearly 250 million AMD Imageon™ media processors shipped to date. Furthermore, AMD is a significant source of mobile intellectual property (IP), licensing graphics technology to semiconductor suppliers. AMD provides customers with a top-to-bottom family of cutting-edge audio, video, imaging, graphics and mobile TV products. The scalable AMD technology platforms are based on open industry standards, and are designed for maximum performance with low power consumption.
    [Show full text]
  • GPU4S: Embedded Gpus in Space
    © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. “The final publication is available at: DOI: 10.1109/DSD.2019.00064 GPU4S: Embedded GPUs in Space Leonidas Kosmidis∗,Jer´ omeˆ Lachaizey, Jaume Abella∗ Olivier Notebaerty, Francisco J. Cazorla∗;z, David Steenarix ∗Barcelona Supercomputing Center (BSC), Spain yAirbus Defence and Space, France zSpanish National Research Council (IIIA-CSIC), Spain xEuropean Space Agency, The Netherlands Abstract—Following the same trend of automotive and avion- in space [1][2]. Those studies concluded that although their ics, the space domain is witnessing an increase in the on-board energy efficiency is high, their power consumption is an order computing performance demands. This raise in performance of magnitude higher than the limited power budget of a space needs comes from both control and payload parts of the space- craft and calls for advanced electronics able to provide high system, which is limited to a couple of Watts. computational power under the constraints of the harsh space Interestingly, GPUs entered in the embedded domain to environment. On the non-technical side, for strategic reasons it is satisfy the increasing demand for multimedia-based hand- mandatory to get European independence on the used computing held and consumer devices such as smartphones, in-vehicle technology. In this project, which is still in its early phases, we entertainment systems, televisions, set-top boxes etc.
    [Show full text]
  • Accelerating Augmented Reality Video Processing with Fpgas
    Accelerating Augmented Reality Video Processing with FPGAs A Major Qualifying Project Submitted to the Faculty of Worcester Polytechnic Institute in partial fulfillment of the requirements for the Degree of Bachelor of Science 4/27/2016 Anthony Dresser, Lukas Hunker, Andrew Weiler Advisors: Professor James Duckworth, Professor Michael Ciaraldi This report represents work of WPI undergraduate students submitted to the faculty as evidence of a degree requirement. WPI routinely publishes these reports on its web site without editorial or peer review. For more information about the projects program at WPI, see http://www.wpi.edu/Academics/Projects. Abstract This project implemented a system for performing Augmented Reality on a Xilinx Zync FPGA. Augmented and virtual reality is a growing field currently dominated by desktop computer based solutions, and FPGAs offer unique advantages in latency, performance, bandwidth, and portability over more traditional solutions. The parallel nature of FPGAs also create a favorable platform for common types of video processing and machine vision algorithms. The project uses two OV7670 cameras mounted on the front of an Oculus Rift DK2. A video pipeline is designed around an Avnet ZedBoard, which has a Zynq 7020 SoC/FPGA. The system aimed to highlight moving objects in front of the user. Executive Summary Virtual and augmented reality are quickly growing fields, with many companies bringing unique hard- ware and software solutions to market each quarter. Presently, these solutions generally rely on a desktop computing platform to perform their video processing and video rendering. While it is easy to develop on these platforms due to their abundant performance, several issues arise that are generally discounted: cost, portability, power consumption, real time performance, and latency.
    [Show full text]
  • Rapid Prototyping of an FPGA-Based Video Processing System
    Rapid Prototyping of an FPGA-Based Video Processing System Zhun Shi Thesis submitted to the faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science In Computer Engineering Peter M. Athanas, Chair Thomas Martin Haibo Zeng Apr 29th, 2016 Blacksburg, Virginia Keywords: FPGA, Computer Vision, Video Processing, Rapid Prototyping, High-Level Synthesis Copyright 2016, Zhun Shi Rapid Prototyping of an FPGA-Based Video Processing System Zhun Shi (ABSTRACT) Computer vision technology can be seen in a variety of applications ranging from mobile phones to autonomous vehicles. Many computer vision applications such as drones and autonomous vehicles requires real-time processing capability in order to communicate with the control unit for sending commands in real time. Besides real-time processing capability, it is crucial to keep the power consumption low in order to extend the battery life of not only mobile devices, but also drones and autonomous vehicles. FPGAs are desired platforms that can provide high-performance and low-power solutions for real-time video processing. As hardware designs typically are more time consuming than equivalent software designs, this thesis proposes a rapid prototyping flow for FPGA-based video processing system design by taking advantage of the use of high performance AXI interface and a high level synthesis tool, Vivado HLS. Vivado HLS provides the convenience of automatically synthesizing a software implementation to hardware implementation. But the tool is far from being perfect, and users still need embedded hardware knowledge and experience in order to accomplish a successful design.
    [Show full text]
  • Performance Characterization of Mobile GP-Gpus
    Performance Characterization of Mobile GP-GPUs Fitsum Assamnew Andargie Jonathan Rose School of Electrical and Computer Engineering The Edward Roger Sr. Department of Electrical and Addis Ababa University Computer Engineering Addis Ababa, Ethiopia University of Toronto [email protected] Toronto, Canada [email protected] Abstract— As smartphones and tablets have become more efficient algorithms [4]. The microarchitectural parameters of sophisticated, they now include General Purpose Graphics desktop/server GP GPUs are well understood and revealed by Processing Units (GP GPUs) that can be used for computation the vendors [4], whereas mobile GP GPU microarchitectures beyond driving the high-resolution screens. To use them are far less well documented. The purpose of this paper is to effectively, the programmer needs to have a clear sense of their measure key aspects of the microarchitecture and micro- microarchitecture, which in some cases is hidden by the communication channels for the Qualcomm Adreno 320 [5] manufacturer. In this paper we unearth key microarchitectural and 420 GPUs, which exist in the widely used Snapdragon parameters of the Qualcomm Adreno 320 and 420 GP GPUs, series of SoCs [6] used in many tablets and phones. present in one of the key SoCs in the industry, the Snapdragon Understanding these GP GPUs will enable high performance series of chips. applications to be developed for platforms that harbor them. Keywords—smartphones; GP GPU; microarchitecture; Adreno GPU;OpenCL II. BACKGROUND Recent smartphones are equipped with many kinds of I. INTRODUCTION compute modalities that can be used to enhance application Smartphones have progressed dramatically in the last few performance.
    [Show full text]
  • Simulation and Development Environment for Mobile 3D Graphics Architectures
    SPECIAL SECTION ON ADVANCES IN ELECTRONICS SYSTEMS SIMULATION Simulation and development environment for mobile 3D graphics architectures W.-J. Lee, W.-C. Park, V.P. Srini and T.-D. Han Abstract: This paper describes a simulation and development environment for designing mobile three-dimensional (3D) graphics architectures. The proposed simulation and verification environ- ment (SVE) uses glTrace’s ability to intercept and redirect an OpenGLjES streams. The SVE simu- lates the behaviour of mobile 3D graphics pipeline during the playback of traces and produces the second geometry trace that can be used as a test vector for the Verilog/hardware discription language RT-level model. An architectural verification can be conducted by comparing the frame-by-frame results. The functionality of the SVE is demonstrated by designing a mobile 3D graphics architecture and implementing the verified architecture on field programmable gate array (FPGA) boards. An application development environment (ADE) is also presented that includes a mobile graphics application programming interface and a device driver interface. The proposed SVE and the ADE could be efficiently used for developing and testing mobile appli- cations, architectural analysis and hardware designs. 1 Introduction for mobile 3D has been proposed with optimisation tech- niques such as multi-sampling, texture filtering and simple Mobile devices such as hand-held phone, smart phone, culling. Mitsubishi researchers have published a paper digital multimedia broadcasting (DMB) terminal, PDA and about an large-scale integration (LSI) core, called Z3D [4]. portable gaming console are used all over the world. They Many GPUs for mobile devices are being released by hard- contain a decent liquid crystal display (LCD) colour ware manufacturers.
    [Show full text]
  • Memory System Optimizations for CPU-GPU Heterogeneous Chip-Multiprocessors
    Memory System Optimizations for CPU-GPU Heterogeneous Chip-multiprocessors A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Siddharth Rai to the DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING INDIAN INSTITUTE OF TECHNOLOGY KANPUR, INDIA July, 2018 Synopsis Recent commercial chip-multiprocessors (CMPs) have integrated CPU as well as GPU cores on the same chip [42, 43, 44, 93]. In today's designs, these cores typically share parts of the memory system resources between the applications executing on the two types of cores. However, since the CPU and the GPU cores execute very different workloads leading to very different resource requirements, designing intelligent protocols for sharing resources between them such that both CPU and GPU gain in performance brings forth new challenges to the design space of these heterogeneous processors. In this dissertation, we explore solutions to dynamically allocate last-level cache (LLC) capacity and DRAM bandwidth to the CPU and GPU cores in a design where both the CPU and the GPU share the large on- die LLC, DRAM controllers, DRAM channels, DRAM ranks, and DRAM device resources (banks, rows). CPU and GPU differ vastly in their execution models, workload characteristics, and performance requirements. On one hand, a CPU core executes instructions of a latency-sensitive and/or moderately bandwidth-sensitive job progressively in a pipeline generating memory accesses (for instruction and data) only in a few pipeline stages (instruction fetch and data memory access stages). On the other hand, GPU can access different data streams having different semantic meanings and disparate access patterns throughout the rendering pipeline.
    [Show full text]
  • (Unified) Shader GPU Microarchitecture for Embedded Systems*
    A Single (Unified) Shader GPU Microarchitecture * for Embedded Systems Victor Moya1, Carlos González, Jordi Roca, 2 Agustín Fernández, and Roger Espasa Department of Computer Architecture, Universitat Politècnica de Catalunya Abstract. We present and evaluate the TILA-rin GPU microarchitecture for embedded systems using the ATTILA GPU simulation framework. We use a trace from an execution of the Unreal Tournament 2004 PC game to evaluate and compare the performance of the proposed embedded GPU against a baseline GPU architecture for the PC. We evaluate the different elements that have been removed from the baseline GPU architecture to accommodate the architecture to the restricted power, bandwidth and area budgets of embedded systems. The unified shader architecture we present processes vertices, triangles and fragments in a single processing unit saving space and reducing hardware complexity. The proposed embedded GPU architecture sustains 20 frames per second on the selected UT 2004 trace. 1 Introduction In the last years the embedded market has been growing at a fast peace. With the in- crease of the computational power of the CPUs mounted in embedded systems and the increase in the amount of available memory those systems have become open to new kind of applications. One of these applications are 3D graphic applications, mainly games. Modern PDAs, powerful mobile phones and portable consoles already implement relatively powerful GPUs and support games with similar characteristics and features of PC games from five to ten years ago. However at the current pace embedded GPUs are about to reach the programmability and performance capabilities of their ‘big brothers’, the PC GPUs.
    [Show full text]
  • Mobile Graphics Trends
    Visual Computing Group Part 2 Mobile graphics trends • Hardware architectures • Applications 1 Visual Computing Group Hardware architectures 2 Mobile Graphics Tutorial – EuroGraphics 2017 Brief history of mobile graphics hardware Apple Samsung Imagination ARM Qualcomm AMD Intel Nvidia (PowerVR) (mostly ARM) PowerVR Mali Snapdragon/ iPhone MBX Buys Adreno (MBX) SGX535/541 Phalanx 2007 (GLES 2.0) Buys Sells Imageon Omnia HD Buys PA Hummingbird Mali 400 Imageon (TI OMAP 3 SGX543 (GLES 2008 Semi (Cortex A8) GLES 2.0 (Adreno) & Power VR 2.0, GL 2.1) SGX530) iPhone 3GS SGX545 (GLES 2009 (SGX535) 2.0 GL 3.2) Tegra 2 (Cortex- 2010 A4 (ARM A9, GLES 2.0) Cortex A8) Tegra 3 (Cortex- 2011 A9, GLES 2.0) Series 6XE/XT T600 GLES Adreno 530 GLES 3.1+, 2012 A7/A8 & GLES 3.1 GL 3.2 2.0, DX9.0 OpenCL 2, A8X (28nm) DX 11.2 Tegra 4 (Cortex- (GT64XX) Vulcan 1.0 2013 T700 GLES A15, GL 4.4, 28nm) Exynos 3,1, DX 11.1 5433/7410 Series7XE A9 OpenCL 1.1 Tegra K1 (Cortex- 2014 (GT7600) (20nm, Mali- Vulkan 1.0 GLES A15, GL 4.4, 28nm) T760 MP6) 3.1 (latter ones T800 GLES 3,1, Tegra X1 (Cortex- 10nm) DX 11.1-11.2 A57, GLES 3.1, GL 2015 OpenCL 1.2 4.5, Vulkan, 20nm) Plans to Apple will no longer require 2016 build its own its services in 18-24 months Next Tegra GPU Furian? generations seem to be for automotive 3 Mobile Graphics Tutorial – EuroGraphics 2017 Architectures (beginning 2015) ARM 4 Mobile Graphics Tutorial – EuroGraphics 2017 Architectures • x86 (CISC 32/64bit) – Intel Atom Z3740/Z3770, X3/X5/X7 – AMD Amur / Styx (announced) – Present in few smartphones, more common in tablets – Less efficient • ARM – RISC 32/64bit • With SIMD add-ons – Most common chip for smartphones – More efficient & smaller area • MIPS – RISC 32/64bit – Including some SIMD instructions – Acquired by Imagination, Inc.
    [Show full text]
  • 3D Graphics and Speqg Update
    3D Graphics and SpeqG Update David Ligon Product Manager, Staff QUALCOMM Incorporated Agenda • Overview of QUALCOMM® Graphics Cores • MSM6xxx Update, Including New Cores • MSM7x00 Update • MSM7850 Introduction • SpeqG 100M Gaming Phone Alliance QUALCOMM Graphics Core Performance 1G Convergence Sony PSP Enhanced “Imageon” Stargate “Imageon” 100M without SMI Sony PS2 “Stargate” Convergence Convergence 10M Enhanced Defender3 Nintendo DS “Defender3” “Imageon” “LT” 1M with SMI Convergence Enhanced 100K Platform provides 3D Pixels/Sec Defender2 advanced graphics features not “Defender2” available on PSP 10K and other handheld gaming devices: Gameboy Advance 1K 1K 10K 100K 1M 10M 100M MSM Cores 3D Triangles/Sec New MSM Cores Graphics Core MSM Lineup Gfx Core Peak Performance In Production 2007 21M TRIS /SEC 133M PIXELS /SEC 7850A7850 LT 3D DOrB LT 2D 532M PIXEL REJECT /S 798M TOTAL INST /S Q1 7200A 7500A HSUPA Imageon 3D 4M TRIS /SEC 7500 7200 DOrA 133M PIXELS /SEC DOrA HSUPA 7600 Imageon 2D DOrA Q1 Q4 HSUPA Stargate 3D 600K TRIS /SEC 6280A HSDPA ARM 2D 90M PIXELS /SEC Q3 Defender3 3D 225K TRIS /SEC 6175 6800A 6575 ARM 2D 22M PIXELS /SEC 1x DOrA DOr0 6550 6550A 6800 6280 Defender2 3D 225K TRIS /SEC DOr0 DOr0 DOrA HSDPA ARM 2D 7M PIXELS /SEC 6150 6275 1x HSDPA 6500 6100 6250A 6260 ARM-DSP 3D 50K - 100K TRIS /SEC DOr0 1x WCDMA HSDPA ARM 2D 400K - 1M PIXELS /SEC 6125 6250 6255A 6245 1x WCDMA WEDGE WEDGE 6050 6025 QSC QSC QSC 7525 7225 QSC 1x 1x 6030 6055 6075 DOrA HSUPA 6085 No 3D N/A 1x 1x DOrA DOrA ARM 2D 6000 QSC QSC 6225 Q1 QSC 6260-1 QSC QSC
    [Show full text]