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(12) United States Patent (10) Patent No.: US 9,106,488 B1 Haran (45) Date of Patent: Aug

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(12) United States Patent (10) Patent No.: US 9,106,488 B1 Haran (45) Date of Patent: Aug USOO9106488B1 (12) United States Patent (10) Patent No.: US 9,106,488 B1 Haran (45) Date of Patent: Aug. 11, 2015 (54) ENERGY EFFICIENT HIGHWAY 8,204,078 B2 * 6/2012 McLaughlin ................. 370/466 ADDRESSABLE REMOTE TRANSDUCER 2004/0113814 A1* 6/2004 Lochner ......... ... 340,870.18 2009 OO72994 A1* 3, 2009 Kleven et al. 340,870.05 SOFT MODEMI 2009/0110.039 A1 4/2009 Kort .............................. 375.222 2011/0286542 A1* 11/2011 Shelburne ... 375/272 (71) Applicant: Smart Embedded Systems Inc., 2012/0020430 A1 1/2012 Haase et al. ... 375,295 Fremont, CA (US) 2013,0107919 A1* 5, 2013 Burns et al. .... ... 375,219 2014/0269764 A1* 9/2014 Borgeson et al. ............. 370/468 (72) Inventor: Pranatharthi Subbaratnam Haran, Fremont, CA (US) * cited by examiner (73) Assignee: Smart Embedded Systems, Inc., Primary Examiner — Erin File Fremont, CA (US) (74) Attorney, Agent, or Firm — Ash Tankha; Lipton, (*) Notice: Subject to any disclaimer, the term of this Weinberger & Husick patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days. (57) ABSTRACT (21) Appl. No.: 14/466,970 A method and a highway addressable remote transducer (HART) soft modem device for modulating and demodulat (22) Filed: Aug. 23, 2014 ing analog signals with HART messages are provided. A phase coherent frequency shift keying (FSK) modulator (51) Int. Cl. modulates and transmits analog signals with HART mes H04B I/38 (2015.01) sages, and a phase coherent FSK demodulator receives and H04L 5/16 (2006.01) demodulates the analog signals with the HART messages. H04L 27/2 (2006.01) The FSK modulator is a digital modulator that outputs 1 or 0 H04L 25/240 (2006.01) for transmission. With oversampling and low pass filtering, (52) U.S. Cl. the digital modulation results in low jitter and good signal to CPC .............. H04L 27/122 (2013.01); H04L 25/40 noise ratio. The FSK demodulator applies a fast energy detect (2013.01) algorithm and dynamically reduces or increases a clock speed (58) Field of Classification Search of a central processing unit (CPU) of the HART soft modem CPC .............................. H04L 27/122; H04L 25/40 device for reducing power consumption of the CPU. Further See application file for complete search history. more, the HART soft modem device uses direct memory access (DMA) to further reduce the power consumption, (56) References Cited thereby reducing the overall power consumption by around U.S. PATENT DOCUMENTS 50%. 5,596,188 A * 1/1997 McElroy .................. 250,231.16 6,297.691 B1 * 10/2001 Anderson et al. ............. 329,300 2 Claims, 10 Drawing Sheets ANAOG INTT SIMULATION O% TO IOO% 3.3W 102 3.3W k -- MICROCONTROLLER A MEDIA ACCESS UNIT 101b 10c 9ir WOLTAGE -4 -4 REGULATOR - PARAIIE TO SFRA CPUPU VSP CONVERTER 102. 102b FSKFMOTATOR FSK HART STACK 7 MODULATORLAT 50: SFNSORAN FR 101d 7 MODEM 101 102a COM i CN OOP(-) r M r AIR CHART 103 UART FOREBGAN TRANSMIT OT BAND PASS W CONTROI FILTER AR RECEIVE IN H U.S. Patent US 9,106,488 B1 U.S. Patent Aug. 11, 2015 Sheet 2 of 10 US 9,106,488 B1 CONVERT A HIGHWAY ADDRESSABLE REMOTE TRANSDUCER (HART) MESSAGE INTO A SERIAL DATA BIT STREAM COMPRISING BINARY INTFORMATION BY A PARALLEL TO SERIAL CONVERTER CHECK A VALUE OF THE BINARY INFORMATION OF THE SERIAL DATA BIT STREAM BY A PHASE COHERENT FREQUENCY SHIFT KEYING (FSK) MODULATOR SET A PHASE CHANGE OF A CARRIER SIGNAL TO A FIRST FREQUENCY WHEN THE VALUE OF THE BINARY INFORMATION IS 1, AND SET THE PHASE CHANGE OF THE CARRIER SIGNAL TO ASECOND FREQUENCY WHEN THE VALUE OF THE BINARY INFORMATION IS 0, BY THE FSK MODULATOR ACCUMULATE INCREMENTAL PIASE CIIANGE DATA BY CONTINUOUSLY ADDING THE PHASE CHANGE OF THE CARRIER SIGNAL BY THE FSK MODULATOR COMPARE THE ACCUMULATED PHASE CHANGE DATA WITH MUI TIPLE SINE VALUES FROMA PREDETERMINED SINE VALUE PHASE TABLE BY THE FSKMODULATOR SELECT ASINE VALUE FOR THE CORRESPONDING ACCUMULATED PHASE CIIANGE DATA FROM TIE PREDETERMINED SINE VALUE PIASE TABLE BY THE FSK MODULATOR CONVERT THE SELECTED SINE VALUE INTO AN ANALOG SIGNAL BY THE FSK MODULATOR FORTRANSMISSION OF THE HART MESSAGE FIG 2 U.S. Patent Aug. 11, 2015 Sheet 3 of 10 US 9,106,488 B1 INPUT SERIAL BIT STREAM FREQUENCY = 1200 Hz FREQUENCY = 2200 Hz SET PHASE CHANGE FOR SET PHASE CHANGE FOR 1200 HZ 2200 HZ ACCUMULATE IPHASE PHASE = PHASE - PHASE CHANGE LOOK UP SINE VALUE FROM ASINE VALUE PHASE TABLE OUTPUT VALUE TO N BIT DAC FIG, 3 U.S. Patent US 9,106,488 B1 stolº (O+1(PaOWEPop))soo (0+(1–1)(OOWEPop))soo U.S. Patent Aug. 11, 2015 Sheet 5 of 10 US 9,106,488 B1 RECEIVE AN ANALOGSIGNAL COMPRISINGA IIIGIIWAY ADDRESSABLE REMOTE TRANSDUCER (HART) MESSAGE BY A PHASE COHERENT FREQUENCY SHIFT KEYING (FSK) DEMODULATOR OF A HART SOFT MODEMDEVICE SAMPLE THE ANALOG SIGNAL AND CONVERT THE SAMPLED ANALOG SIGNAL INTO DIGITIZED ANAIOG SAMPIES AT APREDETERMINED DIGITA, SAMPING RATE PROCESS THE DIGITIZED ANALOG SAMPLES FOR REMOVING LOW FREQUENCY INTERFERING SIGNALS FROM THE DIGITIZED ANALOG SAMPLES COMPARE A SIGNAL AMPLITUDE OF THE PROCESSED DIGITIZED ANALOG SAMPLES WITH PREDETERMINED THRESHOLD VALUES AND APPLY AFAST ENERGY DETECT ALGORITIIM USING AN ENERGY DETECTOR FOR DETERMINING WHETHERFURTHER SIGNAL PROCESSING OF THE PROCESSED DIGITIZED ANALOG SAMPLES IS REQUIRED REDUCE A CLOCK SPELED OF A CENTRAL PROCESSING UNIT (CPU) OF THE HART SOFT MODEM DEVICE TO APREDETERMINED LOW FREQUENCY VALUE WHEN SUFFICIENT ENERGY IS NOT DIETIECTIED DURING THE COMPARISON INCREASE TIE CLOCKSPEED OF TIE CPU TO APREDETERMINED IIIGII FREQUENCY VALUE WHEN SUFFICIENT ENERGY IS DETECTED DURING THE COMPARISON INTRODUCE A PREDIETIERMINED PHASE DIELAY IN THE PROCESSIED DIGITIZED ANALOG SAMPLES FOR PRODUCING IPHASE SHIFTED DIGITIZED ANALOG SAMPLES DEMODULATE THE PROCESSED DIGITIZED ANALOG SAMIPLES TO OBTAINA 508 DEMODULATED SIGNAL VIA PHASE DISCRIMINATION BY MULTIPLYING THE PROCESSED DIGITIZED ANALOG SAMPLES FROM TIE ENERGY DETECTOR WITII THE PHASE SHIFTED DIGITIZED ANALOG SAMPLES 509 REMOVE SECOND ORDER FREQUENCIES IN THE DEMODULATED DIGITIZED ANAIOG SAMPLES 510 CHECK THE DEMODULATED DIGITIZED ANALOG SAMPLES FOR A BINARY VALUE 511 IPERFORMA BIT SHIFT OPERATION AND ASSEMBLE AN 11 BIT CHARACTERFOR CHARACTER GENERATION AND BIT SYNCHRONIZATION OF THE DEMODULATED ANALOG SIGNAL FIG. 5 U.S. Patent Aug. 11, 2015 Sheet 6 of 10 US 9,106,488 B1 601 WAIT FOR GET SIGNAL NEXT VALUE FROM THE SAMPLE AfD CONVERTER SIGNAL CONDITION BY HIGH PASS FIIHR IS SIGNAI, GREATER THAN UPPER OR LOWER 605 TIIRESIOLD 609 SIGNAL EDCOUNT = SIGNAL TOO SMALL EDCOUNT - LARGE DECREMENT EDCOUNT NUMBER CARRIER DETECTED SPEED UP THE CPU SET CPU MUTITIPLIER TO N PERFORM FSK DEMODULATION SIGNAL NOT PRESENT SLOW DOWN TIE CPU 608 BY SETTING CPU MUI TIPLIER TO WAIT FOR NEXT SAMPLE WAIT FOR NEXT SAMPLE FIG. 6 U.S. Patent Aug. 11, 2015 Sheet 7 of 10 US 9,106,488 B1 RECEIVE DIGITIZED ANALOG SAMPLES FROM A HIGH PASS FILTER OF A PHASE COHERENT FREQUENCY SHIFT KEYING (FSK) DEMODULATOR OF A HIGHWAY ADDRESSABLE REMOTE TRANSDUCER (HART) SOFT MODEM DEVICE BY AN ENERGY DETECTOR COMPARE A SIGNAL AMPLITIDE OF THE RECEIVED DIGITIZED ANALOG SAMPLES WITH PREDETERMINED THRESHOLD VALUES DETECT PRESENCE OF A VALID HART ANALOG SIGNAL WHEN THE COMPARISON RESULTS IN A VALUE GREATER THAN THE PREDETERMINED 793 THRESHOLD VALUES AND INCREASE THE SPEED OF A CENTRAL PROCESSING UNIT (CPU) CLOCK OF THE HART SOFT MODEM DEVICE TO A PREDETERMINED HIGH FREQUENCY VALUE SET AN ENERGY DETECT COUNT VALUE TO APREDETERMINED VALUE 704 AND DECREMENT THE ENERGY DETECT COUNT VALUE WHENEVER THE SIGNAL AMPLITUDE OF THE RECEIVED DIGITIZED ANALOG SAMPLESIS LESS THAN THE PREDETERMINED THRESHOLD VALUES DETECT ABSENCE OF THE VALID HART ANALOG SIGNAL WHEN THE 705 ENERGY DETECT COUNT VALUE IS LESS THAN ZERO AND REDUCE THE SPEED OF THE CPU CLOCK OF THE HART SOFT MODEM DEVICE FOR REDUCING POWER CONSUMPTION OF TECU FIG. 7 U.S. Patent Aug. 11, 2015 Sheet 8 of 10 US 9,106,488 B1 ANALOG TO DIGITAL CONVERSION OF A HART ANALOG SIGNAL PROCESS DIGITAL DATA BY HIGH PASS FILTER ENERGY DETECTION PHASE DELAY OF PI/2 PHASE DISCRIMINATION LOW PASS FILTERING DETECT 1 OR 0 CHARACTER ASSEMBLY FIG. 8 U.S. Patent Aug. 11, 2015 Sheet 9 of 10 US 9,106,488 B1 FSK SIGNAL - - - UPPER THRESHOLD LOWER THRESHOLD FIG. 9 U.S. Patent Aug. 11, 2015 Sheet 10 of 10 US 9,106,488 B1 1000 DMA TIMER 1004 CONTROLLER ADC SAMPLES HARDWARE MUITIDIER FILTER COEFFICIENTS FILTER OUTPUT D ACTIONDM FIG 10 US 9,106,488 B1 1. 2 ENERGY EFFICIENT HIGHWAY modem is a modem with minimal hardware that utilizes a ADDRESSABLE REMOTE TRANSDUCER host’s resources in place of additional hardware in a conven SOFT MODEMI tional modem. Since HART field data devices that utilize Bell 202 modem standards are power sensitive, there is a need for BACKGROUND a soft modem implementation of the HART field data device that uses advanced techniques to minimize operating power. Smart field data devices in use today are generally High In a typical Highway Addressable Remote Transducer way Addressable Remote Transducer (HART) enabled. (HART) field data device, modulation is performed via pulse HART is a global standard for sending and receiving digital width modulation (PWM). PWM is a modulation technique information across analog wires between Smart devices and 10 that controls the width of a pulse based on modulator signal control or monitoring systems. The HART communications information. Typically, PWM allows control of the power protocol is widely recognized as the industry standard for supplied to electrical devices. A conventional PWM modula digitally enhanced 4 milliampere (mA)-20 mA Smart instru tor utilizes two different frequencies for PWM generation. ment communication. Use of the HART based technology is This type of modulation works well at low baud rates, for growing rapidly and today most major global instrumentation 15 example, at 300 bauds in a V.21 or Bell 103 modem, but suppliers offer products with the HART communications pro results in Substantial jitter and a lack of phase coherency at tocol.
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