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Advance Program ASP-DAC 2010 Highlights ‧1D-2: Maximizing the Harvested Energy for Micro-Power Applications through Efficient MPPT and PMU Design Opening Authors: Hui Shao, Chi-Ying Tsui, Wing-Hung Ki Contents Tuesday, January 19, 8:30-09:00 Affiliation of All Authors: Hong Kong Univ. of Science Taipei International Convention Center (TICC), Room 101 and Technology, Hong Kong Highlights .....................................2 Speaker: Chi-Ying Tsui Keynote I Welcome to ASP-DAC 2010 .........................9 Tuesday, January 19, 9:00-10:00 ‧1D-3: Dynamic Power Management in Environmentally Taipei International Convention Center (TICC), Room 101 Sponsorship ..................................10 Powered Systems “I Attended the Nineteenth Design Automation Conference” Authors: Clemens Moser, Jian-Jia Chen, and Lothar Thiele Organizing Committee ...........................11 Chung-Laung Liu Affiliation of All Authors: ETH Zurich, Switzerland Chair Professor of National Tsing Hua University, Taiwan Speaker: Jian-Jia Chen Technical Program Committee ......................13 University LSI Design Contest Committee ..............18 Keynote II ‧1D-4: Micro-scale energy harvesting: A system perspective Tuesday, January 19, 10:20-11:20 Authors: Lu Chao, Vijay Raghunathan, and Kaushik Roy Industry Liaison ................................18 Taipei International Convention Center (TICC), Room 101 Affiliation of All Authors: Purdue Univ., USA “Delivering 10X Design Improvements” Steering Committee ............................19 Speaker: Vijay Raghunathan Walden C. Rhines University LSI Design Contest ......................21 Chairman and Chief Executive Officer, Mentor Graphics, USA Session 2D: Tuesday, January 19, 15:30-17:10, Room 101D 3D Integration and Networks on Chips Designers’ Forum ..............................23 Keynote III Organizer & Moderator: Srinivasan Murali, iNoCs/EPFL, Student Forum at ASP-DAC 2010 ....................27 Tuesday, January 19, 11:20-12:20 Switzerland Taipei International Convention Center (TICC), Room 101 Invitation to ASP-DAC 2011 ........................28 “IC Design for the Intuitive Life Style” ‧2D-1: 3D Integration and Networks on Chips (Short Paper) Keynote Addresses .............................29 Jim Lai Authors: Srinivasan Murali (iNoCs/EPFL, Switzerland), President of Global Unichip Corp., Taiwan Luca Benini (Univ. of Bologna, Italy), Giovanni De Micheli Technical Program ..............................31 (EPFL, Switzerland) Tutorials .....................................57 Special Sessions Speaker: Srinivasan Murali Session 1D: Tuesday, January 19, 13:30-15:10, Room 101D ASP-DAC 2010 at a Glance .........................65 Techniques for Efficient Energy Harvesting and Generation ‧2D-2: Panel Discussion: 3D Integration and Networks on Chips Registration ...................................69 for Portable and Embedded Systems Organizer & Chair: Pai Chou (Univ. of California, Irvine, USA/ Organizer & Moderator: Srinivasan Murali, iNoCs/EPFL, Registration Form ..............................73 National Tsing Hua Univ., Taiwan) Switzerland Panelists: Ruchir Puri, IBM, USA Information ...................................75 Paull Marchal, IMEC, Belgium ‧1D-1: Room-Temperature Fuel Cells and Their Integration Accommodations ..............................77 into Portable and Embedded Systems Yuan Xie, Pennsylvania State Univ., USA Authors: Naehyuck Chang, Jueun Seo, Donghwa Shin, Ahmed Jerraya, LETI, France Hotel Reservation Form ..........................81 Nobuaki Miyakawa, Honda Research, Japan and Younghyun Kim Access to Taipei International Convention Center (TICC) .....82 Affiliation of All Authors: Seoul National Univ., Republic of Korea Venue Map/Room Assignment .....................83 Speaker: Naehyuck Chang 1 2 3 Session 3D: Wednesday, January 20, 08:30-10:10, Room 101D ‧7D-4: Panel Discussion: Dependable Silicon Design with ‧5D-2: Design and Verification Methods of Toshiba's Recent Advancement in Post-Silicon Validation Unreliable Components Wireless LAN Baseband SoC Chair: Ing-Jer Huang, National Sun Yat-Sen Univ., Taiwan Organizer & Moderator: Vincent Mooney, Georgia Tech/ Masanori Kuwahara, Toshiba, Japan Nanyang Technological Univ., USA ‧3D-1: Data Learning Based Diagnosis Panelists: Vivek K. De, Intel Corp., USA ‧5D-3: Programmable Platform for Multimedia SoC Author: Li-C. Wang, Univ. of California, Santa Barbara, USA Siva Narendra, Tyfone, Inc., USA Bor-Sung Liang, Sunplus Core Technology, Taiwan Krishna Palem, Rice Univ./ Nanyang ‧3D-2: Using Introspective Software-Based Testing for Post- Technological Univ., USA Silicon Debug and Repair ‧5D-4: SoC for Car Navigation Systems with a 53.3 GOPS Image Recognition Engine Author: Todd Austin, Univ. of Michigan, USA Session 8D: Thursday, January 21, 10:30-12:10, Room 101D ESL: Analysis and Synthesis of Multi-Core Systems Hiroyuki Hamasaki, Renesas Technology, Japan ‧3D-3: Post-Silicon Debugging for Multi-Core Designs Organizer & Chair: Daniel D. Gajski, Univ. of California at Irvine, Author: Valeria Bertacco, Univ. of Michigan, USA USA Session 6D: Wednesday, January 20, 15:30-17:10, Room 101D Is 3D Integration an Opportunity or Just a Hype? ‧3D-4: Low-Cost Repair Techniques by Using Partitioning ‧8D-1: Computer-Aided Recoding for Multi-Core Systems Organizers: Cheng-Wen Wu, National Tsing Hua Univ./ITRI, Author: Kyungho Kim, Byungtae Kang, Dongyun Kim Author: Rainer Dömer, Univ. of California, Irvine, USA Taiwan (Samsung Electronics Co., Republic of Korea), Sungchul Lee, Jin-Fu Li, National Central Univ./ITRI, Taiwan Juyong Shin and Hyunchul Shin (Hanyang Univ., Republic of ‧8D-2: TLM Automation for Multi-Core Design Korea) Author: Samar Abdi, Concordia Univ., Canada ‧6D-1: Tutorial: Is 3D Integration an Opportunity or Just Speaker: Hyunchul Shin a Hype? ‧8D-3: Platform Modeling for Exploration and Synthesis Jin-Fu Li, National Central Univ./ITRI, Taiwan ‧3D-5: On Signal Tracing in Post-Silicon Validation Authors: Andreas Gerstlauer, Univ. of Texas at Austin, Author: Qiang Xu and Xiao Liu, Chinese Univ. of Hong Kong, USA; Gunar Schirner, Northeastern Univ., USA ‧6D-2: Panel Discussion: Is 3D Integration an Opportunity Hong Kong Speaker: Andreas Gerstlauer Speaker: Qiang Xu or Just a Hype? Organizers & Moderators: Cheng-Wen Wu, National Tsing ‧8D-4: Application of ESL Synthesis on GSM Edge Algorithm Session 7D: Thursday, January 21, 08:30-10:10, Room 101D for Base Station Hua Univ./ITRI, Taiwan Dependable Silicon Design with Unreliable Components Author: Alan Su, Global Unichip Corp., Taiwan Jin-Fu Li, National Central Univ./ITRI, Taiwan Organizer & Moderator: Vincent Mooney, Georgia Tech/ Panelists: Albert Li, GUC, Taiwan Nanyang Technological Univ., USA Designers’ Forum Erik Jan Marinissen, IMEC, Belgium Ding-Ming Kwai, ITRI, Taiwan ‧7D-1: Resilient Design in Scaled CMOS for Energy Efficiency Session 5D: Wednesday, January 20, 13:30-15:10, Room 101D Kyu-Myung Choi, Samsung, Republic of Korea Authors: James Tschanz, Keith Bowman, Muhammad Oral Session: State-of-the-art SoCs Makoto Takahashi, Toshiba, Japan Khellah, Chris Wilkerson, Bibiche Geuskens, Dinesh Organizers: Kunio Uchiyama, Hitachi, Japan Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Ing-Jer Huang, National Sun Yat-Sen Univ., Taiwan Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek K. De Session 9D: Thursday, January 21, 13:30-15:10, Room 101D Affiliation of All Authors: Intel Corp., USA Oral Session: ESL, the Road to Glory, Or Is It Not? Real Stories Invited Talks: about Using ESL Design Methodology in Product Development Speaker: Vivek K. De Overview of ITRI's Parallel Architecture Core (PAC) DSP Project: from VLIW DSP Processor to Android ready Organizers: Alan P. Su, Global Unichip Corp., Taiwan ‧7D-2: Benefits and Barriers to Probabilistic Design Multicore Computing Platform Ing-Jer Huang, National Sun Yat-Sen Univ., Taiwan Author: Siva Narendra, Tyfone, Inc., USA An-Yeu (Andy) Wu, ITRI, Taiwan Invited Talks: ‧7D-3: A Probabilistic Boolean Logic for Energy Efficient 5D-1: Overview of ITRI's Parallel Architecture Core (PAC) ‧9D-1: Possibility of ESL- A Software Centric System Design Circuit and System Design ‧ DSP Project: from VLIW DSP Processor to Android ready for Multicore SoC in the Upstream Phase Author: Lakshmi N. B. Chakrapani (Rice Univ., USA), Krishna Koichiro Yamashita, Fujitsu Laboratories Ltd., Japan Palem (Rice Univ./Nanyang Technological Univ., USA) Multicore Computing Platform Speaker: Krishna Palem An-Yeu (Andy) Wu, ITRI, Taiwan 4 5 6 ‧9D-2: Design of Complex Image Processing Systems in ESL Two Half-Day and Three Full-Day Tutorials Welcome to ASP-DAC 2010 Benjamin Carrion Schafer (NEC Corp., Japan), Ashish Trambadia (NEC, Japan), Kazutoshi Wakabayashi (NEC HALF-DAY Tutorials On behalf of the Organizing Committee, I would like to invite you to the 2010 Asia Corp., Japan) Tutorial 1: Monday, January 18, 9:30-12:30, Room 101A Speaker: Kazutoshi Wakabayashi and South Pacific Design Automation Embedded Software for System-on-Chip (SoC) Design Conference (ASP-DAC 2010) to be held Organizer: Tie-Wei Kuo (National Taiwan Univ., Taiwan) 9D-3: PAC Duo System Power Estimation at ESL on January 18-21, 2010 in Taipei, Taiwan. ‧ Speakers: Lothar Thiele (Swiss Federal Institute of Technology Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang (ITRI/ This is the first time that ASP-DAC comes (ETH), Switzerland) National Tsing Hua Univ., Taiwan) to Taiwan. Taiwan is the place where many electronics systems Speaker: Wen-Tsan Hsieh Tie-Wei Kuo (National Taiwan Univ., Taiwan) and semiconductor devices are designed and manufactured.
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