Array Structured Memories

STMicro/Intel UCSD CAD LAB Weste Text

1 STMicro/Intel/UCSD/THNUEE141 Memory Memory Arrays Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory (CAM)

Read/Write Memory Read Only Memory Shift Registers Queues (RAM) (ROM) (Volatile) (Nonvolatile)

Serial In Parallel In First In Last In Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out (SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)

Mask ROM Programmable Erasable Electrically Flash ROM ROM Programmable Erasable (PROM) ROM Programmable (EPROM) ROM (EEPROM)

2 STMicro/Intel/UCSD/THNUEE141 Memory Feature Comparison Between Memory Types

3 STMicro/Intel/UCSD/THNUEE141 Memory 4 STMicro/Intel/UCSD/THNUEE141 Memory Array Architecture ß 2n words of 2m bits each ß If n >> m, fold by 2k into fewer rows of more columns

bitline conditioning wordlines bitlines row decoder

memory cells: 2n-k rows x 2m+k columns

n-k k column circuitry n column decoder 2m bits ß Good regularity œ easy to design ß Very high density if good cells are used

5 STMicro/Intel/UCSD/THNUEE141 Memory Memory - Real Organization Array of N x K words ------columns ------KxM S0

C of M bit words row 0 R------rows ------

C of M bit words row 1

C of M bit words row 2 Log2R Row Address Decoder Lines

C of M bit words row N-2

C of M bit words row N-1 SR-1 ---- KxM bits - - - - Log2C Address Column Select Lines

M bit data word 6 STMicro/Intel/UCSD/THNUEE141 Memory Hierarchical Memory Architecture

Row Address

Column Address

Block Address

Global Data Bus Control Block Selector Global Circuitry Amplifier/Driver

I/O

Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings 7 STMicro/Intel/UCSD/THNUEE141 Memory Array Organization Design Issues

ß aspect ratio should be relative square ° Row / Column organisation (matrix) ° R = log2(N_rows); C = log2(N_columns) ° R + C = N (N_address_bits) ß number of rows should be power of 2 ° number of bits in a row need not be… ß sense amplifiers to speed voltage swing ß 1 -> 2R row decoder ß 1 -> 2C column decoder ° M column decoders (M bits, one per bit) œ M = output word width

8 STMicro/Intel/UCSD/THNUEE141 Memory Simple 4x4 SRAM Memory read precharge bit line precharge enable WL[0] BL !BL

A1 e 2 bit width: M=2 d WL[1] R o R = 2 => N_rows = 2 = 4 c

C = 1 D A2 WL[2]

N_columns = 2c x M = 4 w

N = R + C = 3 R WL[3] Array size = N_rows x N_columns = 16 A 0 Column Decoder A0! clocking and control -> sense amplifiers WE! , OE! write circuitry

9 STMicro/Intel/UCSD/THNUEE141 Memory SRAM Read Timing (typical)

ß tAA (access time for address): time for stable output after a change in address.

ß tACS (access time for chip select): time for stable output after CS is asserted.

ß tOE (output enable time): time for low impedance when OE and CS are both asserted.

ß tOZ (output-disable time): time to high-impedance state when OE or CS are negated.

ß tOH (output-hold time): time data remains valid after a change to the address inputs.

10 STMicro/Intel/UCSD/THNUEE141 Memory SRAM Read Timing (typical)

ADDR stable stable stable

í tAA Max(tAA, tACS)

CS_L

tOH tACS

OE_L

tAA tOZ tOE tOZ tOE

DOUT valid valid valid

WE_L = HIGH

11 STMicro/Intel/UCSD/THNUEE141 Memory SRAM write cycle timing

~WE controlled

~CS controlled

12 STMicro/Intel/UCSD/THNUEE141 Memory SRAM Cell Design

ß Memory arrays are large ° Need to optimize cell design for area and performance ° Peripheral circuits can be complex œ 60-80% area in array, 20-40% in periphery ß Classical Memory cell design ° 6T cell full CMOS ° 4T cell with high resistance poly load ° TFT load cell

13 STMicro/Intel/UCSD/THNUEE141 Memory Anatomy of the SRAM Cell

Write: •set bit lines to new data value Read: •b‘ = ~b •set bit lines high •raise word line to —high“ •set word line high •sets cell to new state •see which bit line goes low •Low impedance bit-lines •High impedance bit lines 14 STMicro/Intel/UCSD/THNUEE141 Memory SRAM Cell Operating Principle

•Inverter Amplifies •Negative gain •Slope < œ1 in middle •Saturates at ends • Inverter Pair Amplifies •Positive gain •Slope > 1 in middle •Saturates at ends 15 STMicro/Intel/UCSD/THNUEE141 Memory Bistable Element Stability ° Require Vin = V2 ° Stable at endpoints recover from pertubation ° Metastable in middle Fall out when perturbed

Ball on Ramp Analogy 16 STMicro/Intel/UCSD/THNUEE141 Memory Cell Static Noise Margin Cell state may be disturbed by •DC •Layout pattern offset •Process mismatches •non-uniformity of implantation •gate pattern size errors •AC •Alpha particles •Crosstalk SNM (static noise margin) •Voltage supply ripple = Maximum Value of Vn •Thermal noise not flipping cell state

17 STMicro/Intel/UCSD/THNUEE141 Memory SNM: Butterfly Curves

SNM

2 SNM 1

2 1 1 2

18 STMicro/Intel/UCSD/THNUEE141 Memory SNM for Poly Load Cell

19 STMicro/Intel/UCSD/THNUEE141 Memory bit 12T SRAM Cell write

ß Basic building block: write_b

SRAM Cell read ° 1-bit/cell (noise margin again) read_b ß 12-transistor (12T) SRAM cell ° Latch with TM-gate write ° Separately buffered read

20 STMicro/Intel/UCSD/THNUEE141 Memory 6T SRAM Cell ß Cell size accounts for most of array size ° Reduce cell size at cost of complexity/margins ß 6T SRAM Cell ß Read: ° Precharge bit, bit_b bit bit_b ° Raise wordline word ß Write: ° Drive data onto bit, bit_b ° Raise wordline

21 STMicro/Intel/UCSD/THNUEE141 Memory SRAM Design

TI 65nm: IBM 65nm: Intel 65nm: 0.46x1.06um2 0.41x1.25um2 0.46x1.24um2

* Figures courtesy A. Chatterjee et al., P. Bai et al., and Z. Luo et al., Int. Electron Device Meeting Tech. Digest, 2004

22 STMicro/Intel/UCSD/THNUEE141 Memory Vertical 6T Cell Layout B- B+ N Well Connection

VDD

PMOS Pull Up

Q/ Q

NMOS Pull Down GND

SEL

SEL MOSFET

Substrate Connection 23 STMicro/Intel/UCSD/THNUEE141 Memory 6T SRAM Array Layout

24 STMicro/Intel/UCSD/THNUEE141 Memory SRAM Bitcell Design WL VSS VDD BL

VDD PU2 PD2 PU2 PG1 PU1 WL WL NL NL NR NR NL NR PG1 PG2 PD1 PU1 PG2 PD2 PD1 VSS BLB BL BLB VDD VSS Schematic Layout Micrograph ß Requirements of SRAM bitcell design ° Stable read operation: Do not disturb data when reading ° Stable write operation: Must write data within a specified time ° Stable data retention: Data should not be lost ß Typical transistor sizing ° Cell ratio (= I(PD) / I(PG)) = 1.5 ~ 2.5 ° Pull-up ratio (= I(PU) / I(PG)) = 0.5 25 STMicro/Intel/UCSD/THNUEE141 Memory Bitcell Assembly

26 STMicro/Intel/UCSD/THNUEE141 Memory Bitcell Array

27 STMicro/Intel/UCSD/THNUEE141 Memory Detailed SRAM Bitcell Layout

œ Vertical: 2 poly pitch œ Horizontal: 5 contact pitch œ Poly-to-contact space > overlay + spacer + strain_layer + CD_control (6.4nm*) (ö 8nm**) (ö10nm**) (ö 2.6nm*) = 27nm œ 1 poly pitch = 2 poly_to_contact + poly_width + contact_width ö 54 + 32 + 45** = 131 nm A pitch is a multiple of a drawing grid for fine-grain pattern placement Ex.: 5 grid per pitch Ï drawing grid = (131/5) = 26 nm poly CNT Ex.: 6 grid per pitch Ï drawing grid = (13* From1/6) ITRS = 3222nm nmtech. spacer ** From S. Verhaegen et al., SPIE Adv. Litho., 2008 Strain layer

28 STMicro/Intel/UCSD/THNUEE141 Memory SRAM Read

bit bit_b ß Precharge both bitlines highword P1 P2 ß Then turn on wordline N2 N4 A A_b ß One of the two bitlines will N1 N3 ° be pulled down by the cell ß Ex: A = 0, A_b = 1 A_b bit_b ° bit discharges, bit_b stays high1.5

1.0 ° But A bumps up slightly word bit ß Read stability 0.5 A ° A must not flip 0.0 0 100 200 300 400 500 600 ° N1 >> N2 time (ps) 29 STMicro/Intel/UCSD/THNUEE141 Memory bit bit_b word P1 P2 N2 N4 A A_b N1 N3

SRAM Read, 0 is stored in the cell

30 STMicro/Intel/UCSD/THNUEE141 Memory bit bit_b word SRAM Write P1 P2 N2 N4 ß Drive one bitline high, other low A A_b N1 N3 ß Then turn on wordline ß Bitlines overpower cell ß Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 ° Force A_b low, then A rises high

ß Writability A_b

° Must overpower feedback 1.5 A

° P2 << N4 to force A_b low, bit_b 1.0 ° N1 turns off, P1 turns on, 0.5 ° raise A high as desired word

0.0 0 100 200 300 400 500 600 700 time (ps) 31 STMicro/Intel/UCSD/THNUEE141 Memory SRAM Sizing

ß High bitlines must not overpower inverters during reads ß But low bitlines must write new value

into cell bit bit_b word weak med med A A_b strong

32 STMicro/Intel/UCSD/THNUEE141 Memory SRAM Column Example read write Bitline Conditioning

f2 More Cells word_q1 bit_b_v bit_v SRAM Cell 1 1 f f write_q1

data_s1

33 STMicro/Intel/UCSD/THNUEE141 Memory Decoders

ß n:2n decoder consists of 2n n-input AND gates ° One needed for each row of memory ° Build AND from NAND or NOR gate choose minimum size to reduce load on the address lines A1 A0 A1 A0 1/2 4 16 1 1 8 word word A0 A1 2 8 A1 1 4 1 1 A0 1

word0 word0 word1 word1 Pseudo-nMOS word2 static word2 word3 word3

34 STMicro/Intel/UCSD/THNUEE141 Memory Single Pass-Gate Mux

A1 A0

B0 B1 B2 B3

bitlines propagate through 1 transistor

35 STMicro/Intel/UCSD/THNUEE141 Memory Decoder Layout

ß Decoders must be pitch-matched to SRAM cell ° Requires very skinny gates

A3 A3 A2 A2 A1 A1 A0 A0

VDD

word

GND

NAND gate buffer inverter

36 STMicro/Intel/UCSD/THNUEE141 Memory Large Decoders

ß For n > 4, NAND gates become slow ° Break large gates into multiple smaller gates A3 A2 A1 A0

word0

word1

word2

word3

word15

37 STMicro/Intel/UCSD/THNUEE141 Memory Predecoding

ß Many of these gates are redundant ° Factor out common A3 gates into predecoderA2 A1 ° Saves area A0 ° Same path effort predecoders

1 of 4 hot predecoded lines

word0

word1

word2

word3

word15 38 STMicro/Intel/UCSD/THNUEE141 Memory 39 STMicro/Intel/UCSD/THNUEE141 Memory Column Circuitry

ß Some circuitry is required for each column ° Bitline conditioning ° Sense amplifiers ° Column multiplexing ß Each column must have write drivers and read sensing circuits

40 STMicro/Intel/UCSD/THNUEE141 Memory Column Multiplexing

ß Recall that array may be folded for good aspect ratio ß Ex: 2k word x 16 folded into 256 rows x 128 columns ° Must select 16 output bits from the 128 columns ° Requires 16 8:1 column multiplexers

41 STMicro/Intel/UCSD/THNUEE141 Memory Typical Column Access

42 STMicro/Intel/UCSD/THNUEE141 Memory Pass Transistor Based Column Decoder BL3 !BL3 BL2 !BL2 BL1 !BL1 BL0 !BL0

A1 S2

A0 S

inputdecoder NOR 0 2

Data !Data

ß Advantage: speed since there is only one extra transistor in the signal path

ß Disadvantage: large transistor count 43 STMicro/Intel/UCSD/THNUEE141 Memory Tree Decoder Mux

ß Column MUX can use pass transistors ° Use nMOS only, precharge outputs ß One design is to use k series transistors for 2k:1 mux ° No external decoder logic needed

B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A0

A1 A1

A2 A2

Y Y to sense amps and write circuits

44 STMicro/Intel/UCSD/THNUEE141 Memory Ex: 2-way Muxed SRAM

More More Cells Cells word_q1

2-to-1 mux

A0 A0

write0_q1 f2 write1_q1 two bits from two cells and data_v1 selected by A0

45 STMicro/Intel/UCSD/THNUEE141 Memory Bitline Conditioning

ß Precharge bitlines high before reads

f f bit bit_b bit bit_b

ß Equalize bitlines to minimize voltage difference when using sense amplifiers

46 STMicro/Intel/UCSD/THNUEE141 Memory Sense Amplifiers

ß Bitlines have many cells attached ° Ex: 32-kbit SRAM has 256 rows x 128 cols ° 128 cells on each bitline

ß tpd î (C/I) DV ° Even with shared diffusion contacts, 64C of diffusion capacitance (big C) ° Discharged slowly through small transistors (small I) ß Sense amplifiers are triggered on small voltage swing (reduce DV)

47 STMicro/Intel/UCSD/THNUEE141 Memory Differential Pair Amp

ß Differential pair requires no clock ß But always dissipates static power

P1 P2 sense_b sense bitN1 N2 bit_b

48 STMicro/Intel/UCSD/THNUEE141 Memory Clocked Sense Amp

ß Clocked sense amp saves power ß Requires sense_clk after enough bitline swing ß Isolation transistors cut off large bitline capacitance

bit bit_b

sense_clk isolation transistors

regenerative feedback

sense sense_b

49 STMicro/Intel/UCSD/THNUEE141 Memory Sense Amp Waveforms 1ns / div bit 200mV bit‘

wordlineå wordlineå begin precharging bit lines

BIT 2.5V BIT‘

sense clkå sense clké 50 STMicro/Intel/UCSD/THNUEE141 Memory Write Driver Circuits

51 STMicro/Intel/UCSD/THNUEE141 Memory Dual-Ported SRAM

ß Simple dual-ported SRAM ° Two independent single-ended reads bit bit_b ° Or one differential write wordA wordB wordA reads bit_b (complementary) wordB reads bit (true)

ß Do two reads and one write by time multiplexing 52 STMicro/Intel/UCSD/THNUEE141 ° Read during ph1, write during ph2 Memory Multiple Ports

ß We have considered single-ported SRAM ° One read or one write on each cycle ß Multiported SRAM are needed for register files ß Examples: ° Multicycle MIPS must read two sources or write a result on some cycles ° Pipelined MIPS must read two sources and write a third result each cycle ° Superscalar MIPS must read and write many sources and results each cycle 53 STMicro/Intel/UCSD/THNUEE141 Memory Multi-Ported SRAM ß Adding more access transistors hurts read stability ß Multiported SRAM isolates reads from state node ß Single-ended design minimizes number of bitlines

bA bB bC bD bE bF bG wordA wordB wordC wordD wordE wordF wordG

write circuits

read circuits

54 STMicro/Intel/UCSD/THNUEE141 Memory Logical effort of RAMs

55 STMicro/Intel/UCSD/THNUEE141 Memory 56 STMicro/Intel/UCSD/THNUEE141 Memory Twisted Bitlines

ß Sense amplifiers also amplify noise ° Coupling noise is severe in modern processes ° Try to couple equally onto bit and bit_b ° Done by twisting bitlines

b0 b0_b b1 b1_b b2 b2_b b3 b3_b

57 STMicro/Intel/UCSD/THNUEE141 Memory Alternative SRAM Cells

ß Low Voltage/High Leakage/Process Variations crowd the operating margins of conventional SRAM ß Alternative Sense Amplifiers, column and row arrangements, adaptive timing, smaller hierarchy, redundant and spare rows/columns have all been addressed in the literature with some success. ß Some problems come from the cell design itselfœ modifying the cell can break conflicting demands for optimization

58 STMicro/Intel/UCSD/THNUEE141 Memory 10T

ß Features ° BL Leakage reduction ß Approaches ° Separated Read port ° Stacked effect by M10 ß Performance ° 400mV@475kHz, 3.28uW ° 320mV W/O Read error@27ā ° 380mV W/O Write error@27ā ° Vmin=300mV@1% bit errors ° 256 bits/BL A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation B. Calhoun & A. Chandrakasan, JSSC,5 92007 STMicro/Intel/UCSD/THNUEE141 Memory 10T

ß Features ° BL leakage reduction of data ß Approaches ° Virtual GND Replica ° Reverse Short Channel Effect ° BL Writeback ß Performance ° 0.2V@100kHz, 2uW ° 1024 bits/BL ° 130nm process technology

A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and

Virtual Ground Replica Scheme60 STMicro/Intel/UCSD/THNUEE141 Chris Kim, ISSCC,Memory 2007 10T

ß Features ° ST cell array can work @160mV ° 2.1x larger than 6T cell ß Approaches ° Schmitt Trigger based cell ° Good stability @ LowVDD ° Good scalability ß Performance ° Read SNMĉ1.56x @VDD=0.4V ° More power saving ° Leakage powerċ18% ° Dynamic powerċ50% ° Hold SNM @150mV is 2.3x of 6T ° 130nm process A 160mV Robust Schmitt Trigger Based Subthreshold SRAM

K. Roy, JSSC, 200761 STMicro/Intel/UCSD/THNUEE141 Memory 9T ß Features ° Modifying from 10Tcell ° 17% more area than 6T cell ° 16.5% less area than 10T cell ß Approaches ° More leakage saving than 8T cell ° Separated read port ß Performance ° 128 bits/BL @350mV ,100MHz ° Hold SNM=117mV @300mV ° Stand-by power: 6uW ° 65nm process A 100MHz to 1GHz, 0.35V to 1.5V Supply 256x64 SRAM Block using Symmetrized 9T SRAM cell with controlled Read S. A. Verkila,et al, Conference on VLSI Design, 2008 62 STMicro/Intel/UCSD/THNUEE141 Memory 9T ß Features ° Read stability enhancement ° Leakage power reduction ß Approaches ° Separated read port ° Min. sizing of N3, N4 and negative Vg7, and larger Node3 during stand-by mode for leakage reduction ß Performance ° 2x R-SNM cf. 6T ° 22.9% leakage power reduction ° 65 nm PTM High Read Stability and Low Leakage Cache Memory Cell

Z. Liu and V. Kursun, IEEE Conference, 200763 STMicro/Intel/UCSD/THNUEE141 Memory 8T

ß Features ° No read disturb ° About 30% area penalty ß Approaches ° Separate Read & Write WL ° Separated read port ß Performance ° Larger SNM than 6T ° Better scalability than 6T

Stable SRM Cell Design for the 32nm Node and Beyond Leland Chang et. al, Symp. on VLSI,200564 STMicro/Intel/UCSD/THNUEE141 Memory 8T ß Features ° No read disturb ° Low VDD(350mV) ° Low subthreshold(Sub. Vt) leakage ß Approaches ° Separate Read &Write WL ° Separated read port ° Foot-drivers reduce the sub.Vt leakage ß Performance ° 65nm process ,128 cells/row ° Operating @ 25KHz ° 2.2uW leakage power

A 256kb 65nm 8T Subhreshold SRAM Employing Sense-Amplifier Redundancy65 STMicro/Intel/UCSD/THNUEE141 N. Verma ,and A. P. Chandrakasan, MemoryJSSC,2008 7T ß Features ° 23% smaller than Conv. 6T bitcell ° Low VDD(440mV) ° Not suit for low speed demand ß Approaches ° Separate Read &Write WL ° Seperate Read &Write BL ° Data protection nMOS:N5 ß Performance ° 20ns access [email protected] ° 90nm process

A Read-Static-Noise-Margin-Free SRAM Cell forLow-VDD

66 and STMicro/Intel/UCSD/THNUEE141 High-Speed Applications NEC, JSSC,Memory 2006 7T ß Features ° 90% power saving ß Approaches ° BL swing: VDD/6 ß Performance ° 0.35um proces ° Leakage not controlled well

90% Write Power-Saving SRAM Using Sense-Amplifying Memory Cell T. Sakurai et. al., JSSC, 2004 67 STMicro/Intel/UCSD/THNUEE141 Memory 7T ß Features ° Low write power ° SNM is effected by —Read pattern“ (Read 0-N2,P2,N4 & Read 1- N1,P1,N3,N5) ° 17.5% larger than 6T ß Approaches ° Reducing write power by cut off the (feedback) connection to BL ß Performance ° 0.18um proces ° 49% write power saving Novel 7T SRAM Cell For Low Power Cache Design R. Aly, M. Faisal and A. Bayoumi 68 STMicro/Intel/UCSD/THNUEE141 IEEE SoC Conf.,Memory 2005 6T

• Features BL œ Single-ended WL œ Low VDD • Approaches œ Adjustable header/footer (virVDD, virGND)

• Performance WL œ VDD range: 1.2V~193mV œ Vmin=170mV with 2% redundancy

A Sub-200mV 6T SRAM in 0.13m CMOS ISSCC, 200769 STMicro/Intel/UCSD/THNUEE141 Memory 5T • Features œ Single-ended œ Single BL, Single WL œ Area 23% smaller than 6T • Approaches œ BL precharge to Vpc=600mV œ Asymmetric cell sizing œ Differential SA is used for Read • Performance œ 75% BL leakage reduction cf. 6T œ SNM is 50% lower than the 6T‘s œ 0.18um process High-skewed Low-skewed Inverter Inverter

A High Density, Low Leakage, 5T SRAM for Embeded

Caches70 STMicro/Intel/UCSD/THNUEE141 I. Carlson et.al., ESSCIRC,Memory 2004 Example Electrical Design: UCSD 32nm prototype • Butterfly (read stability) • SPICE Model: • N-curves (read and write stability) œ 32nm HKMG (high-

• Iread (read stability and access K/metal-gate) from time) PTM VDD • HOLD (data retention) • Reference Design

• Ileakage (power and data retention) œ Scaled bitcell from TSMC 90nm bitcell

32nm scaled from 32nm proposed TSMC 90nm TSMC 90nm (for 30x12, 25x12) (REFERENCE) L (nm) W (nm) L (nm) W (nm) L (nm) W (nm) Pull-up 100 100 32 32 32 44 Pull-down 100 175 32 56 32 88 Pass-Gate 115 120 37 38 32 44

71 STMicro/Intel/UCSD/THNUEE141 Memory Butterfly and N-Curves • Measure method œ Increase VR and measure VL œ Increase VL and measure VR œ Make voltage transfer curve in VR and VL axes ‰ Butterfly

œ Measure Iin ‰ N-curve

72 STMicro/Intel/UCSD/THNUEE141 Memory Iread, Ileakage and VDDHOLD

° Iread / ° Measure bitline current when WL WL switches to high VDD ° ILEAKAGE A1 A2 ° Measure VDD (or VSS) current when ”1‘ nr C1 nl C2 WL=0 ”0‘ B1 B2 ° VDDHOLD ° Decreasing VDD voltage, while WL=0 BLb BL ”1‘ ”1‘ ° Measure minimum VDD voltage when | V(nl) - V(nr) | = ”sensing margin‘ (100mV is assumed) 32nm proposed REFERENCE (for 30x12 and 25x12)

Iread 41.2 uA 66.7 uA

Ileakage 85.4 nA 142.7 nA

VDDHOLD 110 mV 118 mV 73 STMicro/Intel/UCSD/THNUEE141 Memory Corner Simulation: Butterfly and N- Curve

9 9 9 {{ / bb / CC / 9 {{ / 9 bb / 9 CC / • Three candidate {{ / layouts across 9 9 bb / 9 CC / 9 operating corners9 show little9 9 9 9 9 difference 9 9 9 9 9

9 9 9

9 9 9 9 9 9 9 9 9 9 9 9 9 9 (SS, 125degC, 1.0V) (NN, 25degC, 1.0V) (FF, -40degC, 1.0V)

74 STMicro/Intel/UCSD/THNUEE141 Memory Corner Simulation: Iread ,Ileakage and VDDHOLD

Iread (A) Ileakage (A) 9 9 9 CC 9 CC 9 CC CC 9 CC 9 CC 9 bb bb 9 9 bb bb bb bb 9 9 {{ {{ 9 {{ 9 {{ 9 {{ {{ 9 9 VDD (V)

0.13 0.128 0.126 VDD (V) 0.124 HOLD 0.122 0.12 0.118 0.116 0.114 0.112 25x10 25x12 30x12 25x10 25x12 30x12 25x10 25x12 30x12

FF, -40 NN, 25 SS, 125 75 STMicro/Intel/UCSD/THNUEE141 Memory Processor Memory Bandwidth/Pins

76 STMicro/Intel/UCSD/THNUEE141 Memory GPU Bandwidth/Core (local and PCIe)

77 STMicro/Intel/UCSD/THNUEE141 Memory 78 STMicro/Intel/UCSD/THNUEE141 Memory Why 3D DRAM?

79 STMicro/Intel/UCSD/THNUEE141 Memory