Array Structured Memories STMicro/Intel UCSD CAD LAB Weste Text 1 STMicro/Intel/UCSD/THNUEE141 Memory Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory Read nly Memory Shift Registers &ueues (RAM) (R M) (Volatile) (Nonvolatile) Serial In Parallel In First In Last In Static RAM Dynamic RAM Parallel ut Serial ut First ut First ut (SRAM) (DRAM) (SIP ) (PIS ) (FIF ) (LIF ) Mask ROM Programmable Erasable Electrically Flash R M R M Programmable Erasable (PR M) R M Programmable (EPR M) R M (EEPR M) 2 STMicro/Intel/UCSD/THNUEE141 Memory Feature Comparison Between Memory Types 3 STMicro/Intel/UCSD/THNUEE141 Memory 4 STMicro/Intel/UCSD/THNUEE141 Memory Array Architecture 2n words of 2m bits each If n ++ m, fold by 2k into fewer rows of more columns bitline conditioning wordlines bitlines row decoder row memory cells: 2n-k rows x 2m1k columns n-k k column circuitry n column decoder 2m bits Good regularity . easy to design Very high density if good cells are used 5 STMicro/Intel/UCSD/THNUEE141 Memory Memory - eal Organization Array of N x 3 words ------------- columns ------------ 3xM S0 C of M bit words row 0 ------------- rowsR------------ C of M bit words row 1 C of M bit words row 2 Log2R Row Address Decoder Lines C of M bit words row N-2 C of M bit words row N-1 SR-1 ---- xM bits - - - - Log2C Address Column Select Lines M bit data word 6 STMicro/Intel/UCSD/THNUEE141 Memory Hierarchical Memory Architecture ow Address Column Address Block Address Global Data Bus Control Block Selector Global Circuitry Amplifier/Driver I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings 7 STMicro/Intel/UCSD/THNUEE141 Memory Array Organization Design Issues aspect ratio should be relative square ° Row / Column organisation (matri ) ° R " log2(N_rows)$ C " log2(N_columns) ° R % C " N (N_address_bits) number of rows should be power of 2 ° number of bits in a row need not be' sense amplifiers to speed voltage swing 1 -( 2R row decoder 1 -( 2C column decoder ° M column decoders (M bits, one per bit) . M " output word width 8 STMicro/Intel/UCSD/THNUEE141 Memory Simple 4x4 S AM Memory read precharge bit line precharge enable WL405 BL 7BL r A1 e 2 bit width: M"2 d WL415 R o R " 2 "( N_rows " 2 " 4 c e C " 1 D A2 WL425 N_columns " 2c M " 4 w o N " R % C " , R WL485 Arra. si/e " N_rows N_columns " 10 A 0 Column Decoder A07 clocking and control -+ sense amplifiers WE7 , E7 write circuitry 9 STMicro/Intel/UCSD/THNUEE141 Memory S AM ead Timing (typical, tAA (access time for address): time for stable output after a change in address. tAC2 (access time for chip select): time for stable output after C2 is asserted. t3E (output enable time): time for low impedance when 3E and C2 are both asserted. t35 (output-disable time): time to high-impedance state when 3E or C2 are negated. t36 (output-hold time): time data remains valid after a change to the address inputs. 10 STMicro/Intel/UCSD/THNUEE141 Memory S AM ead Timing (typical, ADDR stable stable stable tAA Max(tAA, tACS) CS_L tOH tACS E_L tAA tOZ tOE tOZ tOE D UT valid valid valid WE_L : HIGH 11 STMicro/Intel/UCSD/THNUEE141 Memory SRAM write cycle timing WE controlled CS controlled 12 STMicro/Intel/UCSD/THNUEE141 Memory S AM Cell Design Memory arrays are large ° Need to optimize cell design for area and performance ° Peripheral circuits can be complex . 60-80% area in array, 20-40% in periphery Classical Memory cell design ° 6T cell full CM S ° 4T cell with high resistance poly load ° TFT load cell 13 STMicro/Intel/UCSD/THNUEE141 Memory Anatomy of the S AM Cell Write: set bit lines to new data value Read: b7 " 8b set bit lines high raise word line to —high: set word line high sets cell to new state see which bit line goes low Low impedance bit-lines 6igh impedance bit lines 14 STMicro/Intel/UCSD/THNUEE141 Memory S AM Cell Operating Principle Inverter Amplifies Negative gain 2lope < =1 in middle 2aturates at ends Inverter Pair Amplifies Positive gain 2lope ( 1 in middle 2aturates at ends 15 STMicro/Intel/UCSD/THNUEE141 Memory Bistable .lement 2tabilit. ° Require Vin " V2 ° 2table at endpoints recover from pertubation ° Metastable in middle Fall out when perturbed Aall on Ramp Analog. 16 STMicro/Intel/UCSD/THNUEE141 Memory Cell Static Noise Margin Cell state ma. be disturbed b. DC La.out pattern offset Process mismatches non-uniformity of implantation gate pattern size errors AC Alpha particles CrosstalC SNM (static noise margin) Voltage suppl. ripple / Maximum Value of Vn Thermal noise not flipping cell state 17 STMicro/Intel/UCSD/THNUEE141 Memory SNM1 Butterfly Curves 1 SNM 2 2 SNM 1 2 1 1 2 18 STMicro/Intel/UCSD/THNUEE141 Memory SNM for Poly 2oad Cell 19 STMicro/Intel/UCSD/THNUEE141 Memory bit 12T S AM Cell write Aasic building blocC: write_b 2RAM Cell read ° 1-bit/cell (noise margin again) read_b 12-transistor (12T) 2RAM cell ° Latch with TM-gate write ° 2eparatel. buffered read 20 STMicro/Intel/UCSD/THNUEE141 Memory 5T S AM Cell Cell size accounts for most of array size ° Reduce cell size at cost of complexity/margins 6T SRAM Cell Read0 ° Precharge bit, bit_b bit bit_b ° Raise wordline word Write0 ° Drive data onto bit, bit_b ° Raise wordline 21 STMicro/Intel/UCSD/THNUEE141 Memory S AM Design TI 0Enm: IAM 0Enm: Intel 0Enm: 0.40 1.00um2 0.41 1.2Eum2 0.40 1.24um2 Figures courtesy A. ChatterAee et al., P. Bai et al., and B. Luo et al., Int. Electron Device Meeting Tech. Digest, 2004 22 STMicro/Intel/UCSD/THNUEE141 Memory 0ertical 5T Cell 2ayout B- B1 N Well Connection VDD PM S Pull Up &/ & NM S Pull Down GND SEL SEL M SFET Substrate Connection 23 STMicro/Intel/UCSD/THNUEE141 Memory 5T S AM Array 2ayout 24 STMicro/Intel/UCSD/THNUEE141 Memory S AM Bitcell Design WL V22 VDD AL VDD PU2 PD2 PU2 PF1 PU1 WL WL NL NL NR NR NL NR PF1 PF2 PD1 PU1 PF2 PD2 PD1 V22 ALA AL ALA VDD V22 2chematic La.out Micrograph ReCuirements of SRAM bitcell design ° 2table read operation0 Do not disturb data when reading ° 2table write operation0 Must write data within a specified time ° 2table data retention0 Data should not be lost Typical transistor sizing ° Cell ratio (: I(PD) / I(PG)) : 1.5 2.5 ° Pull-up ratio (: I(PU) / I(PG)) : 0.5 25 STMicro/Intel/UCSD/THNUEE141 Memory Bitcell Assembly 26 STMicro/Intel/UCSD/THNUEE141 Memory Bitcell Array 27 STMicro/Intel/UCSD/THNUEE141 Memory Detailed S AM Bitcell 2ayout . Vertical0 2 poly pitch . Horizontal0 5 contact pitch . Poly-to-contact space + overlay 1 spacer 1 strain_layer 1 CD_control (6.4nm) ( 8nm) (10nm) ( 2.6nm) : 27nm . 1 pol. pitch : 2 poly_to_contact 1 poly_width 1 contact_width 54 1 82 1 45 : 181 nm A pitch is a multiple of a drawing grid for fine-grain pattern placement Ex.0 5 grid per pitch drawing grid : (181/5) : 26 nm pol. CNT Ex.0 6 grid per pitch drawing grid : (18 From1/6) ITRS : 8222nm nmtech. spacer From S. Verhaegen et al., SPIE Adv. Litho., 2008 2train la.er 28 STMicro/Intel/UCSD/THNUEE141 Memory S AM ead bit bit_b Precharge both bitlines highword P1 P2 Then turn on wordline N2 N4 A A_b ne of the two bitlines will N1 N8 ° be pulled down by the cell Ex0 A : 0, A_b : 1 A_b bit_b ° bit discharges, bit_b stays high1.5 1.0 ° But A bumps up slightly word bit Read stability 0.5 A ° A must not flip 0.0 0 100 200 800 400 500 600 ° N1 ++ N2 time (ps) 29 STMicro/Intel/UCSD/THNUEE141 Memory bit bit_b word P1 P2 N2 N4 A A_b N1 N8 S AM Read, 0 is stored in the cell 30 STMicro/Intel/UCSD/THNUEE141 Memory bit bit_b word S AM 8rite P1 P2 N2 N4 Drive one bitline high, other low A A_b N1 N8 Then turn on wordline Aitlines overpower cell E : A " 0, A_b " 1, bit " 1, bit_b " 0 ° Force A_b low, then A rises high Writability A_b ° Must overpower feedbacC 1.5 A ° P2 << N4 to force A_b low, bit_b 1.0 ° N1 turns off, P1 turns on, 0.5 ° raise A high as desired word 0.0 0 100 200 800 400 500 600 700 time (ps) 31 STMicro/Intel/UCSD/THNUEE141 Memory S AM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell bit bit_b word weak med med A A_b strong 32 STMicro/Intel/UCSD/THNUEE141 Memory S AM Column .xample read write Bitline Conditioning f2 More Cells word_C1 bit_b_v bit_v SRAM Cell 1 1 f f write_C1 data_s1 33 STMicro/Intel/UCSD/THNUEE141 Memory Decoders n02n decoder consists of 2n n-input AND gates ° ne needed for each row of memory ° Build AND from NAND or N R gate choose minimum size to reduce load on the address lines A1 A0 A1 A0 1/2 4 16 1 1 8 word word A0 A1 2 8 A1 1 4 1 1 A0 1 word0 word0 word1 word1 Pse do-nMOS word2 static word2 word8 word8 34 STMicro/Intel/UCSD/THNUEE141 Memory Single Pass-Gate Mux A1 A0 B0 B1 B2 B8 bitlines propagate through 1 transistor E 35 STMicro/Intel/UCSD/THNUEE141 Memory Decoder 2ayout Decoders must be pitch-matched to SRAM cell ° ReCuires very skinny gates A8 A8 A2 A2 A1 A1 A0 A0 VDD word GND NAND gate buffer inverter 36 STMicro/Intel/UCSD/THNUEE141 Memory 2arge Decoders For n ( 4, NAND gates become slow ° AreaC large gates into multiple smaller gates A8 A2 A1 A0 word0 word1 word2 word8 word15 37 STMicro/Intel/UCSD/THNUEE141 Memory Predecoding Many of these gates are redundant ° Factor out common A8 gates into predecoderA2 A1 ° Saves area A0 ° Same path effort predecoders 1 of 4 hot predecoded lines word0 word1 word2 word8 word15 38 STMicro/Intel/UCSD/THNUEE141 Memory 39 STMicro/Intel/UCSD/THNUEE141 Memory Column Circuitry Some circuitry is reCuired for each column ° Bitline conditioning ° Sense amplifiers ° Column multiplexing Each column