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Board Design Layout Guidelines; External Memory Interface Handbook External Memory Interface Handbook Volume 2 Section II. Board Planning External Memory Interface Handbook Volume 2 Section II. Board Planning 101 Innovation Drive San Jose, CA 95134 www.altera.com EMI_PLAN_BOARD-3.0 Document last updated for Altera Complete Design Suite version: 11.0 Document publication date: June 2011 Subscribe © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. External Memory Interface Handbook Volume 2 June 2011 Altera Corporation Section II. Board Planning Contents Chapter 1. DDR2 and DDR3 SDRAM Interface Termination and Layout Guidelines Leveling and Dynamic ODT . 1–2 Read and Write Leveling . 1–2 Calibrated Output Impedance and ODT . 1–4 Dynamic ODT . 1–4 Dynamic OCT in Stratix III and Stratix IV Devices . 1–5 Dynamic OCT in Stratix V Devices . 1–7 Board Termination for DDR2 SDRAM . 1–7 External Parallel Termination . 1–8 On-Chip Termination . 1–9 Recommended Termination Schemes . 1–10 Dynamic On-Chip Termination . 1–12 FPGA Writing to Memory . 1–13 FPGA Reading from Memory . 1–16 On-Chip Termination (Non-Dynamic) . 1–17 Class II External Parallel Termination . 1–20 FPGA Writing to Memory . 1–20 FPGA Reading from Memory . 1–23 Class I External Parallel Termination . 1–25 FPGA Writing to Memory . 1–26 FPGA Reading from Memory . 1–27 Class I Termination Using ODT . 1–29 FPGA Writing to Memory . 1–29 FPGA Reading from Memory . 1–31 No-Parallel Termination . 1–31 FPGA Writing to Memory . 1–31 FPGA Reading from Memory . 1–33 Board Termination for DDR3 SDRAM . 1–36 Single-Rank DDR3 SDRAM Unbuffered DIMM . 1–36 DQS, DQ, and DM for DDR3 SDRAM UDIMM . 1–38 Memory Clocks for DDR3 SDRAM UDIMM . 1–40 Commands and Addresses for DDR3 SDRAM UDIMM . 1–42 Stratix III, Stratix IV, and Stratix V FPGAs . 1–43 DQS, DQ, and DM for Stratix III, Stratix IV, and Stratix V FPGA . 1–43 Memory Clocks for Stratix III, Stratix IV, and Stratix V FPGA . 1–44 Commands and Addresses for Stratix III and Stratix IV FPGA . 1–44 Multi-Rank DDR3 SDRAM Unbuffered DIMM . 1–44 DDR3 SDRAM Registered DIMM . 1–46 DDR3 SDRAM Components With Leveling . 1–46 DDR3 SDRAM Components With or Without Leveling . 1–46 Stratix III, Stratix IV, and Stratix V FPGAs . 1–50 Drive Strength . 1–51 How Strong is Strong Enough? . 1–52 System Loading . 1–53 Component Versus DIMM . 1–53 FPGA Writing to Memory . 1–53 FPGA Reading from Memory . 1–55 Single- Versus Dual-Rank DIMM . 1–56 Single DIMM Versus Multiple DIMMs . 1–58 June 2011 Altera Corporation External Memory Interface Handbook Volume 2 Section II. Board Planning iv Contents Design Layout Guidelines . 1–58 Layout Guidelines for DDR2 SDRAM Interface . 1–58 Layout Guidelines for DDR3 SDRAM Interface . 1–61 Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits) . 1–66 Fly-By Network Design for Clock, Command, and Address Signals . 1–66 Chapter 2. Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines DDR2 SDRAM . 2–1 Stratix II High Speed Board . 2–2 Overview of ODT Control . 2–3 DIMM Configuration . 2–5 Dual-DIMM Memory Interface with Slot 1 Populated . 2–5 FPGA Writing to Memory . ..
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