CPY Document
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
Zynq-7000 All Programmable Soc and 7 Series Devices Memory Interface Solutions User Guide (UG586) [Ref 2]
Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions (v4.1) DS176 April 4, 2018 Advance Product Specification • I/O Power Reduction option reduces average I/O Introduction power by automatically disabling DQ/DQS IBUFs and The Xilinx® Zynq®-7000 All Programmable SoC and internal terminations during writes and periods of 7 series FPGAs memory interface solutions cores provide inactivity high-performance connections to DDR3 and DDR2 • Internal VREF support SDRAMs, QDR II+ SRAM, RLDRAM II/RLDRAM 3, and • LPDDR2 SDRAM. Multicontroller support for up to eight controllers • Two controller request processing modes: DDR3 and DDR2 SDRAMs o Normal: reorder requests to optimize system throughput and latency This section discusses the features, applications, and functional description of Xilinx 7 series FPGAs memory o Strict: memory requests are processed in the order interface solutions in DDR3 and DDR2 SDRAMs. These received solutions are available with an optional AXI4 slave interface. LogiCORE™ IP Facts Table Core Specifics DDR3 SDRAM Features Supported Zynq®-7000 All Programmable SoC (1) • Component support for interface widths up to 72 bits Device Family 7series(2) FPGAs • Supported DDR3 Component and DIMM, DDR2 Single and dual rank UDIMM, RDIMM, and SODIMM Memory support Component and DIMM, QDR II+, RLDRAM II, RLDRAM 3, and LPDDR2 SDRAM Components • DDR3 (1.5V) and DDR3L (1.35V) Resources See Table 1. • 1, 2, 4, and 8 Gb density device support Provided with Core • 8-bank support Documentation Product Specification • x8 and x16 device -
Memory Technology and Trends for High Performance Computing Contract #: MDA904-02-C-0441
Memory Technology and Trends for High Performance Computing Contract #: MDA904-02-C-0441 Contract Institution: Georgia Institute of Technology Project Director: D. Scott Wills Project Report 12 September 2002 — 11 September 2004 This project explored the impact of developing memory technologies on future supercomputers. This activity included both a literature study (see attached whitepaper), plus a more practical exploration of potential memory interfacing techniques using the sponsor recommended HyperTransport interface. The report indicates trends that will affect interconnection network design in future supercomputers. Related publications during the contract period include: 1. P. G. Sassone and D. S. Wills, On the Scaling of the Atlas Chip-Scale Multiprocessor, to appear in IEEE Transaction on Computers. 2. P. G. Sassone and D. S. Wills, Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication, to appear in IEEE/ACM International Symposium on Microarchitecture, Portland, OR, December 2004. 3. B. A. Small, A. Shacham, K. Bergman, K. Athikulwongse, C. Hawkins, and D. S. Wills, Emulation of Realistic Network Traffic Patterns on an Eight-Node Data Vortex Interconnection Network Subsystem, to appear in OSA Journal of Optical Networking. 4. P. G. Sassone and D. S. Wills, On the Extraction and Analysis of Prevalent Dataflow Patterns, to appear in The IEEE 7th Annual Workshop on Workload Characterization (WWC-7), 8 pages, Austin, TX, October 2004. 5. H. Kim, D. S. Wills, and L. M. Wills, Empirical Analysis of Operand Usage and Transport in Multimedia Applications, in Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications(IWSOC'04), pages 168-171, Banff, Alberta, Canada, July 2004. -
Micron Technology Inc
MICRON TECHNOLOGY INC FORM 10-K (Annual Report) Filed 10/26/10 for the Period Ending 09/02/10 Address 8000 S FEDERAL WAY PO BOX 6 BOISE, ID 83716-9632 Telephone 2083684000 CIK 0000723125 Symbol MU SIC Code 3674 - Semiconductors and Related Devices Industry Semiconductors Sector Technology Fiscal Year 03/10 http://www.edgar-online.com © Copyright 2010, EDGAR Online, Inc. All Rights Reserved. Distribution and use of this document restricted under EDGAR Online, Inc. Terms of Use. UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 10-K (Mark One) ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the fiscal year ended September 2, 2010 OR TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the transition period from to Commission file number 1-10658 Micron Technology, Inc. (Exact name of registrant as specified in its charter) Delaware 75 -1618004 (State or other jurisdiction of (IRS Employer incorporation or organization) Identification No.) 8000 S. Federal Way, Boise, Idaho 83716 -9632 (Address of principal executive offices) (Zip Code) Registrant ’s telephone number, including area code (208) 368 -4000 Securities registered pursuant to Section 12(b) of the Act: Title of each class Name of each exchange on which registered Common Stock, par value $.10 per share NASDAQ Global Select Market Securities registered pursuant to Section 12(g) of the Act: None (Title of Class) Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. -
Architecture of an AHB Compliant SDRAM Memory Controller
International Journal of Innovations in Engineering and Technology (IJIET) Architecture of An AHB Compliant SDRAM Memory Controller S. Lakshma Reddy Metch student, Department of Electronics and Communication Engineering CVSR College of Engineering, Hyderabad, Andhra Pradesh, India A .Krishna Kumari Professor, Department of Electronics and Communication Engineering CVSR College of Engineering, Hyderabad, Andhra Pradesh, India Abstract- -- Microprocessor performance has improved rapidly these years. In contrast, memory latencies and bandwidths have improved little. The result is that the memory access time has been a bottleneck which limits the system performance. As the speed of fetching data from memories is not able to match up with speed of processors. So there is the need for a fast memory controller. The responsibility of the controller is to match the speeds of the processor on one side and memory on the other so that the communication can take place seamlessly. Here we have built a memory controller which is specifically targeted for SDRAM. Certain features were included in the design which could increase the overall efficiency of the controller, such as, searching the internal memory of the controller for the requested data for the most recently used data, instead of going to the Memory to fetch it. The memory controller is designed which compatible with Advanced High-performance Bus (AHB) which is a new generation of AMBA bus. The AHB is for high-performance, high clock frequency system modules. The AHB acts as the high-performance system backbone bus. Index Terms- SDRAM, Memory controller, AMBA, FPGA, Xilinx, I. INTRODUCTION In order to enhance overall performance, SDRAMs offer features including multiple internal banks, burst mode access, and pipelining of operation executions. -
ABSTRACT the Performance Characteristics of Modern DRAM
ABSTRACT Title of dissertation: MODERN DRAM MEMORY SYSTEMS: PERFORMANCE ANALYSIS AND A HIGH PERFORMANCE, POWER-CONSTRAINED DRAM SCHEDULING ALGORITHM David Tawei Wang, Doctor of Philosophy, 2005 Dissertation directed by: Associate Professor Bruce L. Jacob Department of Electrical and Computer Engineer- ing, and Institute for Advanced Computer Studies The performance characteristics of modern DRAM memory systems are impacted by two primary attributes: device datarate and row cycle time. Modern DRAM device dat- arates and row cycle times are scaling at different rates with each successive generation of DRAM devices. As a result, the performance characteristics of modern DRAM memory systems are becoming more difficult to evaluate at the same time that they are increasingly limiting the performance of modern computer systems. In this work, a performance evalua- tion framework that enables abstract performance analysis of DRAM memory systems is presented. The performance evaluation framework enables the performance characteriza- tion of memory systems while fully accounting for the effects of datarates, row cycle times, protocol overheads, device power constraints, and memory system organizations. This dissertation utilizes the described evaluation framework to examine the perfor- mance impact of the number of banks per DRAM device, the effects of relatively static DRAM row cycle times and increasing DRAM device datarates, power limitation con- straints, and data burst lengths in future generations of DRAM devices. Simulation results obtained in the analysis provide insights into DRAM memory system performance charac- teristics including, but not limited to the following observations. • The performance benefit of having a 16 banks over 8 banks increases with increasing datarate. The average performance benefit reaches 18% at 1 Gbps for both open-page and close-page systems. -
Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips
Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips Donghyuk Leeyz Samira Khan@ Lavanya Subramaniany Saugata Ghosey Rachata Ausavarungniruny Gennady Pekhimenkoy{ Vivek Seshadriy{ Onur Mutluyx yCarnegie Mellon University zNVIDIA @University of Virginia {Microsoft Research xETH Zürich ABSTRACT 40.0%/60.5%, which translates to an overall system perfor- Variation has been shown to exist across the cells within mance improvement of 14.7%/13.7%/13.8% (in 2-/4-/8-core a modern DRAM chip. Prior work has studied and exploited systems) across a variety of workloads, while ensuring reli- several forms of variation, such as manufacturing-process- able operation. or temperature-induced variation. We empirically demon- strate a new form of variation that exists within a real DRAM 1 INTRODUCTION chip, induced by the design and placement of different compo- In modern systems, DRAM-based main memory is sig- nents in the DRAM chip: different regions in DRAM, based nificantly slower than the processor. Consequently, pro- on their relative distances from the peripheral structures, cessors spend a long time waiting to access data from require different minimum access latencies for reliable oper- main memory [5, 66], making the long main memory ac- ation. In particular, we show that in most real DRAM chips, cess latency one of the most critical bottlenecks in achiev- cells closer to the peripheral structures can be accessed much ing high performance [48, 64, 67]. Unfortunately, the la- faster than cells that are farther. We call this phenomenon tency of DRAM has remained almost constant in the past design-induced variation in DRAM. -
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access ∗
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access ∗ Niladrish Chatterjee‡ Manjunath Shevgoor‡ Rajeev Balasubramonian‡ Al Davis‡ Zhen Fang§† Ramesh Illikkal∞ Ravi Iyer∞ ‡University of Utah §Nvidia Corporation ∞Intel Labs {nil,shevgoor,rajeev,ald}@cs.utah.edu [email protected] {ramesh.g.illikkal,ravishankar.iyer}@intel.com Abstract of DRAM chips to build and exploit a heterogeneous memory sys- tem. This paper takes an important step in uncovering the potential The DRAM main memory system in modern servers is largely ho- of such a heterogeneous DRAM memory system. mogeneous. In recent years, DRAM manufacturers have produced The DRAM industry already produces chips with varying proper- chips with vastly differing latency and energy characteristics. This ties. Micron offers a Reduced Latency DRAM (RLDRAM) product provides the opportunity to build a heterogeneous main memory sys- that offers lower latency and lower capacity, and is targeted at high tem where different parts of the address space can yield different performance routers, switches, and network processing [7]. Mi- latencies and energy per access. The limited prior work in this area cron also offers a Low Power DRAM (LPDRAM) product that of- has explored smart placement of pages with high activities. In this fers lower energy and longer latencies and that has typically been paper, we propose a novel alternative to exploit DRAM heterogene- employed in the mobile market segment [6]. Our work explores ity. We observe that the critical word in a cache line can be easily innovations that can exploit a main memory that includes regular recognized beforehand and placed in a low-latency region of the DDR chips as well as RLDRAM and LPDRAM chips. -
Dynamic Rams from Asynchrounos to DDR4
Dynamic RAMs From Asynchrounos to DDR4 PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sun, 10 Feb 2013 17:59:42 UTC Contents Articles Dynamic random-access memory 1 Synchronous dynamic random-access memory 14 DDR SDRAM 27 DDR2 SDRAM 33 DDR3 SDRAM 37 DDR4 SDRAM 43 References Article Sources and Contributors 48 Image Sources, Licenses and Contributors 49 Article Licenses License 50 Dynamic random-access memory 1 Dynamic random-access memory Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. The main memory (the "RAM") in personal computers is dynamic RAM (DRAM). It is the RAM in laptop and workstation computers as well as some of the RAM of video game consoles. The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities. Unlike flash memory, DRAM is volatile memory (cf. non-volatile memory), since it loses its data quickly when power is removed. The transistors and capacitors used are extremely small; billions can fit on a single memory chip. -
Memory Systems Cache, DRAM, Disk
Memory Systems Cache, DRAM, Disk Bruce Jacob University of Maryland at College Park Spencer W. Ng Hitachi Global Storage Technologies David T. Wang MetaRAM With Contributions By Samuel Rodriguez Advanced Micro Devices Xmmmk JÜOBSK'1'"'" AMSTERDAM • BOSTON • HEIDELBERG LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO :<* ELSEVIER Morgan Kaufmann is an imprint of Elsevier MORGAN KAUFMANN PUBLISHERS Preface "It's the Memory, Stupid!" xxxi Overview On Memory Systems and Their Design 1 Ov.l Memory Systems 2 Ov.1.1 Locality ofReference Breeds the Memory Hierarchy 2 Ov.1.2 ImportantFigures ofMerit 7 Ov.1.3 The Goal ofa Memory Hierarchy 10 Ov.2 Four Anecdotes on Modular Design 14 Ov.2.1 Anecdote I: Systemic Behaviors Exist 15 Ov.2.2 Anecdote II: The DLL in DDR SDRAM 17 Ov.2.3 Anecdote III: A Catch-22 in the Search for Bandwidth 18 Ov.2.4 Anecdote IV: Proposais to Exploit Variability in CellLeakage 19 Ov.2.5 Perspective 19 Ov.3 Cross-Cutting Issues 20 Ov.3.1 Cost/Performance Analysis 20 Ov.3.2 Power and Energy 26 Ov.3.3 Reliability 32 Ov.3.4 Virtual Memory 34 Ov.4 An Example Holistic Analysis 41 Ov.4.1 Fully-Buffered DIMM vs. the Disk Cache 41 Ov.4.2 FullyBufferedDIMM: Basics 43 Ov.4.3 Disk Caches: Basics 46 Ov.4.4 Experimental Results 47 Ov.4.5 Conclusions 52 Ov.5 What to Expect 54 IX - X Contents Part I Cache 55 Chapter 1 An Overview of Cache Principles 57 1.1 Caches, 'Caches/ and "Caches" 59 1.2 Locality Principles 62 1.2.1 Temporal Locality 63 1.2.2 Spatial Locality 63 1.2.3 Algorithmic Locality 64 1.2.4 -
MOCA: Memory Object Classification and Allocation in Heterogeneous Memory Systems
MOCA: Memory Object Classification and Allocation in Heterogeneous Memory Systems Aditya Narayan∗, Tiansheng Zhang∗, Shaizeen Agay, Satish Narayanasamyy and Ayse K. Coskun∗ ∗Boston University, Boston, MA 02215, USA; Email: fadityan, tszhang, [email protected] yUniversity of Michigan, Ann Arbor, MI 48109, USA; Email: fshaizeen, [email protected] Abstract—In the era of abundant-data computing, main mem- Traditionally, the main memory (e.g., DRAM) of a com- ory’s latency and power significantly impact overall system puting system is composed of a set of homogeneous memory performance and power. Today’s computing systems are typically modules. The key attributes that determine the efficiency of a composed of homogeneous memory modules, which are optimized to provide either low latency, high bandwidth, or low power. Such memory system are latency, bandwidth, and power. An ideal memory modules do not cater to a wide range of applications with memory system should provide the highest data bandwidth diverse memory access behavior. Thus, heterogeneous memory at the lowest latency with minimum power consumption. systems, which include several memory modules with distinct However, there is no such perfect memory system as a memory performance and power characteristics, are becoming promising module with high performance generally has a high power alternatives. In such a system, allocating applications to their best-fitting memory modules improves system performance and density. Hence, memory modules come in different flavors, energy efficiency. However, such an approach still leaves the optimized to either improve system performance or reduce full potential of heterogeneous memory systems under-utilized power consumption. because not only applications, but also the memory objects within Due to diverse memory access behavior across workloads, a that application differ in their memory access behavior. -
Techniquesfor
TECHNIQUESFOR Design Examples, Signaling and Memory Technologies, Fiber Optics, Modeling and Simulation to Ensure Signal Zntegrity Tom Granberg, P1i.D. PRENTICEHALL PTR UPPER SADDLERIVER, NJ 07458 WWW.PHiTRCOM PTR Preface xxxvii How This Book 1s Organized xxxvii This Textbook Was Written with Educational Institutions in Mind xxxix University Courses for Which This Book 1s Suitable xl Solutions Manual 1s Available xl Cash for Identifying Textbook Errors xl How This Book Was Prepared xli Personal Acknowledgments xli Technical Acknowledgments xliii Part 1 Introduction 1 Chapter 1 Trends in High-Speed Design 1.1 Everything Keeps Getting Faster and Faster! 1.2 Emerging Technologies and Industry Trends 1.2.1 Major Drivers of Printed Circuit Board (PCB) Technology 1.2.2 Drivers of Innovation 1.2.3 110 Signaling Standards 1.2.4 Web Site as Retailer 1.2.5 Memories 1.2.6 On-Die Terminations 1.3 Trends in Bus Architecture 1.3.1 Moving from Parallel to Serial 1.3.2 The Power of Tools 1.3.3 ASSPs and ASMs 1.4 High-Speed Design as an Offshoot from Microwave Theory 1.5 Background Disciplines Needed for High-Speed Design 1.5.1 High-Speed Conferences and Forums 1.6 Book Organization 1.7 Exercises X Contents cha&er 2 ASICs, Backplane Configurations, and SerDes Technology 2.1 Application-Specific Integrated Circuits (ASICs) 2.2 Bus Configurations 2.2.1 Single-Termination Multidrop 2.2.2 Double-Termination Multidrop 2.2.3 Data Distribution with Point-to-Point Links 2.2.4 Multipoint 2.2.5 Switch Matrix Mesh und Fahric Point-to-Point Bus Architectures 2.3 SerDes Devices 2.3.1 SerDes Device Fundamentals 2.3.2 SerDes at 5 Gbps 2.3.3 SerDes Multibit Signal Encoding 2.4 Electrical Interconnects vs. -
Zynq-7000 All Programmable Soc and 7 Series Devices Memory Interface Solutions User Guide (UG586) [Ref 2]
Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions (v2.3) DS176 June 24, 2015 Advance Product Specification Introduction • Strict: memory requests are processed in the order received The Xilinx® Zynq®-7000 All Programmable SoC and 7 series FPGAs memory interface solutions cores provide LogiCORE™ IP Facts Table high-performance connections to DDR3 and DDR2 Core Specifics SDRAMs, QDR II+ SRAM, RLDRAM II/RLDRAM 3, Supported Zynq®-7000All Programmable SoC, Virtex®-7(2), Kintex®-7(2), and LPDDR2 SDRAM. Device ® Family(1) Artix -7 Supported DDR3 Component and DIMM, DDR2 Component and DIMM, DDR3 and DDR2 SDRAMs Memory QDR II+, RLDRAM II, RLDRAM 3, and LPDDR2 SDRAM Components This section discusses the features, applications, and Resources See Table 1. functional description of Xilinx 7 series FPGAs memory interface solutions in DDR3 and DDR2 SDRAMs. These Provided with Core solutions are available with an optional AXI4 slave Documentation Product Specification User Guide interface. Design Files Verilog, VHDL (top-level files only) Example DDR3 SDRAM Features Design Verilog, VHDL (top-level files only) • Component support for interface widths up to 72 bits Test Bench Not Provided • Single and dual rank UDIMM, RDIMM, and Constraints XDC SODIMM support File • DDR3 (1.5V) and DDR3L (1.35V) Supported N/A • 1, 2, 4, and 8 Gb density device support S/W Driver • 8-bank support Tested Design Flows(3) • x8 and x16 device support Design Entry Vivado® Design Suite • 8:1 DQ:DQS ratio support Simulation For supported simulators, see the • Configurable data bus widths (multiples of 8, up to Xilinx Design Tools: Release Notes Guide.