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A CMOS, Self Calibrating, 100Mhz RC-Oscillator for ASIC Applications

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A CMOS, Self Calibrating, 100Mhz RC-Oscillator for ASIC Applications A CMOS, Self Calibrating, lOOMHz RC-Oscillator for ASIC Applications Timothy O'Shaughnessy American Microsystems, Inc. 2300 Buckskin Road Pocatello, Idaho 83201 USA Abstract The design of a high performance cell based CMOS rc-oscillator for ASIC applications is presented. The oscillator operates over a wide voltage range that includes 3.0 volt operation. The circuit features low operating current and low temperature sensitivity. The frequency accuracy is dominated only by the tolerances of the R. and C elements. Circuit theory, simulations COU12 and measured performance are presented. T Cl"' T 1. Introduction Fig. 2: Equivelent circuit of oscillator shown in fig. 1 Although rc-oscillators have some desirable features, Most rc-oscillators use the resistor element R, and the the limitations of these circuits often prevent usage capacitor element C, to establish the period of except in very limited applications. Some features of oscillation. By design the period of oscillation is merit include low cost, no inductors and the ability to proportional to the RC product. However, the package adjust the frequency. The traditional limitations of capacitance and the effective series resistance of the rc-oscillators include low operating frequency, a high output significantly alter this RC product. Likewise, any temperature sensitivity and a wide variation in delay through the ampiifin); stages increases the period frequency over process. These traditional limitations of oscillation. often restrict rc-oscillators to applications of low frequency and low precision signal sources, such as The performance of rc-oscillators is limited by the tone generators, alarms or flashing indicators. Even in intrinsic delays within the circuit structure, and by the such applications requiring only moderate values of effects of the parasitic circuit elements on the frequency frequency accuracy (1 to 10 percent), the more costly selective structure. The oscillator shown in fig.l [l] crystal oscillators traditionally replace the includes the intrinsic delays through amplifier stages, the rc-oscillators. parasitic input capacitance of the package and input stage, and the effective series resistance of the output INVl I NV2 stage. Fig. 2 provides a model of this circuit topology, including the nonideal elements. Table- 1 provides a summary of the errors when operating at selected frequencies. Most of these errors scale with frequency, which severely limits the usable applications of such circuits above 1 .OMHz. Fig. 1: Conventional CMOS RC oscillator. 0-7803-2707-1195$4.00 0 1995 IEEE 279 DlllDc 2. Circuit Description and Theory I I The rc-oscillator in fig. 3 samples its own period, and then compares the sample period to the RC product. The circuit generates a negative feedback signal that corrects for the variations in delay that result from FwY-CY changes in temperature, power supply voltage, or from process parameters. The circuit comprises a VCO, a binary counter, a "ramp and hold" circuit (R/H), a RC ic comparator and integrating charge pump. Because this circuit has no phase comparator, it is not a phase lock loop (PLL). This circuit uses no input reference signal, Fig. 3: Functional block diagram of self calibrating RC oscillator and as such it is not a frequency lock loop (FLL). The circuit operates by comparing two voltages. The VCO When capacitor element C is fabricated on chip, then produces a frequency that is divided by a binary counter the effects of package capacitance are eliminated. The using standard cell logic elements. Outputs from the smaller value of capacitance allows more reasonable binary counter operate the R/H circuit and integrating resistor values for R. However, process variations in charge pump. The FUH produces a current proportional dielectric thickness again increase the frequency to the reference voltage. The current is mirrored to the variance. The application of trim to reduce variance in capacitor C. After initialization the capacitor charges frequency increases the die cost. As temperature until the start of a hold interval. If the VCO frequency increases, mobility decreases [2], which increases the is low, the capacitor charges to a "hold" voltage that delay of any amplifier stages. As a consequence most exceeds the reference voltage. The comparator output rc-oscillators exhibit temperature sensitivity. These then activates the charge pump to increase input voltage traditional limitations of CMOS rc-oscillators are to the VCO. The frequency of the VCO increases. A greatly reduced using the circuit topology shown in high VCO frequency produces a low "hold" voltage. fig. 3. The comparator activates the charge pump to decrease the VCO input voltage. IN11 n DECODE PUMPF VDO P1B P11 N3 P6 p7 IL N2 P13 PI2 -cost -31-"xT CPunP vco - *'R x C NI NI3 -': I' NlY __ 280 I SI TABLE 1: Typical Errors of Conventional RC-Oscillators * .S8 Cosc=SOOpf, Rosc= YzfoscCosc 9.1 1.51 VALUE O.1MHz 0.SMHz 1.OMHz 5.OMHz 3.a delay 1 2.5ns 5E-4 2SE-3 SE-3 2.5E-2 2.51 1.) delay 2 2.511s 5E-4 2SE-3 SE-3 2SE-2 I .SI I .I Rout 1 xCin2 loops 2E-5 1E-4 2E-4 1E-3 SII.1)1 Rout2 XCOUQ loops 2E-5 1E-4 2E4 1E-3 I. 1.- .......*.........~.............................,......................................,........... ' Cinl/C,, 2E-2 2E-2 2E-2 2E-2 2E-2 Rout lmosc - 1E-3 SE-3 1E-2 5E-2 Rout2/Rosc - 1E-3 5E-3 1E-2 SE-2 Oscillator 2.3% 3.52% S.04% 17.2% Total 3.3% 4.52% 6.04% 18.2% NOTES: Total includes OS% tolarence for both ROSCand Cosc. WUsuRED: HORZ: i!O ns/div ZOO ns The circuit is ratio metric. The current chargng the capacitor C ( I ), the ramp rate (2),the resulting "hold" Fig. 5: Simulated and measured output waveform of RC oscillator voltage (3), and the oscillator frequency (4) are operating at 1OOMHz obtained from the following relationships: Vref The circuit structure has fea.tures that facilitate the high Iramp = m- (1) R performance. The analog signal processing of the R/H circuit, comparator and chairge pump occurs at the lower frequency of fosc/N. The low frequency provides Vref dVldt = m- adequate settling to occur and allows a very accurate RC compare of Vhold to Vref. Because the frequency is scaled by the binary countler, the capacitor C becomes Vref Tramp Vhold = m (3) large enough to be insensitive to charge injection and RC also to parasitic capacitances. Fig. 4 shows the rc-oscillator with transistor level schematics for the R/H circuit, comparator and chairge pump. Vref is the gate to mN source voltage of transistor NI. A CMOS inverter fosc = - (4) 4RC comprising MOS transistors N2 and P2 forms the comparator with an input threshold that is also matched Where: the gate to source voltage of transistor NI. This self Zrump = the current charging C. bias topology simplifies the comparator and eliminates the need for opamp circuitry. The circuit topology is = the current mirror ratio. m used for 2-pin, I-pin and for 0-pin applications. The 2 R = resistance to set frequency. pin RC oscillator uses both R and C as external C = capacitance to set frequency. frequency setting elements. The 1 pin rc-oscillator uses Vref = internal reference voltage. an external resistor R, and provides the option to trim out process variations in capacitance. The 0-pin Vhold = FUH hold voltage across C. rc-oscillator uses a polysilicon resistors array that is Trump = time of WH charging interval. trimmed to set the operating frequency. In this N = divide by ratio of binary counter. application, the circuit corrects for changes in delay fosc = VCO output frequency. resulting from temperature, power supply voltage, and MOS parameters. 28 1 3. Simulated and Measured Results RC-osc LOOP: ICS. Rmnx. cmnx. e5t. q.5~: vco 17-0 Cl. 199Il I .50 =. ................................................... Closed loop transient simulations of the rc-oscillator ,.660 =.'."...."""".I .......... ...., ............................ were performed using HSPICE version 9007d. ..................;,. ............... :.................... : Simulations indicate that the steady state output frequency equals the expected frequency of operation 1 within accuracy limits of the simulation. The closed ........................................ loop simulations also predict that the steady state VCO I .350 =.'. input dithers for each Vhold interval. The dither ...............; .............................. ...., > ...... magnitude on the VCO input and the corresponding ..................................... ......................... frequency modulation are established by the values of LI l.i?OF... charge pump current and the integrating capacitor. ............................................................................. The rc-oscillator was designed and evaluated using a the 2 pin topology fabricated with a 1 micron, N-well process. Oscillator frequency was measured over power supply voltage and temperature. Part to part frequency variation was measured using fixed values for R and C. 95* ............................................................ Table provides a summary of oscillator performance. 2 ,*loa 20. ou TABLE 2: Measured Electrical Performance Maximum Frequency: 103.0 MHz Fig. 7: Simulated closed loop transient response of charge pump Temperature Sensitivity: 57.1 ppm output (Cpump) with coarse dither. Voltage Sensitivity: 3.43E-3 1/V Minimum Supply Voltage: 2.70 Volts Maximum Supply Voltage: 6.00 Volts 4. Conclusions Frequency Linearity Error: 2.79E-3 Full Scale Chip Area: 1.25 sq. mm. "Self calibrating" rc-oscillator topologies have been evaluated. These structures provide improved performance over traditional rc-oscillators. Changes in delay resulting from temperature, supply voltage and MOS process parameters are corrected by comparing N samples of the oscillator period to the RC product. The circuit allows flexibility in selecting values of R and C to establish frequency, thereby reducing the sensitivity to parasitics. Applications for utilizing rc-oscillators of moderate precision or high frequency are now realizable. References (1) J. Millman and A. Crabel "Microelectronics", 2nd ed., McCraw-Hill, 1987, pp. 674-675 0.5 V/di. (2) S.
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