A 1.8 V 18.13 Mhz Inverter-Based On-Chip RC Oscillator with Flicker Noise Suppression Using Logic Transition Voltage Feedback

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Article A 1.8 V 18.13 MHz Inverter-Based On-Chip RC Oscillator with Flicker Noise Suppression Using Logic Transition Voltage Feedback

Junsoo Ko and Minjae Lee *

School of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Gwangju 61005, Korea; [email protected] * Correspondence: [email protected]; Tel.: +81-62-715-2205

Received: 21 October 2019; Accepted: 11 November 2019; Published: 15 November 2019

Abstract: An inverter-based on-chip resistor capacitor (RC) oscillator with logic transition voltage (LTV) tracking feedback for circuit delay compensation is presented. In order to achieve good frequency stability, the proposed technique considers the entire inverter chain as a comparator block and changes the LTV to control the oscillation frequency. Furthermore, the negative feedback structure also reduces low-frequency oﬀset phase noise. With a 1.8 V supply and at room temperature, the suggested oscillator operates at 18.13 MHz, consuming 245.7 µW. Compared to the free-running case, the proposed technique reduces phase noise by 7.7 dB and 5.45 dB at 100 Hz and 1 kHz, respectively. The measured phase noise values are 60.09 dBc/Hz at 1 kHz with a ﬁgure of merit − (FOM) of 151.35 dB/Hz, and 106.27 dBc/Hz at 100 KHz with an FOM of 157.53 dBc/Hz. The proposed − oscillator occupies 0.056 mm2 in a standard 0.18 µm CMOS process.

Keywords: RC on-chip oscillator; low phase noise; inverter-based; logic transition voltage tracking

1. Introduction As smart devices become more popular and the market demand for wearable devices grows, the need for low-power, on-chip resistor capacitor (RC) oscillators in a standard CMOS process is increasing, to address the cost and board area issues in external crystal oscillators. Owing to their strengths compared with ring oscillators (better frequency stability, control linearity, and wide tuning range), fully integrated relaxation oscillators are widely used as on-chip reference clocks, or as sensor front-end interfaces [1,2]. However, since the figure of merit (FOM) of a relaxation oscillator still cannot reach its theoretical limit [3], several studies are currently ongoing to overcome these circuit issues. Voltage-to-delay feedback and a switch-capacitor, swing-boosting (SCSB) circuit have been proposed to help improve frequency stability and phase noise characteristics [1], but an SCSB requires a large chip area due to its passive components. In order to reduce comparator noise effects, [2] suggests a differential swing-boosting method with a 162.1 dBc/Hz FOM. However, this scheme requires a high-speed comparator for output frequency stabilization [4]. Filtering the jitter noise in [3] yields a good FOM, while using a low-noise, milliwatt-level, power-hungry block. A feedback structure for frequency stabilization is also introduced in [5,6], but the power consumption in its analog feedback blocks limits its FOM. A low-frequency, inverter-chain-based RC oscillator scheme is presented in [7], achieving a high-voltage swing at its oscillating node. However, as this single-ended approach is vulnerable to circuit delay fluctuations, a regulated supply from a proportional-to-absolution-temperature (PTAT) reference is required, and this leads to a low operating frequency. In this article, an inverter-based RC oscillator with a logic transition voltage (LTV) tracking feedback method is proposed. The LTV of an inverter is defined where the input and output voltages

Electronics 2019, 8, 1353; doi:10.3390/electronics8111353 www.mdpi.com/journal/electronics Electronics 2019, 8, x FOR PEER REVIEW 2 of 11

In this article, an inverter-based RC oscillator with a logic transition voltage (LTV) tracking Electronics 2019, 8, 1353 2 of 11 feedback method is proposed. The LTV of an inverter is defined where the input and output voltages are the same. While maintaining a boosted voltage slope on the timing capacitor [7] for low-noise operationare the same. [2], we While replace maintaining the local regulated a boosted supply voltage scheme slope onwith the an timing LTV tracking capacitor structure, [7] for low-noise utilizing aoperation voltage averaging [2], we replace feedback the local(VAF) regulated concept supply[5] to obtain scheme a high-frequency with an LTV tracking oscillator structure, (>1 MHz). utilizing The structurea voltage of averaging the first-stage feedback inverter (VAF) is modified concept so [5] that to obtainthe feedback a high-frequency loop can control oscillator the LTV (>1 of MHz). this inverter.The structure As a ofresult, the first-stage the effect inverterof circuit is delay modified on the so thatoscillation the feedback frequency loop is can reduced. control The the LTVsuggested of this structureinverter. Asis not a result, only insensitive the effect of to circuit circuit delay variations, on the but oscillation also suppresses frequency low is reduced. frequency The offset suggested phase noisestructure and isflicker not only noise, insensitive due to its to negative circuit variations,feedback configuration. but also suppresses low frequency offset phase noiseThis and article flicker consists noise, due of six to itssections. negative Section feedback 2 demonstrates configuration. a conventional RC oscillator and the voltage-averagingThis article consists feedback of sixconcept. sections. In Section 23, demonstrates the circuit level a conventional implementation RC oscillator of the proposed and the oscillatorvoltage-averaging is described, feedback followed concept. by simulation In Section 3an, thed measurement circuit level implementation results illustrated of thein Section proposed 4. Finally,oscillator we is present described, our conclusions followed by in simulationSection 5. and measurement results illustrated in Section4. Finally, we present our conclusions in Section5. 2. RC Oscillator Architecture 2. RC Oscillator Architecture 2.1. Conventional RC Oscillator Structure 2.1. Conventional RC Oscillator Structure Figure 1 shows a generally known, conventional RC relaxation oscillator and its timing diagram Figure1 shows a generally known, conventional RC relaxation oscillator and its timing diagram [ 8]. [8]. For a logical high Φ 1 (and a low Φ 2), the timing capacitor C1 is charged by the constant current For a logical high Φ 1 (and a low Φ 2), the timing capacitor C is charged by the constant current source source IB, while C2 is grounded. When the voltage across C1 1 (V1 in Figure 1) reaches the threshold I , while C is grounded. When the voltage across C (V in Figure1) reaches the threshold level levelB 𝑽𝑹𝑬𝑭 ,2 the output of the comparator toggles, causing1 1 C1 to discharge and C2 to charge. VREF, the output of the comparator toggles, causing C to discharge and C to charge. Conversely, Conversely, when the voltage on C2 crosses 𝑽𝑹𝑬𝑭, C1 charges1 and C2 discharges.2 This cycle repeats to createwhen thethe voltageoscillating on Cfunction.2 crosses AsVREF shown,C1 charges in the timing and C2 diagramdischarges. in Figure This cycle 1, the repeats oscillator to create output the oscillating function. As shown in the timing diagram in Figure1, the oscillator output period consists period consists of 𝑻𝑶𝑺𝑪, as determined by the timing capacitors, plus the circuit delay. As this delay isof sensitiveTOSC, as to determined supply and by temperature the timing capacitors,variation, several plus the methods circuit delay.have been As this introduced delay is [1,5,8] sensitive to stabilizeto supply the and oscillation temperature frequency. variation, In addition, several in methods order to have achieve been low introduced noise, [2] [introduced1,5,8] to stabilize a method the ofoscillation increasing frequency. the charging/dischar In addition, inging order slope to achieveof the timing low noise, capacitor [2] introduced voltages using a method a swing of increasing booster circuit.the charging /discharging slope of the timing capacitor voltages using a swing booster circuit.

Figure 1. Conventional RC relaxation oscillator and its waveform. Figure 1. Conventional RC relaxation oscillator and its waveform. Figure2 shows the inverter-based RC oscillator scheme introduced in [ 7]. Biased by the PTAT reference current, a voltage regulator produces a local supply voltage (Local Supply in Figure2). The circuit delay through the inverter chains causes the almost constant over supply of voltage and temperature variations, because this regulated supply tracks for both NMOS and PMOS thresholds, leading to a stable oscillation frequency. An increased voltage swing across its timing capacitor also helps this structure to achieve low-noise performance. However, a lower local supply voltage limits this scheme to a low oscillating frequency (33 kHz in [7]).

Figure 2. Inverter-based RC oscillator with a regulated local supply [7].

Electronics 2019, 8, x FOR PEER REVIEW 2 of 11

In this article, an inverter-based RC oscillator with a logic transition voltage (LTV) tracking feedback method is proposed. The LTV of an inverter is defined where the input and output voltages are the same. While maintaining a boosted voltage slope on the timing capacitor [7] for low-noise operation [2], we replace the local regulated supply scheme with an LTV tracking structure, utilizing a voltage averaging feedback (VAF) concept [5] to obtain a high-frequency oscillator (>1 MHz). The structure of the first-stage inverter is modified so that the feedback loop can control the LTV of this inverter. As a result, the effect of circuit delay on the oscillation frequency is reduced. The suggested structure is not only insensitive to circuit variations, but also suppresses low frequency offset phase noise and flicker noise, due to its negative feedback configuration. This article consists of six sections. Section 2 demonstrates a conventional RC oscillator and the voltage-averaging feedback concept. In Section 3, the circuit level implementation of the proposed oscillator is described, followed by simulation and measurement results illustrated in Section 4. Finally, we present our conclusions in Section 5.

2. RC Oscillator Architecture

2.1. Conventional RC Oscillator Structure Figure 1 shows a generally known, conventional RC relaxation oscillator and its timing diagram [8]. For a logical high Φ 1 (and a low Φ 2), the timing capacitor C1 is charged by the constant current source IB, while C2 is grounded. When the voltage across C1 (V1 in Figure 1) reaches the threshold

level 𝑽𝑹𝑬𝑭 , the output of the comparator toggles, causing C1 to discharge and C2 to charge. Conversely, when the voltage on C2 crosses 𝑽𝑹𝑬𝑭, C1 charges and C2 discharges. This cycle repeats to create the oscillating function. As shown in the timing diagram in Figure 1, the oscillator output

period consists of 𝑻𝑶𝑺𝑪, as determined by the timing capacitors, plus the circuit delay. As this delay is sensitive to supply and temperature variation, several methods have been introduced [1,5,8] to stabilize the oscillation frequency. In addition, in order to achieve low noise, [2] introduced a method of increasing the charging/discharging slope of the timing capacitor voltages using a swing booster circuit.

Electronics 2019, 8, 1353 3 of 11 Figure 1. Conventional RC relaxation oscillator and its waveform.

Figure 2. Inverter-based RC oscillator with a regulated local supply [7].

2.2. Voltage Averaging FeedbackFigure (VAF)Concept 2. Inverter-based RC oscillator with a regulated local supply [7]. A voltage-averaging feedback (VAF) method has been proposed in order to achieve good frequency Electronics 2019 , 8, x FOR PEER REVIEW 3 of 11 stability in an on-chip CMOS relaxation oscillator [5]. The conceptual waveform is illustrated in FigureFigure3, where2 showsV THthe,COMP inverter-basedand VREF are RC theoscillator threshold scheme voltage introduced of the comparators in [7]. Biased and by the the reference PTAT referencevoltage current, of the VAF a voltage integrator, regulator respectively. produces In itsa local steady supply state, voltage the active (Local ﬁlter Supply in the VAFin Figure loop equalizes2). The circuitVREF delayand the through DC voltage the inverter of oscillation, chains creating causes thethe followingalmost constant relationship: over supply of voltage and temperature variations, because this regulated supply tracks for both NMOS and PMOS thresholds, Z TH leading to a stable oscillation frequency.1 An increased voltage swing across its timing capacitor also VOSC(t)dt = VREF (1) helps this structure to achieve low-noiseT Hperformance.0 However, a lower local supply voltage limits this scheme to a low oscillating frequency (33 kHz in [7]). Z TH VOSC(t)dt = VREF TH = Constant (2) 2.2. Voltage Averaging Feedback (VAF)0 Concept ×

V V VOSC,Increased

VOSC,Nominal VOSC,Nominal

VTH,COMP VTH,COMP VAF Effect

VREF VREF

VTH,COMP-β

δCOMP δCOMP+α δCOMP+α T T ～～ T H TH+α TH

(a) (b)

Figure 3. Conceptual waveforms of the on-chip relaxation oscillator with voltage averaging feedback [5]: Figure 3. Conceptual waveforms of the on-chip relaxation oscillator with voltage averaging feedback (a) nominal case; (b) in case of increased comparator delay with threshold voltage correction. [5]: (a) nominal case; (b) in case of increased comparator delay with threshold voltage correction. In Equation (2), during T , the areas of the V and V graphs are the same. If the comparator A voltage-averaging feedbackH (VAF) methodOSC has beenREF proposed in order to achieve good delay (δ s in Figure3) increases while V maintains its value, the graph area conﬁgured by frequency COMPstability in an on-chip CMOS relaxationTH,COMP oscillator [5]. The conceptual waveform is V increases. Since the area under the graph enclosed by V – the output of a resistive divider – is illustratedOSC in Figure 3, where 𝑉 and 𝑉 are the thresholdREF voltage of the comparators and constant and insensitive to delay, variation, the VAF loop lowers V to satisfy the integration the reference voltage of the VAF integrator, respectively. In its steadyTH ,COMPstate, the active filter in the relationship (Figure3b). In contrast, for a shorter δCOMP, the feedback structure increases VTH,COMP to VAF loop equalizes 𝑉 and the DC voltage of oscillation, creating the following relationship: adjust the VOSC curve. In summary, if the circuit delay1 is constant, an increase/decrease in VTH,COMP causes a 𝑉𝑡𝑑𝑡 =𝑉 (1) decrease/increase in the oscillation frequency.𝑇 Therefore, the VAFtechnique, by changing the comparator threshold voltage, reduces the eﬀect of circuit delay variation by controlling the frequency. 𝑉𝑡𝑑𝑡 =𝑉 ×𝑇 =Constant (2)

In Equation (2), during 𝑇 , the areas of the 𝑉 and 𝑉 graphs are the same. If the comparator delay (𝛿𝑠 in Figure 3) increases while 𝑉, maintains its value, the graph area configured by 𝑉 increases. Since the area under the graph enclosed by 𝑉 – the output of a resistive divider – is constant and insensitive to delay variation, the VAF loop lowers 𝑉, to satisfy the integration relationship (Figure 3b). In contrast, for a shorter 𝛿, the feedback structure increases 𝑉, to adjust the 𝑉 curve. In summary, if the circuit delay is constant, an increase/decrease in 𝑉, causes a decrease/increase in the oscillation frequency. Therefore, the VAF technique, by changing the comparator threshold voltage, reduces the effect of circuit delay variation by controlling the frequency.

3. Circuit Level Implementation

Electronics 2019, 8, 1353 4 of 11

3. Circuit Level Implementation

3.1. Oscillating Mechanism of an Inverter-Based RC Oscillator A simple example of the structure and waveform of an inverter-based RC oscillator is shown in Figure4. In practice, the gain of the inversion stages ( INV1 and INV2 in Figure4) should be large enough to allow for oscillation, and the proposed oscillator uses multiple inverters to allow for high gain [7]. When the VOSC, VA, and VB nodes are, respectively, high, low, and high, VOSC gradually decreases as ROSC discharges COSC. When VOSC equals the LTV of INV1, where the input and output voltages are the same, VA and VB change to logical high and low states, respectively. Since the charge on the capacitor should be the same, the voltage change at the VB node lowers the VOSC equally, making V equal to LTV VDD. Next, since the V node voltage decreases while V stays in LOW INV1 − OSC A the high state, COSC is charged through ROSC, and the VOSC node voltage increases. Similarly, when the charging VOSC passes the LTVINV1 level, the VOSC node voltage rises to VHIGH = LTVINV1 + VDD, dueElectronics to the logic 2019, changes8, x FOR PEER in the REVIEW following inverters. The timing diagram in Figure4 shows the charge4 of 11 and discharge cycles of the VOSC node, where td1 and td2 are the circuit delays of the inverter chain. 3.1. Oscillating Mechanism of an Inverter-Based RC r

VOSC VHIGH

VA VB INV1 INV2 VDD td1 LTVINV1 td2 GND ROSC COSC VOSC VLOW t TTOT=TOSC+td1+td2

Figure 4. Inverter-based RC oscillator and its waveform. A simple example of the structure and waveform of an inverter-based RC oscillator is shown in The discharge curve of VOSC is represented by the following equation: Figure 4. In practice, the gain of the inversion stages (INV1 and INV2 in Figure 4) should be large t enough to allow for oscillation, and the proposed oscillator usesR multipleC inverters to allow for high VOSC,discharing(t) = (LTVINV1 + VDD) e− OSC OSC (3) gain [7]. When the 𝑽𝑶𝑺𝑪, 𝑽𝑨, and 𝑽𝑩 nodes are, respectively,· high, low, and high, 𝑽𝑶𝑺𝑪 gradually decreases as 𝑹𝑶𝑺𝑪 discharges 𝑪𝑶𝑺𝑪. When 𝑽𝑶𝑺𝑪 equals the LTV of INV1, where the input and output The charging equation of VOSC is: voltages are the same, 𝑽𝑨 and 𝑽𝑩 change to logical high and low states, respectively. Since the t charge on the capacitor should be the same, the voltage changeR C at the 𝑽𝑩 node lowers the 𝑽𝑶𝑺𝑪 VOSC,charing(t) = (LTVINV1 2 VDD) e− OSC OSC + VDD. (4) equally, making 𝑽𝑳𝑶𝑾 equal to 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 − 𝑽𝑫𝑫− . Next,× since· the 𝑽𝑶𝑺𝑪 node voltage decreases while 𝑽𝑨Therefore, stays in the ignoring high state, the circuit 𝑪𝑶𝑺𝑪 is delay, charged the idealthrough period 𝑹𝑶𝑺𝑪 of, and the inverter-basedthe 𝑽𝑶𝑺𝑪 node RCvoltage oscillator increases. is calculatedSimilarly, as being:when the charging 𝑽𝑶𝑺𝑪 passes the 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 level, the 𝑽𝑶𝑺𝑪 node voltage rises to 𝑽𝑯𝑰𝑮𝑯 =𝑳𝑻𝑽𝑰𝑵𝑽𝟏 + 𝑽𝑫𝑫, due to the logic changes in the following inverters. The timing diagram in Figure 4 showsIdeal Periodthe charge(TOSC and) discharge cycles of the 𝑽𝑶𝑺𝑪 node, where td1 and td2 are the circuit delays of the inverter chain. LTVINV1+VDD LTVINV1 2VDD = ROSCCOSC ln + ROSCCOSC ln − The discharge curve of 𝑽 is representedLTVINV by1 the following equation:LTVINV 1 VDD (5) 𝑶𝑺𝑪 − (LTVINV1+VDD)(LTVINV1 2VDD) 𝒕 = ROSCCOSC ln − . (LTVINV1)( LTVINV1 VDD) 𝑹𝑶𝑺𝑪𝑪𝑶𝑺𝑪 (3) 𝑽𝑶𝑺𝑪,𝒅𝒊𝒔𝒄𝒉𝒂𝒓𝒊𝒏𝒈𝒕 = 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 + 𝑽−𝑫𝑫 ∙𝒆

If LTVTheINV charging1 is equal equation to half of of 𝑽V𝑶𝑺𝑪DD ,is: the ideal oscillation period TOSC is ROSCCOSC ln(9), and the ideal duty cycle is 50% [7]. 𝒕 𝑹𝑶𝑺𝑪𝑪𝑶𝑺𝑪 (4) Taking circuit delay into𝑽𝑶𝑺𝑪,𝒄𝒉𝒂𝒓𝒊𝒏𝒈 consideration,𝒕 = 𝑳𝑻𝑽 the practical𝑰𝑵𝑽𝟏 −𝟐× period 𝑫𝑫𝑽 of∙𝒆 the oscillator+ 𝑽𝑫𝑫 is as. follows: Therefore, ignoring the circuit delay, the idealX period of the inverter-based RC oscillator is T = T + t (6) calculated as being: TOT OSC d

𝑰𝒅𝒆𝒂𝒍 𝑷𝒆𝒓𝒊𝒐𝒅𝑻𝑶𝑺𝑪 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 +𝑽𝑫𝑫 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 −𝟐𝑽𝑫𝑫 =𝑹𝑶𝑺𝑪𝑪𝑶𝑺𝑪 𝒍𝒏 + 𝑹𝑶𝑺𝑪𝑪𝑶𝑺𝑪 𝒍𝒏 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 −𝑽𝑫𝑫 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 + 𝑽𝑫𝑫𝑳𝑻𝑽𝑰𝑵𝑽𝟏 −𝟐𝑽𝑫𝑫 =𝑹𝑶𝑺𝑪𝑪𝑶𝑺𝑪 𝒍𝒏 . (5) 𝑳𝑻𝑽𝑰𝑵𝑽𝟏𝑳𝑻𝑽𝑰𝑵𝑽𝟏 −𝑽𝑫𝑫

If 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 is equal to half of 𝑽𝑫𝑫, the ideal oscillation period 𝑻𝑶𝑺𝑪 is 𝑹𝑶𝑺𝑪𝑪𝑶𝑺𝑪 𝒍𝒏𝟗, and the ideal duty cycle is 50% [7]. Taking circuit delay into consideration, the practical period of the oscillator is as follows:

𝑻𝑻𝑶𝑻 =𝑻𝑶𝑺𝑪 +𝒕𝒅 (6)

3.2. Architecture of Proposed Oscillator Electronics 2019, 8, 1353 5 of 11

3.2. Architecture of Proposed Oscillator Figure5 shows the structure of the proposed inverter-based, on-chip RC oscillator. The inverter chain implemented is as small as possible to ensure low power operation. The second to sixth inverters have a standard structure, but the first-stage inverter (INV1 in Figure5) has been reconfigured to control its LTV. The VREF from the resistive divider and VOSC are inputs to the LTV tracking feedback, and its output—VCONT—controls LTVINV1. Charging and discharging at the VOSC node causes an Electronics 2019, 8, x FOR PEER REVIEW 5 of 11 oscillation due to the inverter logic switching, so the entire inverter chain can be seen to function as a comparator. INV1 is the most sensitive to noise and circuit fluctuations, as the slew rate at its input (VOSC) is slower than that of the other nodes. Also, transistor noise in INV1 has a significant effect on circuit delay variation. Thus, because of this sensitivity, INV1 is considered to be the main comparator and its LTV is regarded as the reference voltage for comparison. Electronics 2019, 8, x FOR PEER REVIEW 5 of 11

Figure 5. Proposed inverter-based on-chip RC oscillator.

Figure 5 shows the structure of the proposed inverter-based, on-chip RC oscillator. The inverter chain implemented is as small as possible to ensure low power operation. The second to sixth inverters have a standard structure, but the first-stage inverter (INV1 in Figure 5) has been reconfigured to control its LTV. The 𝑽𝑹𝑬𝑭 from the resistive divider and 𝑽𝑶𝑺𝑪 are inputs to the LTV Figure 5. Proposed inverter-based on-chip RC oscillator. tracking feedback, andFigure its output 5. Proposed—𝑽𝑪𝑶𝑵𝑻 inverter-based—controls 𝑳𝑻𝑽 on-chip𝑰𝑵𝑽𝟏. Charging RC oscillator. and discharging at the 𝑽𝑶𝑺𝑪 node causes an oscillation due to the inverter logic switching, so the entire inverter chain can be seen Figure 5 shows the structure of the proposed inverter-based, on-chip RC oscillator. The inverter Fromto function Equation as a comparator. (5), the operating INV1 is frequencythe most sensitive of the inverter-basedto noise and circuit RC fluctuations, oscillator without as the slew circuit chain implemented is as small as possible to ensure low power operation. The second to sixth delayrate is a functionat its input of (LTV𝑽 )INV is 1slower. Figure than6 illustrates that of the FotherOSC (nodes.= 1/ TAlso,OSC) transistor of the oscillator noise in asINV1 a function has a of inverters have a standard𝑶𝑺𝑪 structure, but the first-stage inverter (INV1 in Figure 5) has been LTVINVsignificant1 with V effectDD = on1.8 circuit V, ROSC delay= 17 variation. kΩ, and Thus,COSC because= 1.4 pF. of thisFOSC sensitivity,is an inverted INV1 is U-shaped considered curve to be with reconfigured to control its LTV. The 𝑽𝑹𝑬𝑭 from the resistive divider and 𝑽𝑶𝑺𝑪 are inputs to the LTV a maximumthe main of comparator 19.123 MHz and when its LTV INV1 is regarded LTV is 900as the mV, reference which voltage is half offorV comparison.DD. tracking feedback, and its output—𝑽𝑪𝑶𝑵𝑻—controls 𝑳𝑻𝑽𝑰𝑵𝑽𝟏. Charging and discharging at the 𝑽𝑶𝑺𝑪 node causes an oscillation due to the inverter logic switching, so the entire inverter chain can be seen to function as a comparator. INV1 is the most sensitive to noise and circuit fluctuations, as the slew

rate at its input (𝑽𝑶𝑺𝑪) is slower than that of the other nodes. Also, transistor noise in INV1 has a significant effect on circuit delay variation. Thus, because of this sensitivity, INV1 is considered to be the main comparator and its LTV is regarded as the reference voltage for comparison.

FigureFigure 6. Oscillation 6. Oscillation frequency frequency of theof the proposed proposed inverter-based inverter-based RC RC oscillatoroscillator with respect respect to to the the LTV LTV of the ﬁrst-stageof the first-stage inverter inverter when when circuit circuit delay delay is ignored. is ignored.

In a practicalFrom Equation oscillator, (5), the theoperating frequency frequency contains of the a inverter-based circuit delay RC component oscillator without as expressed circuit in delay is a function of 𝑳𝑻𝑽 . Figure 6 illustrates 𝑭 ( = 𝟏/𝑻 ) of the oscillator as a function of Equation (6), and delay variations𝑰𝑵𝑽𝟏 degrade the oscillator’s𝑶𝑺𝑪 stability.𝑶𝑺𝑪 Thus, in order to reduce the 𝑳𝑻𝑽 with 𝑽 = 1.8 V, 𝑹 = 17 kΩ, and 𝑪 = 1.4 pF. 𝑭 is an inverted U-shaped curve inﬂuenceFigure𝑰𝑵𝑽𝟏 of these 6. Oscillation variations,𝑫𝑫 frequency a method𝑶𝑺𝑪 of the is proposed required inverter to𝑶𝑺𝑪 detect-based delay RC oscillator𝑶𝑺𝑪 changes with and respect to maintain to the LTV a constant 𝑽 frequency.withof a As themaximum shownfirst-stage of in inverter 19.123 Figure MHzwhen3, the whencircuit VAF INV1delay scheme isLTV ignored. is senses 900 mV, delay which variation is half of by𝑫𝑫 comparing. graph areas, In a practical oscillator, the frequency contains a circuit delay component as expressed in and the reference voltage of the comparator is changed to maintain a constant frequency. EquationFrom (6),Equation and delay (5), the variations operating degrade frequency the ofoscill theator’s inverter-based stability. Thus,RC osci inllator order without to reduce circuit the The suggested LTV tracking technique utilizes the VAF concept for LTVINV1 control to reduce delayinfluence is a function of these variations,of 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 a. Figuremethod 6 isillustrates required 𝑭to𝑶𝑺𝑪 detect ( = delay𝟏/𝑻𝑶𝑺𝑪 changes) of the and oscillator to maintain as a function a constant of the eﬀfrequency.ects of circuit As shown delay in variations. Figure 3, the The VAF proposed scheme senses oscillator delay variation works by by comparing comparing graph the graph areas, area 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 with 𝑽𝑫𝑫 = 1.8 V, 𝑹𝑶𝑺𝑪 = 17 kΩ, and 𝑪𝑶𝑺𝑪 = 1.4 pF. 𝑭𝑶𝑺𝑪 is an inverted U-shaped curve and the reference voltage of the comparator is changed to maintain a constant frequency. with a maximum of 19.123 MHz when INV1 LTV is 900 mV, which is half of 𝑽𝑫𝑫. The suggested LTV tracking technique utilizes the VAF concept for 𝑳𝑻𝑽 control to reduce In a practical oscillator, the frequency contains a circuit delay component𝑰𝑵𝑽𝟏 as expressed in the effects of circuit delay variations. The proposed oscillator works by comparing the graph area Equation (6), and delay variations degrade the oscillator’s stability. Thus, in order to reduce the configured by 𝑽 and 𝑽 , to estimate the delay variation. For example, if the circuit delay influence of these variations,𝑶𝑺𝑪 a𝑹𝑬𝑭 method is required to detect delay changes and to maintain a constant frequency. As shown in Figure 3, the VAF scheme senses delay variation by comparing graph areas, and the reference voltage of the comparator is changed to maintain a constant frequency.

The suggested LTV tracking technique utilizes the VAF concept for 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 control to reduce the effects of circuit delay variations. The proposed oscillator works by comparing the graph area

configured by 𝑽𝑶𝑺𝑪 and 𝑽𝑹𝑬𝑭 , to estimate the delay variation. For example, if the circuit delay

Electronics 2019, 8, 1353 6 of 11

conﬁgured by VOSC and VREF, to estimate the delay variation. For example, if the circuit delay increases, the VOSC graph area grows while the area under VREF is unchanged. In addition, as demonstrated in Equation (6), this increased delay causes a decrease in oscillation frequency. In order to achieve good frequency stability, an operating frequency compensation mechanism that responds to circuit delay variations is required. Figure6 shows that the oscillation frequency of an inverter-based RC oscillator is determined by the LTVINV1, unless the passive components (ROSC and COSC) change. Thus, the proposed LTV tracking scheme allows for the oscillator to have a constant operating frequency by adjusting the LTVINV1 from VCONT (the feedback loop output). If the nominal value of LTVINV1 is 900 mV (half of the 1.8 V supply), the oscillation frequency variation for the LTV change is close to zero, as indicated by the horizontal tangent line in Figure6. Electronics 2019, 8, x FOR PEER REVIEW 6 of 11 Furthermore, increasing or decreasing the LTV to around 900 mV only lowers the oscillator frequency relativeincreases, to the maximum the 𝑉 graph value, area so thegrows oscillator while the cannot area under cope with𝑉 longeris unchanged. circuit delayIn addition, situations. as Therefore,demonstrated because thein Equation integrator (6), this of the increased LTV tracking delay causes loop a decrease makes thein oscillation DC voltage frequency. of VOSC equal to VREF, the proposedIn order to scheme achieve raises good thefrequencyLTVINV stability,1 by setting an operating the resistive frequency divider compensation output to 1.1V,mechanism in order to controlthat the responds oscillator to circuit frequency delay againstvariations any is required. variations Figure of LTV 6 showsINV1. that the oscillation frequency of Inan this inverter-based approach, the RC oscillator oscillator cannot is determined sustain by a 50% the duty𝐿𝑇𝑉 cycle,, unless but the the passive sensitivity components of the operating (𝑅 and 𝐶 ) change. Thus, the proposed LTV tracking scheme allows for the oscillator to have a frequency to LTVINV1 is increased (see the increased tangent line slope in Figure6). When maintaining constant operating frequency by adjusting the 𝐿𝑇𝑉 from 𝑉 (the feedback loop output). negative feedback, the increase/decrease of the LTV relative to 1.1 V causes frequency decrease/increase. If the nominal value of 𝐿𝑇𝑉 is 900 mV (half of the 1.8 V supply), the oscillation frequency Considering frequency controllability alone, LTV’s larger than 1.1V can be used, but this will increase variation for the LTV change is close to zero, as indicated by the horizontal tangent line in Figure 6. power consumption.Furthermore, increasing The proposed or decreasing structure the enablesLTV to around high-frequency 900 mV only operation lowers the by oscillator connecting frequency the chip supplyrelative to the inverterto the maximum chain, rather value, than so the to oscillator the regulated cannot supply, cope with and longer the large circuit voltage delay swingsituations. at the

VOSC nodeTherefore, reduces because the comparator the integrator noise of the of theLTV inverter tracking chainloop makes [2]. the DC voltage of 𝑉 equal to 𝑉, the proposed scheme raises the 𝐿𝑇𝑉 by setting the resistive divider output to 1.1V , in order 3.3. Theto First-Stage control the Inverter oscillator frequency against any variations of 𝐿𝑇𝑉. In a basicIn this inverter approach, structure the oscillator consisting cannot of one sustain NMOS a transistor50% duty andcycle, one but PMOS the sensitivity transistor, of it the is not operating frequency to 𝐿𝑇𝑉 is increased (see the increased tangent line slope in Figure 6). When easy to change the LTV of the inverters, except for the supply voltage control. Therefore, a structural maintaining negative feedback, the increase/decrease of the LTV relative to 1.1 V causes frequency changedecrease/increase. of the inverter is Considering required to frequency control LTV controllabiliINV1. Figurety alone,7a shows LTV’s the larger proposed than 1.1V INV1 can schematicbe used, for LTVbut control, this will where increaseVCONT powerstands consumption. for the output The proposed of the feedbackstructure enables loop. Since high-frequency the input operation DC voltage from LTVby connecting tracking feedback the chip supply (VREF to) is the 1.1 inverter V for oscillationchain, rather frequency than to the regulated control, the supply,VCONT andvalue the large is set so that voltageLTVINV swing1 becomes at the 1.1𝑉 V. node Transistors reduces the PM2 comparator and NM2 noise are of stacked the inverter in the chain output [2]. path, and the substrate of NM2 is connected to VCONT. PM3 and NM3, with VCONT as inputs, are connected to the main inverter3.3. The path,First-Stage forming Inverter an auxiliary path through a resistor connected to each source node.

(a) (b)

Figure 7. (a) Schematic of the first-stage inverter (INV1); (b) Simulated 𝐿𝑇𝑉 with respect to a Figure 7. (a) Schematic of the ﬁrst-stage inverter (INV1); (b) Simulated LTVINV1 with respect to a 𝑉 range of 0.9 V to 1.4 V. VCONT range of 0.9 V to 1.4 V.

ChangingIn a thebasic supply inverter voltage structure to adjustconsisting the of inverter’s one NMOS LTV transistor further and lowers one thePMOS frequency transistor, stability it is not easy to change the LTV of the inverters, except for the supply voltage control. Therefore, a of the inverter chain-based RC oscillator. Also, to maintain the supply voltage, a large chip area is structural change of the inverter is required to control 𝐿𝑇𝑉. Figure 7a shows the proposed INV1 schematic for LTV control, where 𝑉 stands for the output of the feedback loop. Since the input DC voltage from LTV tracking feedback (𝑉) is 1.1 V for oscillation frequency control, the 𝑉 value is set so that 𝐿𝑇𝑉 becomes 1.1 V. Transistors PM2 and NM2 are stacked in the output path, and the substrate of NM2 is connected to 𝑉. PM3 and NM3, with 𝑉 as inputs, are connected to the main inverter path, forming an auxiliary path through a resistor connected to each source node. Changing the supply voltage to adjust the inverter’s LTV further lowers the frequency stability of the inverter chain-based RC oscillator. Also, to maintain the supply voltage, a large chip area is required to change the LTV, using the driving current from multiple connected transistors with

Electronics 2019, 8, 1353 7 of 11

Electronics 2019, 8, x FOR PEER REVIEW 7 of 11 required to change the LTV, using the driving current from multiple connected transistors with switches. However, the proposed method controls LTV relative to 1.1 V,by controlling the pull-down strength drive capability of the NMOS pull-down pathINV [9],1 resulting in a higher 𝑳𝑻𝑽𝑰𝑵𝑽𝟏. Thus, the oscillation withfrequencyVCONT decreaseswhile using according a simple to structure. Equation An (5), increased as illustratedVCONT reducesin Figure the 6. current In addition, drive capability because ofa the NMOS pull-down path [9], resulting in a higher LTV . Thus, the oscillation frequency decreases decreased 𝑽𝑪𝑶𝑵𝑻 leads to a lower 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 , anINV 1increase/decrease in 𝑽𝑪𝑶𝑵𝑻 causes a decrease/increaseaccording to Equation in oscillator (5), as illustrated frequency. in Figure6. In addition, because a decreased VCONT leads to a lower LTV , an increase/decrease in V causes a decrease/increase in oscillator frequency. FigureINV 7b1 shows the change in 𝑳𝑻𝑽CONT𝑰𝑵𝑽𝟏 when the control voltage 𝑽𝑪𝑶𝑵𝑻 varies from 0.9 V to Figure7b shows the change in LTV when the control voltage V varies from 0.9 V to 1.4 V. Since the nominal voltage of 𝑳𝑻𝑽𝑰𝑵𝑽𝟏INV 1 is set to 1.1 V, the positive 𝑽𝑪𝑶𝑵𝑻CONT turns on the PN diode 1.4 V. Since the nominal voltage of LTV is set to 1.1 V, the positive V turns on the PN diode between the substrate node and the sourceINV1 node of NM2 in Figure 7a. TheCONT increase in 𝑽𝑪𝑶𝑵𝑻 causes thebetween drain-source the substrate current node of NM2 and to the be source reduced, node by of increasing NM2 in Figure its substrate-source7a. The increase diode in VcurrentCONT causes while the drain-source current of NM2 to be reduced, by increasing its substrate-source diode current while the drain-source current of NM1 is constant. In this situation, 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 increases because the reduced the drain-source current of NM1 is constant. In this situation, LTV increases because the reduced 𝑰𝑫𝑺,𝑵𝑴𝟐 weakens the inverter pull-down strength. Consequently,INV 𝑳𝑻𝑽1 𝑰𝑵𝑽𝟏 is controlled by 𝑽𝑪𝑶𝑵𝑻 whichIDS,NM 2determinesweakens thethe invertercurrent capability. pull-down Furthermore, strength. Consequently, the auxiliary pathLTVINV consisting1 is controlled of PM3 byandV NM3CONT whichincreases determines the sensitivity the current of INV1 capability. to the control Furthermore, voltage. the This auxiliary is because path the consisting additional of PM3 structure and NM3 not onlyincreases helps the the sensitivity LTV tracking of INV1 loop to thesettle control the output, voltage. but This also is becauseadjusts the the amount additional of structureINV1 pull-down not only current.helps the LTV tracking loop settle the output, but also adjusts the amount of INV1 pull-down current. In [5], [5], the authors introduced an on-chip relaxati relaxationon oscillator flicker flicker no noiseise suppression suppression method, method, by modeling the relaxation oscillator as a voltag voltage-controllede-controlled oscillator (VCO) and applying the the VAF VAF technique. Since Since the the VAF VAF l loopoop creates a high-pass high-pass filter, filter, closed-loop transfer transfer function function for for phase phase noise, noise, the low-frequency ooffsetffset phasephase noisenoise isis reduced.reduced. The suggested inverter-based RC os oscillatorcillator is also a VCO, the frequency of which is controlled by LTVINV1INV1, ,and and we we use use the the VAF VAF concept for the negativenegative feedbackfeedback structure.structure. The The proposed proposed LTV LTV tracking feedbackfeedback decreasesdecreases flicker flicker noise noise in in the the oscillator, oscillator, because because the the noise noise transfer transfer function function in [ 5in] can[5] canbe applied. be applied. Figure Figure8 shows 8 shows the noise the noise transfer transfer model, model, especially especially for the for oscillator the oscillator phase phase noise. noise.

Figure 8. NoiseNoise transfer transfer model model of of the proposed oscillator.

The phase noise of the VCO part is formulated as follows: 𝒔𝑪 𝑹 𝑨 +𝟏 sC 𝑰𝑵𝑻𝑮R 𝑰𝑵𝑻𝑮A 𝟎+ 1 Φ 𝜱𝑶𝑼𝑻== INTG INTG 0 Φ𝜱𝒏 (7) OUT 𝑨𝟎𝒔𝑪𝑰𝑵𝑻𝑮𝑹𝑰𝑵𝑻𝑮 +𝜸𝑲𝑨𝑲𝑽𝑪𝑶 n A0(sCINTGRINTG + γKAKVCO) Unlike the phase noise transfer function in [5], Equation (7) requires a voltage scaling factor 𝑲𝑨. Unlike the phase noise transfer function in [5], Equation (7) requires a voltage scaling factor This is because multiplying the output of the integrator 𝑽𝑪𝑶𝑵𝑻 by 𝑲𝑨 produces 𝑳𝑻𝑽𝑰𝑵𝑽𝟏, which K . This is because multiplying the output of the integrator V by K produces LTV , controlsA the frequency of the oscillator. Equation (7)—with a high-pass,CONT closed-loopA transfer functionINV1 which controls the frequency of the oscillator. Equation (7)—with a high-pass, closed-loop transfer characteristic—has zero and pole at fz and fp, which are described in the following equations: function characteristic—has zero and pole at fz and fp, which are described in the following equations: 𝟏 𝒇𝒛 = (8) 𝟐𝝅𝑪𝑰𝑵𝑻𝑮1 𝑹𝑰𝑵𝑻𝑮𝑨𝟎 fz = (8) 2πCINTGRINTGA0 𝜸𝑲𝑨𝑲𝑽𝑪𝑶 𝒇𝒑 = (9) 𝟐𝝅𝑪γKA𝑰𝑵𝑻𝑮KVCO𝑹𝑰𝑵𝑻𝑮 fp = (9) 2πCINTGRINTG Adjusting 𝑽𝑪𝑶𝑵𝑻 from 1 V to 1.4 V changes the 𝑳𝑻𝑽𝑰𝑵𝑽𝟏 from 1.183 V to 1.02 V, resulting in a 𝑲𝑨 value of 0.41 (absolute value without polarity). Under this condition, the calculated 𝑲𝑽𝑪𝑶 is 41.8 6 × 10 rad/sec∙V, and the scaling factor γ is 0.38 V/MHz. Since 𝑹𝑰𝑵𝑻𝑮 and 𝑪𝑰𝑵𝑻𝑮 are 1.26 MΩ, and

Electronics 2019, 8, 1353 8 of 11

Adjusting VCONT from 1 V to 1.4 V changes the LTVINV1 from 1.183 V to 1.02 V, resulting in a KA value of 0.41 (absolute value without polarity). Under this condition, the calculated K is 41.8 106 VCO × rad/sec V, and the scaling factor γ is 0.38 V/MHz. Since R and C are 1.26 MΩ, and 1.93 pF, · INTG INTG respectively, the simulated fp is 652.864 kHz, which is large enough to suppress the low frequency oﬀset phase noise.

4. Simulation and Measurement Results The proposed LTV tracking, inverter-based RC oscillator was fabricated in a 0.18 µm standard CMOSElectronics process, 2019, 8, xand FOR PEER Figure REVIEW9a shows the layout of the suggested oscillator. Figure9b illustrates8 of 11 the chip die photo, the active area of which is 310 µm 180 µm. The passive components that 6 × make× 10 up rad/sec the reference∙V, and the voltage scaling divider factor and γ is the 0.38 VAF V/MHz. integrating Sincenode, 𝑅 especially and 𝐶 the are resistors, 1.26 MΩ cover, and a1.93 large pF, area. respectively, The suggested the simulated design, with𝑓 is a652.864 nominal kHz, 1.8 which V power is large supply, enough oscillates to suppress at 18.13 the MHz, low consumingfrequency offset 245.7 phaseµW. Figure noise.9 c shows the simulated power distribution ratio of each block in the proposed oscillator. The highest power consumers are ROSC and the ﬁrst-stage inverter due to the charge4. Simulation/discharge and operation Measurement and LTV Results control

(a) (b) (c)

FigureFigure 9. 9.( a(a)) Layout Layout of of the the suggested suggested oscillator; oscillator; ( b(b)) chip chip photomicrograph photomicrograph of of the the proposed proposed oscillator; oscillator; (c()c) simulated simulated power power consumption consumption pie pie chart. chart.

InThe the proposed INV1 schematic LTV tracking, of Figure inverter-based8a, the input RCVCONT oscillatorof PM3 was and fabricated NM3 is disconnected,in a 0.18 μm standard and the substrateCMOS process, of NM2 and is tied Figure to ground 9a shows in order the tolayout implement of the asuggested feedback-free oscillator. structure. Figure Figure 9b illustrates10 illustrates the thechip simulated die photo, phase the active noise characteristics.area of which is The 310 technique μm × 180 proposed μm. The in passive the simulation components reduces that oscillator make up phasethe reference noise by voltage 4 dBc/ dividerHz and and 2 dBc the/Hz VAF at integrating low- and high-frequency node, especially o ffthesets, resistors, respectively. cover a Figurelarge area. 11 showsThe suggested the measured design, phase with noise a nominal characteristics 1.8 V power when su therepply, isoscillates (a) no feedback, at 18.13 MHz, and (b) consuming the suggested 245.7 methodμW. Figure is applied. 9c shows As the a simulated result of thepower negative distribution feedback ratio that of each constitutes block inthe the LTVproposed tracking oscillator. loop, theThe proposed highest schemepower reducesconsumers phase are noise 𝑅 at and low-frequency the first-stage offsets. inverter The phase due noiseto the at charge/discharge both the 100 Hz andoperation the 1 kHzand frequencyLTV control off sets is decreased by 7.7 dBc/Hz (from –44.72 dBc/Hz to 52.42 dBc/Hz) and 5.45 dBc/Hz (from –54.64 dBc/Hz to –60.09 dBc/Hz), respectively. In the feedback-free structure, circuit noise produces some unwanted tones near 100 kHz, degrading the phase noise characteristics, while the proposed LTV tracking technique filters these tones out but still produces the 400 kHz tones. Compared with the simulation, the overall phase noise level is increased in the measurement. However, the amount of noise suppression remains similar.

Figure 10. Simulated phase noise of the proposed oscillator. The blue line and red line represent without the feedback and with the feedback, respectively.

(a) (b)

Electronics 2019, 8, x FOR PEER REVIEW 8 of 11

6 × 10 rad/sec∙V, and the scaling factor γ is 0.38 V/MHz. Since 𝑅 and 𝐶 are 1.26 MΩ, and

1.93 pF, respectively, the simulated 𝑓 is 652.864 kHz, which is large enough to suppress the low frequency offset phase noise.

4. Simulation and Measurement Results Electronics 2019, 8, x FOR PEER REVIEW 8 of 11

1.93 pF, respectively, the simulated 𝒇𝒑 is 652.864 kHz, which is large enough to suppress the low frequency offset phase noise.

4. Simulation and Measurement Results

(a) (b) (c)

Figure 9. (a) Layout of the suggested oscillator; (b) chip photomicrograph of the proposed oscillator; (Figurec) simulated 9. (a) Layoutpower consumptionof the suggested pie oscillator;chart. (b) chip photomicrograph of the proposed oscillator; (c) simulated power consumption pie chart. The proposed LTV tracking, inverter-based RC oscillator was fabricated in a 0.18 μm standard CMOSThe process, proposed and LTV Figure tracking, 9a shows inverter-based the layout of RC the oscillator suggested was oscillator. fabricated Figure in a 0.18 9b illustrates μm standard the chipCMOS die process, photo, the and active Figure area 9a of shows which the is 310layout μm of × the 180 suggested μm. The passiveoscillator. components Figure 9b thatillustrates make upthe thechip reference die photo, voltage the active divider area and of thewhich VAF is integrating310 μm × 180node, μ m.especially The passive the resistors, components cover that a large make area. up Thethe referencesuggested voltage design, divider with a andnominal the VAF 1.8 V integrating power supply, node, oscillates especially at the 18.13 resistors, MHz, consumingcover a large 245.7 area. μTheW. Figuresuggested 9c shows design, the with simulated a nominal power 1.8 Vdistribution power supply, ratio oscillatesof each block at 18.13 in the MHz, proposed consuming oscillator. 245.7

TheμW. highestFigure 9cpower shows consumers the simulated are power𝑅 and distribution the first-stage ratio of inverter each block due in to the the proposed charge/discharge oscillator. operationElectronicsThe highest2019 and, 8power ,LTV 1353 control consumers are 𝑹𝑶𝑺𝑪 and the first-stage inverter due to the charge/discharge9 of 11 operation and LTV control

Figure 10. Simulated phase noise of the proposed oscillator. The blue line and red line represent withoutFigure 10.the SimulatedSimulatedfeedback and phase phase with noise the feedback,of the proposed respectively. oscillator.oscillator. The The blue blue line line and red line represent without the feedback and with the feedback, respectively.respectively.

Figure 11. Measured( aphase) noise of the proposed oscillator: (a) without the feedback(b) mechanism; (b) with the feedback mechanism. Figure 11. Measured phase noise of the proposed oscillator: (a) without the feedback mechanism;

(Inb) the with INV1 the feedback schematic mechanism. of Figure 8a, the input 𝑽𝑪𝑶𝑵𝑻 of PM3 and NM3 is disconnected, and the substrate of NM2 is tied to ground in order to implement a feedback-free structure. Figure 10 illustratesThe ﬁgure the simulated of merit phase (FOM), noise which characteristics. measures the The performance technique prop of anosed oscillator, in the simulation can be expressed reduces ( ) byoscillator the following phase noise two by equations. 4 dBc/Hz andL ∆ 2f dBc/Hz, fOSC, at and low-PDISS and representhigh-frequency phase offsets, noise respectively. at oﬀset frequency, Figure oscillation11 shows the frequency, measured and phase power noise consumption, characteristics respectively. when there is (a) no feedback, and (b) the suggested ! ∆ f PDISS FOM1 = L(∆ f ) + 20log + 10log (10) fOSC 1mW ! fOSC FOM2 = 10 log (11) PDISS

Under the measurement conditions, the proposed oscillator has FOM1 values of 151.35 and 157.53 at 1 kHz and 100 kHz frequency oﬀsets, respectively, and shows an FOM2 value of 108.7. The oscillation frequency, with respect to supply voltage, is illustrated in Figure 12. The solid line depicts the frequency variation of the proposed approach, and the dotted line shows the results without feedback. For a range of 1.7 V to 2.4 V, the proposed oscillator’s frequency variation is calculated as a maximum of 0.365(%/0.1 V), while without feedback, the eﬀect of the supply voltage on the oscillation frequency is 0.522(%/0.1 V). Electronics 2019, 8, x FOR PEER REVIEW 9 of 11

method is applied. As a result of the negative feedback that constitutes the LTV tracking loop, the proposed scheme reduces phase noise at low-frequency offsets. The phase noise at both the 100 Hz and the 1 kHz frequency offsets is decreased by 7.7 dBc/Hz (from –44.72 dBc/Hz to 52.42 dBc/Hz) and 5.45 dBc/Hz (from –54.64 dBc/Hz to –60.09 dBc/Hz), respectively. In the feedback-free structure, circuit noise produces some unwanted tones near 100 kHz, degrading the phase noise characteristics, while the proposed LTV tracking technique filters these tones out but still produces the 400 kHz tones. Compared with the simulation, the overall phase noise level is increased in the measurement. However, the amount of noise suppression remains similar. The figure of merit (FOM), which measures the performance of an oscillator, can be expressed by

the following two equations. 𝑳∆𝒇, 𝒇𝑶𝑺𝑪 , and 𝑷𝑫𝑰𝑺𝑺 represent phase noise at offset frequency, oscillation frequency, and power consumption, respectively.

∆𝒇 𝑷𝑫𝑰𝑺𝑺 𝑭𝑶𝑴𝟏 = 𝑳∆𝒇 + 𝟐𝟎𝒍𝒐𝒈 + 𝟏𝟎𝒍𝒐𝒈 (10) 𝒇𝑶𝑺𝑪 𝟏𝒎𝑾

𝒇𝑶𝑺𝑪 𝑭𝑶𝑴𝟐 =𝟏𝟎𝒍𝒐𝒈 (11) 𝑷𝑫𝑰𝑺𝑺

Under the measurement conditions, the proposed oscillator has 𝑭𝑶𝑴𝟏 values of 151.35 and Electronics 2019, 8, 1353 10 of 11 157.53 at 1 kHz and 100 kHz frequency offsets, respectively, and shows an 𝑭𝑶𝑴𝟐 value of 108.7.

FigureFigure 12. 12.Measured Measured oscillation oscillation frequency frequency for for the the supply supply voltage. voltage.

TableThe 1oscillation tabulates thefrequency, performance with ofrespect the proposed to supply LTV voltage, tracking is oscillator illustrated and in other Figure state-of-the-art 12. The solid designs.line depicts The oscillatorsthe frequency of [5 ]variation and [8] display of the goodproposed frequency approach, stability and against the dotted supply line variation, shows the but results their respectivewithout feedback.FOM1 values For area range signiﬁcantly of 1.7 low,V to due 2.4 toV, the the degradation proposed ofoscillator’s their phase frequency noise characteristics variation is atcalculated the oﬀset as frequencies. a maximum In of [2 0.365(%/0.1], the highest V),FOM while1 value without was feedback, demonstrated, the effect but of in the comparison, supply voltage our approachon the oscillation reduces frequencyfrequency inaccuracyis 0.522(%/0.1 with V). supply variations. Although our proposal requires a largerTable chip area1 tabulates for passive the performance components, of the the method proposed displays LTV FOMstracking comparable oscillator toand other other methods, state-of- duethe-art to suppressed designs. The phase oscill noiseators and of [5] good and frequency[8] display stability. good frequency stability against supply variation,

but their respective 𝑭𝑶𝑴𝟏 values are significantly low, due to the degradation of their phase noise characteristics at the offset frequencies.Table 1.InPerformance [2], the highest Summary. 𝑭𝑶𝑴𝟏 value was demonstrated, but in comparison,Reference our approach [1][ reduces2][ frequency3][ inaccuracy 5with][ supply 8]variations. THIS Although WORK our proposal requires a larger chip area for passive components, the method displays FOMs comparable Process(nm) 180 180 65 180 180 180 to other methods, due to suppressed phase noise and goodVoltage frequency stability. Inverter- based Voltage-to-delay Swing Switched Digital Approach averaging RC and LTV Feedback boosting capacitor Compensation Table 1. Performance Summary.feedback tracking feedback Area(mm2) 0.117 0.015 0.03 0.04 0.012 0.056 Frequency THIS Reference 1.6[1] 10.5 [2] 12.5 [3] 14 [5] 12.77 [8] 18.13 (MHz) WORK Jitter (ps) N.A. 9.86 N.A. 30 78.7 46.61 SupplyProcess(nm) (V) 1180 1.4 180 1.3 65 1.8180 0.9 180 1.8 180 Supply Var. 0.05 0.44 0.08 0.1 0.365 (worst) N.A. @1.2–1.52 V @1.4–2 V @1.7–1.9 V @0.6–1.1 V @1.7–2.4 V (%/0.1 V) Power (µW) 51.4 219.8 91 1/3600 2 45 56.2 245.7 FOM 1 N.A. 157.7 N.A. N.A. 133.3 151.35 @1kHz FOM 1 156 162.1 162 1/148 2 146 140.3 157.53 @100kHz 111.4 1 FOM 104.9 106.8 114.9 113.6 108.7 2 95.4 2 1 Excludes the power of the anti-jitter comparator. 2 Includes the power of the anti-jitter comparator.

5. Discussion and Conclusions This article suggests a method of suppressing flicker noise in an inverter-based, on-chip RC oscillator. By changing LTVINV1 with an adjusted pull-down strength in the first-stage inverter, the proposed LTV tracking feedback not only compensates for circuit delay variations, but also reduces low-frequency offset phase noise. The proposed oscillator operates at 18.13 MHz, consuming 245.7 µW from a 1.8 V power supply. The worst-case frequency variation with supply variation is 0.365%/0.1 V. The suggested technique reduces oscillator phase noise by 7.7 dBc/Hz and 5.45 dBc/Hz for 100 Hz Electronics 2019, 8, 1353 11 of 11 and 1 kHz frequency offsets, respectively. Furthermore, the proposed oscillator shows FOM values comparable with those of the latest technologies.

Author Contributions: Conceptualization, J.K.; Methodology, J.K.; Validation, J.K.; Formal analysis, J.K.; Investigation, J.K.; Data curation, J.K.; Writing—original draft preparation, J.K.; Writing—review and editing, J.K.; Visualization, J.K.; Supervision, M.L.; Project administration, M.L.; Funding acquisition, M.L. Funding: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. NRF-2019R1A2B5B01069415). Acknowledgments: The chip fabrication and EDA tool were supported by the IC Design Education Center (IDEC), Korea. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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