AND8054/D Designing RC Oscillator Circuits with Low Voltage

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Designing RC Oscillator Circuits with Low Voltage Operational Amplifiers and Comparators for Precision Sensor Applications http://onsemi.com

Jim Lepkowski APPLICATION NOTE Senior Applications Engineer Christopher Young Engineering Intern, Arizona State University

INTRODUCTION analog components provide a solution for the analog I/O The design of RC operational amplifier oscillators interface circuits that are required for emerging low voltage requires the use of a formal design procedure. In general, the DSP and microcontroller ICs. design equations for these oscillators are not available; There are a number of advantages that result from therefore, it is necessary to derive the design equations lowering the power supply voltage such as lower power symbolically to select the RC components and to determine consumption and the reduction of multiple power supplies. the influence of each component on the frequency of Low voltage analog design also results in new challenges for oscillation. A design procedure will be shown for two state the designer and care must be taken to transfer existing variable oscillator circuits that can be used in precision higher voltage circuits to the lower voltage levels. For capacitive sensor applications. These two oscillators have example, device parameters such as the bandwidth and slew an output frequency proportional to the product of two rate decrease as the voltage is reduced and are modest in capacitors (C1*C2) and the ratio of two capacitors (C1/C2). comparison to traditional devices operating at voltages such The state variable oscillators have been built using ON as ±10 V. Also, there is a limited voltage swing range Semiconductor’s new family of sub–1 volt operational available at low voltages; however, this problem is amplifiers and comparators. The MC33501, MC33503, and minimized by the rail–to–rail single voltage range of both NCS2001 operational amplifiers, and the NCS2200 the input and output signals of the ON Semiconductor comparator are the industry’s first and only commercially devices. available analog components that are specified at a voltage The MC33501 and MC33503 are designed with a of 0.9 volts. These components can be powered from a single BiCMOS process, while the NCS2001 and NCS2200 are NiCd, NiMH or alkaline battery cell. The wide operating implemented with a full CMOS process. The main attributes temperature range of –40_C to +105_C makes these devices of these devices are their low voltage operation and a full suitable for a wide range of applications. rail–to–rail input and output range. The rail–to–rail ON Semiconductor’s family of low voltage operational operation is provided by using a unique input stage that is amplifiers and comparators help solve the analog limitations formed by a folded cascade N–channel depletion mode that have resulted from the industry’s movement to low differential amplifier. A simplified schematic of the power supply voltages. The ON Semiconductor family of MC33501 and MC33503 is shown in Figure 1.

 Semiconductor Components Industries, LLC, 2002 1 Publication Order Number: February, 2002 – Rev. 1 AND8054/D AND8054/D

VCC

IN– IN+

Offset Out Voltage VCC VCC Trim VCC Output Voltage Clamp Saturation Detector

Body Bias

Figure 1. Simplified Schematic of the MC33501/MC33503

ON Semiconductor’s Family of Low Voltage Operational Amplifiers and Comparators Part Number Component Process Features Package Availability MC33501 Operational BiCMOS @ Single Supply Operation of 1.0 V TSOP–5 Available NOW MC33503 Amplifier • Gain Bandwidth Product = 3 MHz (typ.) Production Release 4Q2000 • Open Loop Voltage Gain = 90 dB (typ.) NCS2001 Operational CMOS @ Single Supply Operation of 0.9 V TSOP–5 Available NOW Amplifier • Gain Bandwidth Product = 1.1 MHz (typ.) Production Release 1Q2001 • Open Loop Voltage Gain = 90 dB (typ.) NCS2200 Comparator CMOS @ Single Supply Operation of 1.0 V TSOP–5 Product Preview • Propagation Delay 1.1 ms (typ.) Production Release 1Q2002 • Complementary or Open Drain Output Configuration

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TRANSDUCER SYSTEM accomplished by implementing a curve fitting routine with A wide variety of different circuits can be used to data obtained by calibrating the sensor over the operating accurately measure capacitive sensors. The design choices range. An analog IC sensor can be used to monitor the sensor include switched capacitor circuits, analog multivibrators, temperature or for very precise applications a second AC bridges, digital logic ICs and RC operational amplifier oscillator could be built with a platinum resistive oscillators. The requirements for a precision sensor circuit temperature device (RTD) sensor. include high accuracy, reliable start–up, good long–term In addition, it is often important for the sensor system to stability, low sensitivity to stray capacitance and a minimal compute the ratio of two capacitors. Calculating the ratio of component count. State variable RC operational amplifier the capacitors reduces the transducer’s sensitivity to oscillators meet all of the requirements listed above; thus, dielectric errors from factors such as temperature. In other they form the basis for this study. cases, such as in an air data quartz DP pressure sensors, the A block diagram of a capacitive sensor system is shown desired measurement is equal to the ratio of two in Figure 2. The oscillation frequency is found by counting capacitances (CMEAS / CREF). Furthermore, dual sensors are the number of clock pulses (i.e. MHz) in a time window that typically designed to double the CMEAS in capacitance, is formed by the square wave oscillator output (i.e. kHz) of while CREF may vary less than one percent. Thus, the a comparator circuit. The counter circuit can be transducer’s accuracy is increased if a circuit such as the implemented with a digital logic counter circuit or by using ratio state variable oscillator can directly detect the CMEAS the Time Processing Unit (TPU) channel of a to CREF ratio. microprocessor. If necessary, temperature correction can be

CMEAS CREF Clock

RC Op–Amp Counter Comparator Oscillator Circuit

Temperature Sensor Micro–Processor Algorithm: Count the number of clock pulses in a time window set by oscillator pulses.

EEPROM: Clock Temperature Signal Compensation Coefficients Oscillator Signal

Figure 2. Block Diagram of Capacitive Sensor Application

SENSOR APPLICATIONS attributes are shown in Table 1. The absolute and dual RC operational amplifier oscillators can be used to capacitive sensors will be used with the absolute and ratio accurately detect both resistive and capacitive sensors; oscillator circuits, respectively. Differential capacitive however, this paper will only analyze capacitive applications. sensors typically are not used in precision applications; The three basic configurations of capacitive sensors and their therefore, they will not be analyzed in this paper.

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Table 1. Summary of Capacitive Sensors

Sensor Configuration Absolute Dual Differential

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CMEAS

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Á Á Á C1

Schematic Representation CMEAS

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Á Á Á C2

CREF

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Á Á Á

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Sensor Applications • Absolute Pressure • Acceleration • Displacement

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Á Á

Á • Humidity • Oil Level • Proximity

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Á Á

Á • Oil Quality

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Á Á

Á • Differential Pressure

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ÁÁÁÁÁÁÁÁÁCircuit Absolute Oscillator Ratio Oscillator Typical Circuit – Multivibrator

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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁOscillation Frequency freq. T C C freq. T C * C

MEAS freq. T MEAS 1 2

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Á Á

Á CREF

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OSCILLATOR THEORY exponentially decaying. In contrast, if T(s) has one pole that An oscillator is a positive feedback control system which lies within the right half plane, the system is unstable does not have an external input signal, but will generate an because the corresponding term exponentially increases in output signal if certain conditions are met. In practice, a small amplitude. An oscillator is on the borderline between a input is applied to the feedback system from factors such as stable and an unstable system and is formed when a pair of noise pick–up or power supply transients, and this initiates the poles is on the imaginary axis, as shown in Figure 4. feedback process to produce a sustained oscillation. A block If the magnitude of the loop gain is greater than one and diagram of an oscillator is shown in Figure 3. the phase is zero, the amplitude of oscillation will increase The poles of the denominator of the transfer equation T(s), exponentially until a factor in the system such as the supply or equivalently the zeroes of the characteristic equation, voltage restricts the growth. In contrast, if the magnitude of determine the time domain behavior of the system. If T(s) the loop gain is less than one, the amplitude of oscillation has all of its poles located within the left plane, the system will exponentially decrease to zero. is stable because the corresponding terms are all

V + T(s) + OUT + A + A + A + A * b * D N(s) V A ≡ Amplifier Gain V VIN 1 A 1 LG s IN OUT D(s) – where A b + LG 5 loop gain Ds 5 characteristic equation

If VIN + 0, then T(s) +Rwhen Ds + 0 b ≡ Feedback Factor At the oscillation condition of Ds = 0, referred to as the Barkhausen stability criterion, |LG| + 1 (magnitude) and éLG + 0 (phase).

Figure 3. Block Diagram of an Oscillator

Imaginary (jω) Imaginary (jω)

Real (ω) Real (ω)

2nd Order Oscillator 3rd Order Oscillator

Figure 4. Pole Locations for a 2nd and 3rd Order Oscillator

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CIRCUIT DESCRIPTIONS oscillation. The first integrator stage consists of amplifier Absolute State Variable Oscillator A1, resistor R1 and sensor capacitance C1. The second The absolute state variable oscillator is used when the integrator consists of amplifier A2, resistor R2 and sensor measurement is proportional to either one or two capacitors capacitance C2. Resistor–capacitor combinations R1 and C1, α (i.e. freq. C1*C2). The block diagram and schematic of the and R2 and C2, set the gain of each integrator stage, in absolute circuit are shown in Figures 5 and 6. This circuit addition to setting the oscillation frequency. The inverter consists of two integrators and an inverter circuit. Each stage consists of amplifier A3, resistors R3 and R4 and _ integrator has a phase shift of 90 , while the inverter adds an capacitor C4. Capacitor C4 is not essential for normal additional 180_ phase shift; thus, a total phase shift of 360_ operation; however, it ensures oscillator startup under is fed into the input of the first integrator to produce the extreme ambient temperature conditions.

Limit Circuit

V1 V2 V3 Integrator Integrator Inverter

6 q = 90° 6 q = 90° 6 q = 180°

Figure 5. Absolute Oscillator Block Diagram

Limit Circuit

C1 C2 R4

R1 A1 R2 – A2 R3 – A3 + – V + 1 + V2 V3

The absolute sensor capacitances C1 and C2 are used by the integration amplifiers.

Figure 6. Absolute Oscillator Schematic

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Ratio State Variable Oscillator R5, and the sensor capacitors C3 and C4 form the The ratio state variable oscillator [6] is used for dual differentiator stage which provides a 180_ phase shift. The capacitive sensors when the oscillation frequency is values of resistors R3, R4 and R5 are selected to set the break proportional to the ratio of sensor capacitances C3 and C4 (i.e. frequencies of the differentiator stage, so that the gain of the α freq. C3 / C4). The block diagram and schematic of the ratio stage is equal to –C3/C4. Resistor R5 provides a DC current circuit are shown in Figures 7 and 8. This circuit consists of path through capacitor C3 in order to initiate oscillation at two integrators and a differentiator circuit. The integrators power–up. Because R5 is relatively large (MΩ), it can be formed by amplifier A1 and A2 are identical to the integrators replaced with a three resistor “Tee” network in order to use used in the absolute circuit. Amplifier A3, resistors R3, R4 and readily available resistors, as shown in Figure 9.

Limit Circuit

V1 V2 V3

Integrator Integrator Differentiator 6 θ = 180° 6 θ = 90° 6 θ = 90°

Figure 7. Ratio Oscillator Block Diagram

Limit Circuit

C1 C2 R4 C3

R1 A1 R2 – A2 R3 R5 – A3 + – V + 1 + V2 V3

The differentiator amplifier is formed by the dual sensor capacitances C3 and C4.

Figure 8. Ratio Oscillator Schematic C4

C1 C2 C3 R4 R1 A1 R2 – A2 – R3 R5a R5b A3 + – V1 + V2 + R5c V3

A Tee network provides a method to replace a large resistor (i.e. MΩ) with three small resistors (i.e. kΩ).

R5a R5b R5_equivalent + ) ) R5aR5b ⇔ R5_equivalent R5a R5b R5c R5c

Figure 9. Ratio Oscillator Schematic with R5 Tee Network

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OSCILLATOR DESIGN PROCEDURE Method II: Solve N(jwo)REAL = N(jwo)IMAGINARY = 0 Listed below is a procedure to design RC active The oscillation equation sometimes can be determined oscillators: directly from the characteristic equation by substituting Step 1: Find LG and ∆s s = jωo into N(s) and arranging N(jωo) into its real and Step 2: Solve ∆s = 0 for s = jωo using methods I, II or III imaginary parts. This method is usually not feasible for fifth N(s) order and higher oscillators. This procedure is essentially a Method I: Solve remainder of = 0 s2 ) w2 subset of the Routh test, because the first two rows of the o ω Method II: Solve N(jωο) = N(jω ) = 0 Routh array will correspond to N(j o)REAL and REAL o IMAG ω ω Method III: Routh’s stability test N(j o)IMAGINARY. If N(s) = j o = 0, the poles of the ± ω Step 3: Form sub–circuit design equations characteristic equation will be on the imaginary axis at j ο ω Step 4: Verify LG ≥ 1 with an oscillation frequency of o. A summary of the oscillation equations for 2nd and 3rd order oscillators Step 1: Find LG and ∆s obtained using Method II [13] is shown in Appendix II. The The oscillation frequency is determined by finding the application of Method II is shown for the 3rd order absolute poles of the denominator of the transfer equation T(s), or oscillator with the inverter capacitor C4. equivalently the zeroes of the numerator N(s) of the characteristic equation ∆s. Mason’s Reduction Theorem, Method III: Routh Stability Test shown in Appendix I, provides a method of determining the The Routh stability criterion [12] provides a method that transfer equation from a signal flow diagram. Mason’s determines the zeroes of the characteristic equation directly Theorem, listed below, shows that it is not necessary to from the characteristic polynomial coefficients, without the obtain the complete T(s) equation. The oscillation frequency necessity of factoring the equation. The Routh test, shown can be determined by analyzing the numerator N(s) of the in Appendix III, is the preferred method to use for fourth ∆s. ∆s is found by obtaining the open loop gain (LG) by order and higher order oscillators. The Routh test consists of breaking the feedback loop and applying a test voltage to the forming a coefficient array. Next, the procedure substitutes ω circuit. s = j o for s, and the summation of the row is set to zero. If the row equation produces a nontrivial solution for ωo, the T(s) + A + A + A 1 * LG D(s) ǒN(s)Ǔ procedure is complete and the frequency of oscillation is D(s) equal to ωo. If the row equation does not yield an equation that can be solved for ω , the procedure continues with the ∆ o Step 2: Solve s next row in the Routh array. Usually, it is necessary only to The second step in the procedure determines the zeroes of complete the first two or three rows of the Routh array to N(s). Several different control theory techniques such as the produce an equation that can be solved for ωo. Method III Bode or Nyquist stability tests can be used, or one of the will be demonstrated by analyzing the ratio oscillator. three methods that are listed below. Examples of the application of the three different methods listed below will Step 3: Sub–circuit Design Equations be provided. The third step in the design procedure is to form the design equations for the sub–circuits formed by each operational N(s) Method I: amplifier. The oscillation equation can be simplified by 2 ) w2 s o selecting the R’s and C’s with the assumptions shown in the An equation is established for the oscillation frequency ωo “Design Equation” section. The amplifier gain and N(s) pole/zero locations for the absolute and ratio oscillator are when N(s) is divided by s2 + ωο2 (i.e. ) and the 2 ) w2 s o also shown. remainder is solved to be equal to zero. Method I is easy to ≥ implement for second and third order systems, but with Step 4: Verify LG 1 higher order systems the algebra can be tedious. Method I is The final step in the procedure verifies that the loop gain described in [12] and is based on factoring the characteristic is equal to or greater than one after the R’s and C’s 2 2 component values have been chosen. This step is required to equation to have a s + ωo term. For example, when a third 2 2 verify that the location and clamping voltage of the limit order system can be factored in the form (s + β)(s + ωo ), circuit will not result in a LG < 1, or that the operational the pole locations are at s = ± jωo and s = –β. Method I will be demonstrated by analyzing the absolute oscillator amplifiers will reach their saturation voltage. The limit without the inverter capacitor C . Although the analysis of circuit can be located across any of the three amplifiers as 4 ≥ this second order system is trivial because N(s) is already in long as the LG 1. 2 2 the form of s + ωo , this method can be used for higher order circuits such as the 4th order ratio oscillator.

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ABSOLUTE OSCILLATOR DESIGN EQUATIONS C4

C1 C2 R4

R1 A1 – R2 A2 – R3 A3 + – V + 1 + V2 V3

Without C4 With C4

1 R4 1 +*ƪǒR4Ǔǒ 1 Ǔƫ A2 +* A3 +* A2 +* A3 ) sR2C2 R3 sR2C2 R3 sR4C4 1 V3 V1 V2 V3 V1 V2

1 1 A1 +* A1 +* sR1C1 sR1C1

Figure 10. Absolute Oscillator Signal Flow Diagrams

Absolute Oscillator (without C4) Step 1: Find LG and Ds The loop gain is found by breaking the loop and inserting a “test’’ voltage into the input. 1 1 R4 A1 + – A2 + – A3 + – sR1C1 sR2C2 R3 VTEST VOUT V1 V2 V3

VOUT LG + + A1 A2 A3 VTEST

N(s) R R R Ds + + 1 * LG + 1 * ǒ– 1 Ǔǒ– 1 Ǔǒ– 4Ǔ + 1 ) 4 + s2 ) 4 D(s) sR1C1 sR2C2 R3 s2R1R2R3C1C2 R1R2R3C1C2 2 ) + s R1R2R3C1C2 R4 s2R1R2R3C1C2

N(s) + s2R1R2R3C1C2 ) R4

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Absolute Oscillator (with C4) Step 1: Find LG and Ds The loop gain is found by breaking the loop and inserting a “test’’ voltage into the input.

1 1 R4 1 A1 + – A2 + – A3 + –ƪǒ Ǔǒ Ǔƫ sR1C1 sR2C2 R3 sR4C4 ) 1 VTEST VOUT V1 V2 V3

VOUT * Z4 R4 || C4 LG + + A1 A2 A3 A3 + + VTEST Z3 R3

+ ǒ 1 Ǔǒ 1 Ǔƪǒ R4Ǔǒ 1 Ǔƫ + R4 LG – – – ) – sR1C1 sR2C2 R3 sR4C4 1 s3R1R2R3R4C1C2C4 ) s2R1R2R3C1C2

N(s) R Ds + + 1 * LG + 1 ) 4 D(s) s3R1R2R3R4C1C2C4 ) s2R1R2R3C1C2

3 ) 2 ) + s R1R2R3R4C1C2C4 s R1R2R3C1C2 R4 s3R1R2R3R4C1C2C4 ) s2R1R2R3C1C2

N(s) + s3R1R2R3R4C1C2C4 ) s2R1R2R3C1C2 ) R4

Absolute Oscillator (without C4) Step 2: Solve N(s) using Method I N(s) Solve Method I: Solve the remainder of: 2 ) w2 s o N(s) + s2R1R2R3C1C2 ) R4

R1R2R3C1C2 R1R2R3C1C2s2 ) R4 s2 ) w2 oǸ * 2 ) w2 R1R2R3C1C2s oR1R2R3C1C2 * w2 R4 oR1R2R3C1C2

w * w2 + w + Ǹ R4 Set the remainder to equal zero and solve for o: R4 oR1R2R3C1C2 0 o R1R2R3C1C2

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Absolute Oscillator (with C4) a3 a2 Step 2: Solve N(s) using Method II shown in Appendix II: wo + Ǹ + Ǹ a1 a0

N(s) + a0s3 ) a1s2 ) a2s ) a3 + s3R1R2R3R4C1C2C4 ) s2R1R2R3C1C2 ) R4

a0 + R1R2R3R4C1C2C4

a1 + R1R2R3C1C2

a2 + 0

a3 + R4

a3 R4 wo + Ǹ + Ǹ a1 R1R2R3C1C2

Absolute Oscillator

Step 3a: Subcircuit Oscillation Design Equations

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Absolute Oscillator Without C4 With C4

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2 ) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á

Á N(s) R1R2R3C1C2s R4 R1R2R3R4C1C2C4s3 ) R1R2R3C1C2s2 ) R4

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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ R R

wo Ǹ 4 Ǹ 4

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Á Á

Á R1R2R3C1C2 R1R2R3C1C2

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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Ǹ Ǹ Oscillation Period P ^ 2pRC1C2 P ^ 2pRC1C2

+ 2p

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Á Á Á P w

o If R1 = R2 = R and R3 = R4 If R1 = R2 = R and R3 = R4

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Absolute Oscillator Step 3b: Subcircuit Amplifier Design Equations

Absolute Oscillator Without C4 With C4

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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ V1 1 * 1 V1 1 * 1 Integrator A1 Gain A1 + + – + A1 + + – +

V3 sR1C1 2pfR1C1 V3 sR1C1 2pfR1C1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á

+ 1 + 1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁPole Location

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ fp1 fp1

2p R1C1 2p R1C1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ V * V *

Integrator A2 Gain + 2 + 1 + 1 + 2 + 1 + 1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á A2 – A2 –

V1 sR2C2 2pfR2C2 V1 sR2C2 2pfR2C2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ 1 1

Pole Location fp2 + fp2 +

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á

Á 2p R2C2 2p R2C2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ V3 R4 V3 R4 1

Inverter A3 Gain A3 + + – A3 + + – ǒ Ǔ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á

Á V2 R3 V2 R3 sR4C4 ) 1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ + 1 Pole Location NńA fp3

2p R4C4

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ w w w w w w w w

* s o + s o + s o + –s o + s o + s o + s o + –s o +

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á

Á R R R R R1 R2 R3 R4 1 2 3 4 RC Sensitivities*

w w 1 w w 1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á s o + s o +* s o + s o +* C C

C1 C2 2 1 2 2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ǒDYǓ d ln(Y) *Sensitivity is defined as: SY + Y + X ǒDXǓ d ln(X) X

Absolute Oscillator Step 4: Verify LG . 1 Step 4 will be demonstrating using the dual power supply limit circuit shown in Figure 25. The design equations are listed below.

Assume: 1.) VPos_Limit + VNeg_Limit + VLimit

2.) V2 + VLimit (i.e. |A2| + VLimit)

3.) |A3| + R4ńR3 + 1

Check: 1.) Is |LG| + A1 A2 A3 w VLimit

1 R + ǒ Ǔ (VLimit) ǒ 4Ǔ w VLimit 2pfR1C1 R3

2.) Using the values shown in Figure 25,

ǒ 1 Ǔ (V )(1)w V 2p(16.6 kHz)(39 K W) (240 pF) Limit Limit

1.02 VLimit w VLimit thus the oscillation will be sustained.

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RATIO OSCILLATOR DESIGN EQUATIONS C4

C1 C2 R4 C3

R1 A1 – R2 A2 – R3 R5 A3 + – V + 1 + V2 V3

1 R4(sR5C3 ) 1) A2 + – A3 + – sR2C2 (sR3R5C3 ) R3 ) R5)(sR4C4 ) 1)

V V1 V2 3

1 A1 + – sR1C1

Figure 11. Ratio Oscillator Signal Flow Diagrams

Ratio Oscillator Step 1: Find LG and Ds The loop gain is found by breaking the loop and inserting a “test’’ voltage into the input. ) 1 1 R4(sR5C3 1) A1 + – A2 + – A3 + – sR1C1 sR2C2 (sR3R5C3 ) R3 ) R5)(sR4C4 ) 1) VTEST VOUT V1 V2 V3 ø VOUT –Z4 R4 C4 LG + + A1 A2 A3 A3 + + VTEST Z3 R3 ) (C3 ø R5)

R4(sR5C3 ) 1) LG + ǒ– 1 Ǔǒ– 1 Ǔǒ– Ǔ sR1C1 sR2C2 (sR3R5C3 ) R3 ) R5)(sR4C4 ) 1)

sR R C ) R LG +* 4 5 3 4 s4R1R2R3R4R5C1C2C3C4 ) s3[(R3R5C3 ) R3R4C4 ) R4R5C4)R1R2C1C2] ) s2(R3 ) R5)(R1R2C1C2)

s4R1R2R3R4R5C1C2C3C4 ) s3[(R3R5C3 ) R3R4C4 ) R4R5C4)R1R2C1C2] ) 2 ) ) ) N(s) s (R3 R5)(R1R2C1C2) sR4R5C3 R4 Ds + + 1 * LG + D(s) s4R1R2R3R4R5C1C2C3C4 ) s3[(R3R5C3 ) R3R4C4 ) R4R5C4)R1R2C1C2] ) s2(R3 ) R5)(R1R2C1C2)

N(s) + s4R1R2R3R4R5C1C2C3C4 ) s3[(R3R5C3 ) R3R4C4 ) R4R5C4)R1R2C1C2] ) s2(R3 ) R5)(R1R2C1C2) ) sR4R5C3 ) R4

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Ratio Oscillator Step 2: Solve N(s) using Method III (Routh’s Stability Test) shown in Appendix III N(s) + s4R1R2R3R4R5C1C2C3C4 ) s3[(R3R5C3 ) R3R4C4 ) R4R5C4)R1R2C1C2] ) s2(R3 ) R5)(R1R2C1C2) ) sR4R5C3 ) R4

Ds + a0s4 ) a1s3 ) a2s2 ) a3s ) a4 a0 + R1R2R3R4R5C1C2C3C4 a1 + [(R3R5C3 ) R3R4C4 ) R4R5C4)R1R2C1C2] a2 + (R3 ) R5)(R1R2C1C2) a3 + R4R5C3 a4 + R4

Routh’s Stability Test Array

Row s4 a0 ) a2 ) a4 à R1R2R3R4R5C1C2C3C4 (R3 ) R5)R1R2C1C2 R4 Row s3 a1 ) a3 à (R3R5C3 ) R3R4C4 ) R4R5C4)R1R2C1C2 R4R5C3

Determine when the row s3 equation is equal to zero. a1s3 ) a3s + s(a1s2 ) a3) + 0 Let s + jwo : a R R C w3 ) w +* w w2 * + w2 + 3 + 4 5 3 –j oa1 j oa3 j o(a1 o a3) 0 o a1 (R1R2C1C2)(R3R5C3 ) R3R4C4 ) R4R5C4)

Ratio Oscillator

Step 3a: Subcircuit Oscillation Design Equations

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

s4R1R2R3R4R5C1C2C3C4 ) s3[(R3R5C3) ) (R3R4C4) ) (R4R5C4)](R1R2C1C2)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á N(s)

) s2(R ) R )(R R C C ) ) sR R C ) R

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á

Á 3 5 1 2 1 2 4 5 3 4

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁw Ǹ R4R5C3 o

R1R2C1C2(R3R5C3 ) R3R4C4 ) R4R5C4)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ If R1 + R2 + R and C1 + C2 + C If R5 ơ R3 and R4 ơ R3 then

Oscillation Period

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á

Á p P + 2 ǒR3C4 C4 R3Ǔ ǸC4

wo P + 2pRC Ǹ ) ) P ^ 2pRC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ R Á

Á R5C3 C3 4 C3

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ratio Oscillator

Step 3b: Subcircuit Amplifier Design Equations ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁIntegrator A V * 1 A + 1 + – 1 + 1 f + 1

Gain/Pole Location 1 V sR C 2pfR C p1 2pR C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á 3 1 1 1 1 1 1

Integrator A

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ2 V2 1 * 1 1 A2 + + – + fp2 +

Gain/Pole Location V1 sR2C2 2pfR2C2 2pR2C2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

R4(sR5C3 ) 1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á A3 +

(R3 ) R5)(sR3C3 ) 1)(sR4C4 ) 1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Differentiator A3 Gain

–R –C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á DC Gain + 4 Gain at Oscillation + 3

R3 ) R5 C4

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

+ 1 + 1 + 1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Pole/Zero Locations fp1 fp2 fz1

2pR4C4 2pR3C3 2pR5C3

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ w w w w w w RC Sensitivities s o + s o + s o + s o +*s o + s o + –1

R R C C C C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á

Á 1 2 1 2 3 4 2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

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Gain (dB) Assumptions C3 1. C3 u C4 20x log 10ǒ Ǔ C4 2. C3 [ C4 3. R3 t R4 t R5 tt [ R5 1 Oscillation 4. R3 R5 and R4 Fz1 + 10 2pR5C3 Range

0 Frequency (Hz)

1 1 Fp1 + Fp2 + 2pR4C4 2pR3C3

R4 20x log 10ǒ Ǔ R3 ) R5

Figure 12. Bode Plot of Differentiator Amplifier A3

Ratio Oscillator Step 4: Verify LG . 1 Step 4 will be demonstrating using the single power supply limit circuit shown in Figure 26. The design equations are listed below. Assume: + + 1.) V2 VMax_Limit (i.e.|A2| VMax_Limit) C 2.) |A3| + 3 C4

Check: 1.) Is |LG| + A1 A2 A3 w VMax_Limit

1 C3 + ǒ Ǔ (VMax_Limit) ǒ Ǔ w VMax_Limit 2pfR1C1 C4

2.) Using the values shown in Figure 26, 1 C3 ǒ Ǔ (VMax_Limit) ǒ Ǔ w VMax_Limit 2p(16.5 kHz)(39 K W) (240 pF) C4 C3 (1.03) (VMax_Limit) ǒ Ǔ w VMax_Limit C4

3.) Oscillation will be sustained if

C3 w ǒ 1 Ǔ C4 1.03

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COMPONENT SELECTION If the integrator offset and bias errors are referenced to the Operation Amplifiers output, as shown below, The selection of an appropriate operational amplifier in a dV (t) precision oscillator application is based on analyzing the OUT + VIO ) IB dt RC C errors caused by the amplifiers. Operational amplifier errors include input offset voltage (V ) and input bias current (I ), the following observations can be made: IO B 1. Use small R, large C. open loop gain (Ao), and a finite bandwidth and slew rate ∝ ∝ (SR). The error contribution of the operational amplifier can 2. VOS 1 / RC and IB 1 / C . be minimized if a low bias current, wide bandwidth 3. Use a low leakage current capacitor. amplifier is chosen. Also, selecting a low oscillation 4. IB can be reduced if a resistor equal to the parallel frequency minimizes the DC gain and bandwidth errors. In combination of R and C is connected to the sensor applications, only the frequency of the signal is non–inverting input of the amplifier. monitored; therefore, the DC amplifier errors of VOS, IB, The error due to the operational amplifier’s finite open and a finite gain will result in output signal distortion, but loop gain and bandwidth, as shown below: will not have a significant effect on the oscillation frequency. The open loop gain of almost all amplifiers will ȱ ȳ VOUT(s) + ƪ* 1 ƫȧ 1 ȧ be several orders of magnitude larger than the closed loop 1)T 1 VIN(s) sRC Ȳ1 ) ǒ osǓǒ1 ) Ǔȴ gain of an oscillator, which typically is 1 to 2 at each Ao sRpC amplifier. The AC amplifier errors resulting from a finite slew rate and bandwidth has a minimal effect if the = ideal (gain )bandwidth error) oscillation frequency is relatively low (i.e. 10 kHz to where: 20 kHz). RdR Rp + Integrators Rd ) R C Rd ≡ open loop impedance To ≡ –3 dB frequency R ω1 ≡ the unity gain bandwidth ≈ Ao / To V – IN V + OUT If Ao >> 1, the transfer equation can be simplified to: ȱ ȳ V (s) Figure 13. Ideal Integrator Amplifier OUT + ƪ– 1 ƫȧ 1 ȧ VIN(s) sRC 1 ) 1 ) Tos ) 1 ) To Listed below are the equations for the ideal integrator Ȳ Ao Ao AoRpCs AoRpCȴ circuit formed by a single resistor and a capacitor as shown in Figure 13. ȱ ȳ ^ ƪ– 1 ƫȧ 1 ȧ sRC s 1 V (t) +* 1 ŕ V (t)dt Ȳ1 ) w ) ȴ OUT RC IN 1 AoRpCs V (s) OUT + – 1 Also, there will be an error due to the amplifier slew rate VIN(s) sRC and output current limitation. The slew rate error is defined The ideal integrator equations do not consider the effect as: of the amplifiers voltage offset and current bias offset errors. dVOUT(t) | + 2pf E + SR The effect of the offset errors is shown below [3][11]. dt max p o 1 1 1 where: fP ≡ full power response VOUT(t) + – ŕ VIN(t)dt " ŕ VIOdt ) ŕ IBdt " VIO RC RC C Eo ≡ rated output voltage

= ideal offset error bias error The output current (Io) of the amplifier charges the integrator feedback capacitor; thus, the integrator may have Where VIO and IB are defined as: a slew rate that is less than the specified amplifier SR. The DV V + V ) IO DT maximum rate of change of output voltage is equal to I /C. IO IO DT (Temp) o DVIO DVIO ) DVs(PowerSupply) ) Dt(Time) DVs Dt DI I + I ) B DT B B DT (Temp) DIB DIB ) DVs(PowerSupply) ) Dt(Time) DVS Dt

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Differentiator A practical differentiator circuit is shown in Figure 15. For R simplicity, this circuit will neglect the effect of resistor R5. There will be an error due to the operational amplifier’s C finite open loop gain as shown below: VIN – VOUT A + s o 1 V (s) * OUT + 1 Ao R3C4 VIN(s) s2 ) sƪ 1 ) 1 ƫ ) 1 Figure 14. Ideal Differentiator R4C4 R3C3 R3R4C3C4 Listed below are the equations for the ideal differentiator If Ao >> 1, the transfer equation can be simplified to: circuit shown in Figure 14. * sǒ 1 Ǔ V (s) R C * OUT ^ 3 4 ^ sR4C3 dVIN(t) V (s) ǒ 1 Ǔǒ 1 Ǔ ǒ ) Ǔǒ ) Ǔ VOUT(t) +*RC IN s ) s ) sR3C3 1 sR4C4 1 dt R3C3 R4C4 V (s) OUT +*sRC C4 VIN(s) R5 However, the ideal differentiator does not consider the R4 effect of the amplifier’s voltage offset and current bias errors, as shown below [3]. R3 C3 VIN(t) VIN – V (t) +*RC " V " I R VOUT OUT dt IO B + If the output offset and bias errors are referenced to the input, as shown below, Figure 15. Practical Differentiator (Neglect R5) dV (t) IN +" VIO " IB dt error RC C The error due to the operational amplifier’s finite open loop gain and bandwidth is shown graphically in Figure 16. the following observations can be made: The oscillator’s amplifier error and bandwidth error terms 1. Use small R, large C. are reduced if a higher gain and increased operational 2. VIO ∝ 1 / RC and IB ∝ 1 / C . amplifier is selected. The oscillation error can be minimized by selecting an oscillation frequency that is as low as practical (i.e. foscillation ≅ 10 KHz). The Slew Rate (SR) error of a differentiator is identical to the equation listed for an integrator. dVOUT(t) | + 2pfpEo + SR dt max Gain (dB)

Open Loop Gain

Gain Error

C3 20x logǒ Ǔ Bandwidth C4 Error 0 Frequency (Hz) To F + 1 R4 P1 2pR C 20x logǒ Ǔ 4 4 Closed Loop Gain R3 ) R5 + 1 Fp2 p 1 2 R3C3 Fz1 + 2pR4C3 Figure 16. Graphical Error Analysis of Ideal Differentiator

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Voltage Limit Circuits VCC Automatic Gain Control (AGC) circuits and voltage limit or bounding circuits are used in oscillators to prevent the U1 V + operational amplifiers from saturating and to avoid IN V – OUT amplifier slew rate limitations. Bipolar transistors are inherently slow in coming out of saturation; therefore, a R1 limit circuit should be used to prevent a frequency error VEE when using amplifiers such as the BiCMOS MC33501 or MC33503. FET transistors do not have the slow recovery time problem coming out of saturation; however, a limit R2 circuit should also be used with CMOS operational Q1 amplifiers. The gain of the transistors in a CMOS operational amplifier such as the NCS2001 will change AGC when the transistors saturate; thus, a limit circuit is necessary to prevent an oscillation error. Limit circuits will also decrease the required time for the oscillation signal to stabilize at start–up. When an Figure 17. FET AGC Circuit oscillator’s poles are located exactly on the imaginary axis, Limit Circuits the resulting waveform will be a perfect sinusoidal signal. Limit circuits are nonlinear circuits, which clamp the To ensure oscillation startup the poles are adjusted to lie amplitude to a voltage level that is less than the amplifier slightly in the right half s–plane causing the signal to grow power supply voltage. This clamping function will produce exponentially until it is limited by some type of distortion in the oscillator signal. The selection of the non–linearity, such as the saturation voltage of the amplifier. voltage limit circuits is based on the allowable signal AGC Circuits distortion and the simplicity of the circuit. The distortion Automatic Gain Control (AGC) circuits provide a linear level for most sensor oscillator circuits is relatively control of the amplifier gain to produce a constant output unimportant because only the frequency of the signal is voltage regardless of the level of the input signal. AGC monitored. Also, limit circuits are preferable to AGC circuits are usually used in applications where the level of circuits because they require fewer components. Limit signal distortion needs to be minimized. AGC circuits are circuits typically consist of a combination of zener diodes, more complex than limit circuits and usually consist of an diodes, and transistors. operational amplifier and/or FET that are used as a variable resistor. An example of an AGC circuit is shown in Figure 17.

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Dual Power Supply Limit Circuits available in voltages of about 1.8 volts, while their forward Figure 18 shows the clamping function of the limit circuit voltage drop is typically 0.7; therefore, this circuit is not for a dual power supply application. A simple dual supply useful for voltage limiting applications below 2.5 volts. voltage limit circuit can be created by using two The minimum voltage range of the back–to–back zener back–to–back zeners as shown in Figure 19. There are diode limit circuit can be reduced by adding two resistors to several performance limitations with this circuit that result the limit circuit as shown in Figure 20 [4]. The clamping from the relative large junction capacitance, leakage current value of this circuit is a function of the zener diode and temperature coefficient of a zener diode. These breakdown voltage multiplied by the ratio of the resistors. limitations result in a distortion of the output signal and an This circuit is solves the low voltage limitation of the error in the oscillation frequency. In addition, this circuit’s back–to–back zener limit circuit; however, this circuit is not low voltage operation is limited to the value of the zener suitable for the integrator amplifiers of the oscillator when diode’s clamping voltage (VZener) plus the forward voltage resistor R2 is replaced by a capacitor. drop (Vf) of the second zener diode. Zener diodes are

D1 D2

VIN and VOUT R2

VIN

VOUT VCC VPos_Limit R1 V – IN V + OUT

VNeg_Limit VEE

VLimit +" (VZener ) Vf) Figure 18. Dual Power Supply Clamping Figure 19. Back–to–Back Zener Diode Limit Circuit

D1 D2

R1a R1b R2 VIN

VCC

– V + OUT

VEE

R2 VLimit ^" (VZener ) Vf) * R1b ) R2

Figure 20. Back–to–Back Zener Diode Limit Circuit with Voltage Ratio Resistors

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The voltage limit circuit shown in Figure 21 is useful in Single Power Supply Circuits dual power supply designs when the integrator capacitance Figure 22 shows the clamping function of the limit circuit is relatively small. A combination of two transistors and two for a single power supply application [3] [4]. The limit diodes are used to make up the circuit, which limits the circuit for low voltage single supply circuits can be formed signal at positive and negative voltages. The diodes are used by a single NPN or PNP transistor. The PNP circuit shown to reduce the effective capacitance of the bipolar transistors in Figure 23 is used to create the maximum voltage limit, and they can be removed for low voltage applications. while the NPN circuit shown in Figure 24 is used to form the The operation of the limit circuits formed by the NPN minimum voltage limit. Note that in single supply and/or PNP transistors can be understood by using the applications it is not necessary to use both the PNP and NPN Ebers–Moll transistor model, where a transistor is modeled limit circuits. Only one of the limit circuits is required to as a base–to–emitter and a base–to–collector diode. The prevent the amplifiers from saturating in the state variable circuit functions by setting the fixed voltage at the oscillator. base–to–collector junction to be less than the diode’s turn–on voltage; therefore, this diode is always “OFF’’. VIN and VOUT Next, the emitter of the transistor is connected to the sine wave output of the amplifier; thus, the base–to–emitter VIN voltage (VBE) can be either greater than or less than a diode’s turn–on voltage. When the VBE voltage is above the diode’s VOUT turn–on voltage, the diode is “ON’’ and the transistor is in VMax_Limit the forward–active mode of operation and the circuit clamps at a level set by the base voltage. However, when the VBE voltage is below the diode turn–on voltage, the junction is “OFF’’ and the transistor is in the cut–off mode of operation and the clamping network is effectively an open circuit. VMin_Limit t

VQ1_Base D1 Figure 22. Single Power Supply Clamping Q1

VQ2_Base D2 VQ1_Base Q2

Q1 C

C VCC

V VIN R CC – VOUT + R VIN – V VOUT EE VCC/2 + VEE

VQ1_Base u 0V VQ2_Base t 0V

+ ) ) VPos_Limit VQ1_base VQ1_base–to–emitter Vf VMax_Limit + VQ1_base ) VQ1_base–to–emitter

^ VQ1_base ) (2 * 0.7) ^ VQ1_base ) 1.4 V ^ VQ1_base ) 0.7 V

VNeg_Limit + VQ2_base * VQ2_base–to–emitter * Vf Figure 23. Single Supply Maximum Limit Circuit

^ VQ2_base * (2 * 0.7) ^ VQ2_base * 1.4 V

Figure 21. Dual Power Supply Limit Circuit

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VQ1_Base specification of 200 ppm or ± 0.02 pF, whichever is greater, for a 2000 hour life test at 200% WVDC and a temperature of 125_C. The major error term of capacitors is due to Q1 temperature hysteresis and is specified as the retrace error. Precision sensors use temperature compensation, thus a C change of capacitance with temperature can be corrected; however, it is difficult to correct for hysteresis errors. Other error sources are a result of the piezoelectric effect (∆C vs. VCC voltage and pressure), the quality factor (Q), and the R terminal resistance. These errors are relatively small VIN – because the capacitors are designed for microwave VOUT VCC/2 + frequencies and are specified at a WVDC well beyond the VEE normal operating voltage of an op–amp circuit.

APPLICATION ISSUES VMin_Limit + VQ1_base * VQ1_base–to–emitter Remote Sensing Often, it is necessary to remotely locate the detection ^ VQ1_base * 0.7 V circuit from the sensor, and connect the sensor to the circuit Figure 24. Single Supply Minimum Limit Circuit with a shielded cable. For example, an oil level sensor for a gas turbine engine must operate at a temperature of 400°F, Resistors and Capacitors which is well beyond the operating capability of standard It is critical that the oscillator circuits use precision electronic components. In addition, a shielded cable is often resistors and capacitors with a small temperature coefficient required to limit the noise sensitivity of the measurement. (TC) and low drift rate to minimize temperature and aging The capacitance of shielded wire is typically 30 to 50 pF per errors. Long term stability is typically specified for resistors foot, while the sensor capacitance is usually less than 100 pF. and capacitors by a life test of 2000 hours at the maximum Thus, the electronic circuit must be insensitive to the cable rated power and ambient temperature. In general these capacitance which will be much larger than the sensor components have an exponential change in value for the first capacitance. 500 hours of the test and are essentially stable for the One approach to minimize the cable capacitance error is remainder of the test. Thus, a burn–in, or temperature to use a shielded cable and the virtual ground feature of an cycling procedure will significantly lower the drift error of operational amplifier when the non–inverting input is the resistors and capacitors. grounded. This feature is inherent in the integrator and Three types of precision resistors are available: metal inverter/differentiator circuits used in the state variable film, wirewound, and foil. Metal film and wirewound oscillator. Because an operational amplifier has a high open resistors are available with a TC of ±10 to ±25 ppm/_C and loop gain and input impedance, the differential voltage a drift specification of approximately 0.1 to 0.5%. Foil between the inverting and non–inverting inputs is resistors are available with a TC of ±0.3 ppm/_C and a drift essentially zero. Thus, the voltage potential at the inverting specification of less than 20 ppm. Errors with resistors are input is equal to the ground potential at the non–inverting caused by both environmental and manufacturing factors. terminal. The virtual ground approach forces a constant The major environmental factors causing changes in voltage to appear across the cable capacitance; therefore, the resistance are the operating power and the ambient cable capacitance does not have to be charged or discharged temperature. Other environmental factors such as humidity, by the circuit and the oscillation frequency is not effected. the voltage coefficient (∆R vs. voltage), the thermal EMF A constant DC level at the non–inverting input in the single (due to the temperature difference between the leads and self power supply configuration is equivalent to a virtual ground heating), and storage will cause relatively small errors. because the AC level of the input terminals is equal to zero Manufacturing induced errors from factors such as volts. The remote sensing ability of the state variable soldering can cause a small change in resistance; however, oscillator will be analyzed in detail in a future application this error will not effect the component’s long term stability. note. Two of the leading technologies of stable capacitors are RF/Microwave multilayer porcelain and NPO (COG) Reference Design ceramic capacitors. The TC of porcelain capacitors is The reference design for the absolute oscillator is shown specified at +90 ± 20 ppm/_C, while NPO ceramic in Figure 25. The circuit uses the BiCMOS MC33501 ± capacitors are available with a TC of 0 ± 30 ppm/_C. The TC operational amplifiers operated at a power supply of 2.5V. is specified over a temperature range of –55 to 125_C; In addition the circuit uses the dual supply limit circuit. The however, the specification is skewed by the relatively large operating voltage of the circuit could be lowered by changes in capacitance at the extreme hot and cold removing diodes D1 and D2, and adjusting the base voltages temperatures. Both types of capacitors have a drift of transistors Q1 (VPos_Limit) and Q2 (VNeg_Limit). In the

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typical application, capacitors C1 and C2 would be the The NCS2200 comparator is used by the ratio oscillator sensor capacitances. design to convert the oscillator’s sine wave output to a The reference design for the ratio circuit is shown in square ware digital signal. The NCS2200 is available in both Figure 26. This circuit uses the CMOS NCS2001 a complementary and an open drain output configuration. operational amplifiers operated at the single power supply The reference design used the open drain configuration to of 0.9V. In addition the circuit uses the single supply limit form a zero crossing detector. circuit. In the typical application, Capacitor C3 functions as Table 2 lists the calculated and measured oscillation the CMEAS sensor while C4 serves as the CREF sensor. frequency for the reference designs. The calculated The single supply Vcc/2 reference voltage was obtained frequency was obtained by measuring the R’s and C’s and by using a resistor divider network. The values of the using these values with the oscillation equations. resistors R9 and R10 were obtained by finding the input The measured frequency of the absolute and ratio impedances of the integrator circuits formed at amplifiers oscillators was approximately ±1% different than the A1 (R1 || C1) and A2 (R2 || C2). The input bias current of the calculated frequency. This error between the measure and CMOS amplifier is specified at only 10 pA; therefore, it is predicated oscillation frequency is probably due to the not necessary to balance the impedances at the capacitance of the limit circuits, which is not included in the non–inverting and inverting terminals of the amplifiers. In frequency equations. The reference designs used standard most applications, the non–inverting terminal can be NPN, PNP transistors and diodes; selecting high frequency connected directly to the reference voltage. Figure 27 shows or RF devices would minimize the oscillation error of the a voltage follower circuit that could be used to provide a limiting circuit. more stable reference voltage with the additional benefit of a low output impedance.

D1 MPS2907A 1N4001 Q1

VQ1_Base = 0.5 V

VQ2_Base = –0.5 V D2 1N4001

Q2 C4 MPS2222A 22 pF

C1 C2 240 pF 240 pF R4 10 k R1 39 k R2 A1 39 k R3 – A2 10 k – A3 + – + MC33501 + MC33501 MC33501

NOTES: 1. Power Supply Voltages for amplifiers A1, A2, and A3 are VCC = 2.5 V, VEE = 2.5 V 2. VPos_Limit = 1.9 V and VNeg_Limit = –1.9 V

Figure 25. Reference Design – Absolute Circuit

Table 2. Reference Designs Oscillation Frequency

Circuit Calculated Oscillation Frequency Measured Oscillation Frequency

Absolute Oscillator 16.6 kHz 16.4 kHz ÁÁÁÁÁÁÁÁÁÁÁÁ

Ratio Oscillator 16.5 kHz 16.3 kHz

ÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ

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MPS2907A Q1 VCC

R9 39 k VQ1_Base = 0.1 V VCC/2 R10 39 k

C4 VCC 47 pF C3 C1 C2 47 pF 240 pF 240 pF R4 R8 3 Meg R7 5 k R1 100 k 39 k R2 A1 39 k R3 R5 – A2 5 k 20 Meg R6 – A3 1 k VCC/2 + – A4 VCC/2 + + NCS2001 VCC/2 + NCS2001 V /2 – NCS2001 CC NCS2200

NOTES: 1. Power Supply Voltages for amplifiers A1, A2, A3, and A4 is VCC = 0.9 V, VEE = 0 V 2. Capacitors C3 and C4 are typically the sensor capacitance; however, for test purposes two 47 pF capacitors were used to verify the circuit. 3. VMax_Limit = 0.8 V Figure 26. Reference Design – Ratio Circuit

VCC

+ VCC/2 – R C

Figure 27. Low Output Impedance Reference Voltage

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Appendix I: Mason’s Reduction Theorem oscillator. In contrast, Step 1 of the design procedure only The oscillation frequency is determined by finding the provides the denominator of T(s) and will not provide the poles of the denominator of the transfer equation T(s) or numerator of the transfer equation. Mason’s equation can equivalently the zeroes of the numerator N(s) of the be rewritten in the form listed below: characteristic equation ∆(s). Mason’s theorem (12.) states T(s) + A + A + A that the transfer function from input X to output Y is 1 * LG D(s) ǒN(s)Ǔ D(s) S D Pi si The absolute and ratio oscillators only have a single T(s) + Y + i X Ds feedback loop, therefore, the calculation of + V3 where the terms are defined as: T(s) V11 Pi is the direct transmittance or path form input X is relatively easy because the path P1 (equivalent to the to output Y amplifier gain A) is defined as the voltage gain from node V11 to V3 and will be equal to the loop gain LG1. In order to D si is the system determinant. calculate the transfer equation, the intermediate voltage node of V is created by adding a “small” resistor R in Dsi + 1ifPi touches all of the loops 11 11 series with resistor R1 to the absolute and ratio circuits as Ȁ Ȁ Ds + 1 * SLj ) S LkLl * S LmLnLn )AAA shown in Figures 29 and 30. Adding R11 and V11 is not mathematically necessary; however, it greatly simplifies SLj is the sum of all loops (i.e. loop gains) the algebra in the transfer equations. Note, the numerator of S the transfer equation depends on the definition of the input LkLl is the sum of products of pairs of and outputs; however, the denominator (i.e. the oscillation non–touching loops equation) is independent of the definition of T(s). If R1 >> SLmLnLo is the sum of products of gains of R11, then the gain of amplifier A1 is a function only of R1 non–touching loops taken three at a and C1. time 1 1 A1 + ǒ– Ǔ ^ – s(R1 ) R11)C1 sR1C1 Mason’s Reduction Theorem should be used to determine the transfer equation if the oscillator has more than one Listed below are the calculation of T(s) for the absolute feedback loop, such as the case for the circuit shown in oscillator with and without capacitor C4 and the ratio Figure 28. Obtaining T(s) also provides the additional oscillator. information required to complete a Bode plot of the

C1 C2 R4

R1 A1 V1 R2 – A2 R3 – A3 + – + V3 V2 + R5

Figure 28. Mason’s Theorem Provides a Method to Determine the Transfer Equation T(s) of an Oscillator when there are Multiple Feedback Loops, as with the Modified Absolute Circuit

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C1 C2 R4

R11 R1

– A1

R2 – A2 +

R3 – A3

V11 + V1 + V2 V3

Figure 29. Schematic of the Absolute Oscillator with Rll that is Used to Obtain T(s), using Mason’s Reduction Theorem

Absolute Oscillator (without C4) Assume R1 >> R11, then R1 + R11 ` R1 1 1 R4 P1 + LG1 + A1 A2 A3 + ǒ– Ǔǒ– Ǔǒ– Ǔ sR1C1 sR2C2 R3

1 1 R4 R4 s2R1R2R3C1C2 ) R4 Ds + 1 * LG1 + 1 * ǒ– Ǔǒ– Ǔǒ– Ǔ + 1 ) + sR1C1 sR2C2 R3 s2R1R2R3C1C2 s2R1R2R3C1C2

ǒ R4 Ǔ 2 * + V3 + P1 + s R1R2R3C1C2 + R4 T(s) D V11 s ǒs2R1R2R3C1C2)R4Ǔ s2R1R2R3C1C2 ) R4 s2R1R2R3C1C2

Absolute Oscillator (with C4) Assume R1 >> R11, then R1 + R11 ` R1

P1 + LG + A1 A2 A3

1 1 R4 1 * R4 P1 + LG + ǒ– Ǔǒ– Ǔƪǒ– Ǔǒ Ǔƫ + – sR1C1 sR2C2 R3 sR4C4 ) 1 s3R1R2R3R4C1C2C4 ) s2R1R2R3C1C2

R s3R R R R C C C ) s2R R R C C ) R Ds + 1 * LG + 1 ) 4 + 1 2 3 4 1 2 4 1 2 3 1 2 4 s3R1R2R3R4C1C2C4 ) s2R1R2R3C1C2 s3R1R2R3R4C1C2C4 ) s2R1R2R3C1C2

ǒ *R4 Ǔ P s3R R R R C C C )s2R R R C C * R T(s) + 1 + 1 2 3 4 1 2 4 1 2 3 1 2 + 4 D ) ) ) ) s ǒs3R1R2R3R4C1C2C4 s2R1R2R3C1C2 R4Ǔ s3R1R2R3R4C1C2C4 s2R1R2R3C1C2 R4 s3R1R2R3R4C1C2C4)s2R1R2R3C1C2

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Ratio Oscillator C4

C1 C2 R4 C3

R11 R1

– A1 R2

– A2

+ R3 R5

– A3

V11 + V1 + V 2 V3

Figure 30. Schematic of the Ratio Oscillator with Rll that is Used to Obtain T(s), using Mason’s Reduction Theorem.

Ratio Circuit Assume R1 >> R11 , then R1 + R11 ` R1 ) 1 1 R4(sR5C3 1) P1 + LG + A1 A2 A3 + ǒ– Ǔǒ– Ǔǒ– Ǔ sR1C1 sR2C2 (sR3R5C3 ) R3 ) R5)(sR4C4 ) 1)

* (sR4R5C3 ) R4) P + LG + 1 1 ƪǒ Ǔ ƫ ǒ Ǔǒ Ǔ s4R1R2R3R4R5C1C2C3C4 ) s3 R3R5C3 ) R3R4C4 ) R4R5C4 R1R2C1C2 ) s2 R3 ) R5 R1R2C1C2

ƪǒ Ǔ ƫ ǒ Ǔǒ Ǔ s4R1R2R3R4R5C1C2C3C4 ) s3 R3R5C3 ) R3R4C4 ) R4R5C4 R1R2C1C2 ) s2 R3 ) R5 R1R2C1C2 ) sR4R5C3 ) R4 Ds + 1 * LG1 + 4 ) 3ƪǒ ) ) Ǔ ƫ ) 2ǒ ) Ǔǒ Ǔ s R1R2R3R4R5C1C2C3C4 s R3R5C3 R3R4C4 R4R5C4 R1R2C1C2 s R3 R5 R1R2C1C2

ǒ *(sR4R5C3)R4) Ǔ 4 ) 3ƪǒ ) ) Ǔ ƫ) 2ǒ ) Ǔǒ Ǔ V P s R1R2R3R4R5C1C2C3C4 s R3R5C3 R3R4C4 R4R5C4 R1R2C1C2 s R3 R5 R1R2C1C2 T(s) + 3 + 1 + V11 Ds ƪǒ Ǔ ƫ ǒ Ǔǒ Ǔ ǒs4R1R2R3R4R5C1C2C3C4)s3 R3R5C3)R3R4C4)R4R5C4 R1R2C1C2 )s2 R3)R5 R1R2C1C2 )sR4R5C3)R4Ǔ ǒ Ǔ ǒ Ǔǒ Ǔ s4R1R2R3R4R5C1C2C3C4)s3ƪ R3R5C3)R3R4C4)R4R5C4 R1R2C1C2ƫ)s2 R3)R5 R1R2C1C2

* (sR R C ) R ) + 4 5 3 4 ƪ ƫ ǒ Ǔǒ Ǔ s4R1R2R3R4R5C1C2C3C4 ) s3 (R3R5C3 ) R3R4C4 ) R4R5C4)R1R2C1C2 ) s2 R3 ) R5 R1R2C1C2 ) sR4R5C3 ) R4

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Appendix II: Method II: Let s = jωο be the frequency at which N2(s) = 0. The ω ω Solve N(j o)REAL = N(j o)IMAGINARY = 0 condition for oscillation is meet when the a1 term is set to The oscillation equation sometimes can be determined zero, and the s–term is removed. The frequency of directly from the characteristic equation by substituting oscillation is found from: s = jωο into ∆s and arranging the N(jωο) into its real and a imaginary parts. However, this method is usually not w + Ǹ 2 o a feasible for circuits which are fifth order and higher 0 oscillators. This procedure is essentially a subset of the Third Order Circuits Routh test, because the first two rows of the Routh array will + 3 ) 2 ) ) correspond to N(jωo)REAL and N(jωo)IMAGINARY. If the N3(s) a0s a1s a2s a3 ω characteristic equation N(s) = j ο = 0, the poles of the Let s = jωο be the frequency at which N3(s) = 0, and arrange characteristic equation will be on the imaginary axis at ±jωο the equation into its real and imaginary parts: with an oscillation frequency of ωο. The Method II w + w2 ) ) w w2 ) + procedure is shown below for second and third order N3(j o) (–a1 o a3) j o(–a0 o a2) 0 oscillators [13]. Thus, the real and imaginary parts equal zero when:

w2 ) + w2 ) + Second–Order Circuits –a1 o a3 0 and –a0 o a2 0 + 2 ) ) + ǒ 2 ) a1 ) a2Ǔ 2 N2(s) a0s a1s a2 a0 s s Solving the above equations for wo gives: a0 a0

2 a3 a2 wo + + a1 a0

Summary of Method II Equations

Oscillator Oscillation

Order N(s) Condition wo

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ + w + Ǹa2 N (s) + a s2 ) a s ) a a1 0 o

2nd 2 0 1 2 a0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á

a a

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ + w + Ǹ 3 + Ǹ 2 N (s) + a s3 ) a s2 ) a s ) a a1a2 a0a3 o

3rd 3 0 1 2 3 a1 a0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á Á Á Á

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Appendix III: Routh’s Stability Test where the coefficients b1, b2, b3, etc., are evaluated as Routh’s Stability Test [12] can be used to test the follows: characteristic equation to determine whether any of roots lie a1a2 * a0a3 a1a4 * a0a5 b1 + b2 + on the imaginary axis. Routh’s test consists of forming a a1 a1 coefficient array. Next, the procedure substitutes s = jωo for a a * a a s, and the summation of the row is set to zero. If the row b + 1 6 0 7 3 a equation produces a nontrivial solution for ωo, the procedure 1 is complete and the frequency of oscillation is equal to ωo. The evaluation of the b’s is continued until the remaining If the row equation does not yield an equation that can be terms are equal to zero. The same pattern of cross solved for ωo, the procedure continues with the next row in multiplying the coefficients of the two previous rows is the Routh array. This technique arranges the numerator of followed in evaluating the c’s, d’s, etc... the characteristic equation (i.e. denominator of the transfer equation) into the array listed below. b1a3 * b2a1 c1 + b1 T(s) + A + A + A 1 * LG D(s) N(Ds) ǒ Ǔ b1a5 * b3a1 D(Ds) c2 + b1 D + ) * ) * ) * N( s) a0sn a1sn 1 a2sn 2 a3sn 3 This process is continued until the n–th row has been ) ... ) an * 1s ) an completed. The Routh stability criterion states: 1. A necessary and sufficient condition for stability is AAA sn a0 a2 a4 an that the first column of the array does not contain AAA sign changes. sn–1 a1 a3 a5 an–1 AAA 2. The number of sign changes in the entries of the sn–2 b1 b2 b3 bn–2 AAA first column of the array is equal to the number of sn–3 c1 c2 c3 cn–3 roots in the right half s–plane. .... 3. If the first element in a row is zero, it is replaced by ... . ε, and the sign changes when ε → 0 are counted ... after completing the array. s0 f1 4. The poles are located in the right half plane or on the imaginary axis if all the elements in a row are zero.

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BIBLIOGRAPHY 7. Lindquist, C., Active Network Design with Signal 1. Baxter, L., “Capacitive Sensors Offer Numerous Filtering Applications, Steward and Sons, Long Advantages”, Electronic Design, January 26, 1998. Beach, 1977. 2. Celma, C., Martinez P., Carlosens, A., “Approach 8. Martinez, P., Aldea C. and Celma, S., “Approach to the Synthesis of Canonic RC–Active Oscillators to the Realization of State Variable Based Using CCII”, IEE Proc. Circuits, Devices and Oscillators”, IEEE International Conference on Systems, Vol. 141, No. 6, December 1994, pp. Electronics Circuits and Systems, Vol. 3, 1998, p. 493–497. 139–142. 3. Clayton, G. and Winder, Steve, Operational 9. Pease, Robert, “Bounding, Clamping Techniques Amplifiers (4th edition), Newness, Boston, 2000. Improve Circuit Performance,” EDN, Nov. 10, 4. Graeme, Jerald, Amplifier Applications of Op 1983. Amps, McGraw – Hill, N.Y., 1999 10. Sidorowicz, R. “An Abundance of Sinusoidal 5. Griffith, R., Vyne, R., Dotson, R., and Petty, T, RC–Oscillators”, Proc. IEE, Vol. 119, No. 3, “A 1–V BiCMOS Rail–to–Rail Amplifier with March 1972, pp. 283–293. n–Channel Depletion Mode Input State,” IEEE 11. Stata, Ray, “AN–357: Operational Integrators,” Journal of Solid–State Circuits, Vol. 32, No. 12, Analog Devices, Norwood, MA, 1967. Dec. 1997, pp. 2012 – 2022. 12. Truxal, J. Introductory System Engineering, 6. Lepkowski, J. and et. al, “Capacitive Pressure McGraw–Hill, N.Y., 1972. Transducer System”, U.S. Patent No. 4,987,782, 13. Van Valkenburg, M., Analog Filter Design, Issued Jan. 29, 1991. Saunders College Publishing, Fort Worth, 1992.

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