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Cdc@ Cyber 18 Processor with Mos Memory ,- I \ "'---/ 96768300 ) ('./ €: 2) CONTROL DATA r" . '" CO I\PO R<\TION ( ! '-.....--" 0 0 0 CDC@ CYBER 18 PROCESSOR C" / WITH MOS MEMORY 0 MACRO LEVEL 0 0 SYSTEM DESCRIPTION FUNCTIONAL DESCRIPTION OPERATING PROCEDURE r~ PROCESSOR INSTRUCTION DESCRIPTION " INTERRUPT SYSTEM 0 PROGRAM PROTECT I/O DEVICES 0 0 0 0 1& 0 0 (r---.., ) --....../ 0 HARDWARE REFERENCE MANUAL () '--....../ o LIST OF EFFECTIVE PAGES o New features', as well as changes, deletions, and additions to information in this manual, are indicated by bars in the margins or by a dot o near the page number if the entire page Is affected. A bar by the page number indicates pagination rather than content has changed. o PAGE REV PAGE REV PAGE REV PAGE REV PAGE ;' REV Cover -- c) Title P~ge -- ii B iii/iv B v/vi A o vii A viii A 1-1 thru 1-7 A o 2-1 thru 2-6 A 4-1 thru o 4-14 A 4-15 B 4-16 thru 4-29 A 5-1 A r 6-1 A 7-1 thru 7-4 A L A-I A A-2 A B-1 thru B-4 A C-l thru C-8 A Comment Sheetl Mailer B o Cover -- o o o o o 96768300 B iii/iv /' ''-. r-"" '-- ( '. '-- r\ C~ #I (' \...,--- {~ \ ....... __ .,.. r I. '---' (' \... " ( '., /' c c ( c (~. o PREFACE The micro-programmable processor emulates the 1700 Additional information on CDC software applicable to the family of computers. Readers of this document should be micro-programmable processor system can be found in the o familiar with the CDC ® 1700 Series computers and their following publications: associated hardware. The processor is upward-compatible o and has an enhanced instruction capability. Description Publication Number c~, 1700 Computer System Codes 60163500 Mass Storage Operating Syste!1l (MSOS) Version 5 96769400 Reference Manual MS FORTRAN Version 3A/B Reference Manual 60362000 CYBER 18 Processor with Core ~emory (Macro Level) ·88973400 o Reference Manual CYBER Cross Syste!1l Version 1 (under SCOPE) 88988800 o Micro Assembler Reference Manual CYBER Cross System Version 1 (under SCOPE) 88988900 Macro Assembler Reference Manual CYBER Cross System Version 1 (under NOS and NOS/BE) ·96836400 Micro Assembler Reference Manual CYBER Cross System Version 1 (under NOS and NOS/BE) 96836500 Macro Assembler Reference ~Anual TIMESHAttE Version 3 Reference Manmll 96768000 o Operational Diagnostic System (ODS) Reference iIt1anual 39452100 o o o o o o 96768300 A v/vi o /' '-.,- - c \ .... ~,." ... I"r', " I\. , (' \ • (' \,._.... (' ''----- (" C'" (" " () CONTENTS o I ¥ ,",.:i, ,.¥".; . l,. i.,LI, o 1. SYSTEM ·DESCRIPTION 1-1 Basic Instruction Set 4-1 Storage Reference 4-1 Functional Characteristics 1-1 Register Reference 4-3 o Physical Characteristics 1-1 In ter-Register 4-3 Major System Component Description 1-3 Skip 4-8 Micro Processor 1-3 Shift 4-8 Transform 1-3 Enhanced Macro Instructions 4-8 o Micro Memory 1-4 Enhanced Storage Reference 4-10 Main Memory (MOS) and Memory Field Reference 4-17 Interface 1-4 Enhanced Inter-Register 4-17 I/O-TrY Interface 1-5 Enhanced Skip 4-17 Exteranl I/O Interface 1-5 Decrement and Repeat 4-19 Miscellaneous Instructions 4-19 Auto-Data Transfer 4-24 o 2. FUNCTIONAL DESCRIPTION 2-1 Micro Processor 2-1 5. INTERRUPT SYSTEM 5-1 Transform and Transform Module 2-1 ALU and Data Transfer Organization 2-1 Interrupt Trap Locations 5-1 o Main Memory 2-4 Mask Register 5-1 Main Memory Configuration 2-4 Priority 5-1 I/O-TrY Module 2-5 Internal Interrupts 5-2 o Breakpoint Panel/Breakpoint Controller 2-6 Operation 5-2 3. OPERATING PROCEDURE 3-1 6. PROGRAM PROTECT 6-1 Startup 3-1 Read-Only Page Protection 6-1 Emulator or Macro-Program Deadstart 3-1 Program Protect Bit Protection 6-1 Shutdown 3-1 Program Protect Violations 6-1 System Failure 3-1 Set/Clear Program Protect Bit 6-1 c MSOS Autoload 3-1 Bounds Register Operation 6-2 Operator Interface 3-1 Storage Parity Errors as Related to Program Function Control Register 3-1 Protection 6-2 Auto-Display 3-4 Programming Requirements 6-2 Panel Interface Control Commands 3-4 Peripheral Equipment Protection 6-2 Panel/Program Mode Commands 3-6 I/O Operations 3-6 7. I/O DEVICES 7-1 4. PROCESSOR MAIN INSTRUCTION Panel/Program Device 7-1 DESCRIPTION 4-1 Director Function (1) 7-1 Director Status (2) 7-3 o Instruction Format 4-1 Real-Time Clock 7-3 Basic Instruction Set 4-1 o APPENDIXES A Glossary A-I C Instruction Execution Times C-l o B Instruction Summary B-1 FIGURES 1-1 Digital Processor Organizations 1-4 2-2 Detailed Block Diagram of Enhanced o 1-2 Standard Processor Chassis 1-4 Processor 2-2 1-3 Typical Processor Printed Wiring Assembly 1-5 2-3 Main Memory Configuration 2-5 1-4 Standard Chassis Layout (Printed Wiring 2-4 Major I/O-TrY Signal Flow Paths 2-5 Assembly Placement) 1-6 4-1 LRG Instruction 4-22 o 1-5 Processor Functional Block Diagram 1-7 4-2 SRG Instruction 4-22 o 2-1 System Block Diagram 2-1 o 96768300 A vii o \ " TABLES c 1-1 Processor General Characteristics 1-2 4-9 Enhanced Storage Reference Instructions 4-14 ~ 2-1 Mask Register/Interrupt Addresses 2-'4 4-10 Field Reference Instructions 4-18 I 3-1 Function Control Register (FCR) 3-2 4-11 Enhanced Skip Instructions 4-18 \ ........... 3-2 Display Code Definitions 3-3 4-12 Miscellaneous Enhanced Instructions 4-20 3-3 Processor/1700 Register Correspondenc~ 3-5 4-13 ADT Table for a Single A/Q Device 4-26 4-1 Storage Reference Instruction Addressing 4-2 4-14 ADT Table for Multiple A/Q Devices 4-26 4-2 Storage Reference Instructions 4-4 4-15 ADT Table for the Clock 4-27 4-3 Register Reference Instructions 4-5 4-16 ADT Table for Single or Multiple 4-4 Inter-Register Instructions 4-7 M05 Devices 4-28 4-5 Inter-Register Instruction Truth Table 4-9 5-1 Interrupt State Definitions 5-1 4-6 Skip Instructions 4-9 7-1 Standard Equipment/lnterrupt Assignments 4-7 Shift Instructions 4-10 for CYBER 18-10/20/30 Timeshare 7-2 4-8 Enhanced Storage Reference Instruction Addresses 4-12 \ ..... " .-'" "- ,f'" , \', (~ ...... (" .......- r \..... .. -- (' "- ...' .. (' '....... " - (' \, C C' viii 96768300 A C () SYSTEM DESCRIPTION 1 The 1700 enhanced processor is a special configuration of programs (called macro instructions). The multilevel proc­ the CDC micro-programmable processor family of parallel essor differs from the conventional processor, as shown in mode, stored program, digital processors. It is dedicated to figure 1-1. Processor operation is controlled by a micro o perform as a 1700-compatible digital computer. The program in micro memory •. The micro program reads 1700 processor uses micro programming to execute the basic 1700 macro instructions from main memory and decodes. them for instruction repertoire plus additional enhanced instructions. execution in the micro processor. The micro memory is several times faster than the main memory. The transform o This manual describes the basic, as well as the optional, aids in decoding and program execution. Therefore, the characteristics of the processor. It covers the hardware, processor uses special micro-programming techniques to general operating procedures, and processor instruction emulate an enhanced 1700 system for lower cost, smaller repertoire. size,. and overall better performance. The basic processor configuration consists of: PHYSICAL CHARACTERISTICS o • Micro processor with 1700 transform The processor is modularly designed with standard TTL MSI • Micro memory (read-only memory) components and commercial construction. • Main memory (MOS) The standard chassis, shown in figure 1-2, is 18.5 in. (46.99 o cm) high by 17.5 in. (44.79 cm) wide by 12 in. (30.48 cm) • Input/output interface deep. The chassis includes cooling fans and a front cover panel. The standard chassis back panel has the input/output • Power supply wiring for the 1700 A/Q and 1700 A/Q-DMA. However, it o may also contain specialized input/output for the user. Various standard options, such as a card reader and a line Wiring details are included in the system wirelist provided printer, are available for the CYBER 18 Computer System. with the unit. The user may also use the micro memory and input/output to perform nonstandard 1700 functions to achieve even greater Power requirements for the processor vary with the user's flexibility with the processor. application. Power supplies of ±5 and ±12 volts are included in a separate chassis. Physical dimensions for the The MOS main memory differs from core main memory in power supply chassis are 8.75 in. (22.22 cm) high by 17.5 in. operation. Although all core memory instructions can be (44.79 cm) wide by 16.0 in. (40.64 cm) deep. Processor input used with MOS memory, gdditional instructions are available power is 120 V ac, 50 or 60 Hz. for MOS memory only. Page mode memory instructions o permit up to 512K bytes to be accessed. Page mode A typical processor printed wiring assembly, shown in figure addressing is discussed in section 2 under Main Memory 1-3, is 11 by 14 in. (27.94 by 35.56 cm) and has 204 Configuration. Page register loading and statusing instruc­ input/output contracts. tions begin in the section entitled Miscellaneous Instructions in section 4. The processor chassis has a prewired location for an optional breakpoint panel interface card. The breakpoint panel is a In addition, the MOS main memory is optionally available 16-in.
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