CYBER 18 COMPUTER SYSTEMS CONTR.OL DATA Corrori\Tlon

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CYBER 18 COMPUTER SYSTEMS CONTR.OL DATA CORrORi\TlON

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l j REVISION RECORD r REVISION DESCRIPTION 01 Preliminary edition released. LJ (3/76) 02 Manual updated. r (4/76) L.-" A Manual,updated and released. (2/77) r L_J

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Address comments concerning this r- manual to: l_ • Control Data Corporation r Publications and Graphics Division 4455 Eastgate Mall "'- © 1976, 1977 by Control Data Corporation La Jolla, California 92037 or use Comment Sheet in the back of LJ Printed in the United States of America this manual. rl

l_J c LIST OF EFFECTIVE PAGES

New features, as well as changes, deletions, and additions to information in this manual, are indicated by bars in the margins or by a dot near the page number if the entire page is affected. A bar by the page number indicates pagination rather than content has changed.

PAGE REV PAGE REV PAGE REV PAGE REV PAGE REV -- Cover -- o Title -- ii, iii A iv blank v thru viii A c 1-1 thru 1-3 A 2-1 thru 2-6 A 3-1 thru 3-3 A 4-1, 4-2 . A 5-1 thru 5-23 A 6-1 thru 6-5 A 7-1 thru 7-12 A A-I thru A-8 A c Comment sheet A Envelope -- Back cover --

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1 1 CYBER 18 1-1 Basic Instruction Set 5-6 Storage Reference 5-6 LJ 2. CYBER 18 SOFTWARE PRODUCTS 2-1 Register Reference 5-9 Inter.:.. Re gister 5-9 Operating Systems 2-1 Skip 5-9 Mass Storage Operating System (MSOS 5) 2-1 Shift 5-9 J Minimum Operating System (RTOS 3) 2-2 Enhanced Instructions 5-9 Languages 2-3 Enhanced Storage Reference 5'10 Macro Assembler 2-3 rl Field Reference 5-14 Cross Assembler (CLASS) 2-3 Enhanced Inter-Register 5-14 -..J Micro Assembler 2-3 Enhanced Skip 5-14 FORTRAN 2-3 Decrement and Repeat 5'-14 1""1 PASCAL 2-5 Miscellaneous 5-14 BASIC 2-6 u Interrupt System 5-17 RPGII 2-6 Interrupt Trap Locations 5-17 Mask Register 5-17 3 APPLICATION SOFTWARE PRODUCTS 3-1 Priority . 5-17 C TIMESHARE 3 3-1 Internal Interrupts 5-17 Manufacturing Industry Accounting System 3-1 Operation 5-17 rl Interactive Terminal-Oriented System 3-2 Program Protect 5-19

I Executive 3-2 Program Protect Violations 5-19 --..J Terminal Handler 3-2 Storage Parity Errors Related to File/Data Manager 3-2 Program Protection 5-19 Text Editor 3-2 Set/Clear Program Protect Bit 5-19 [=:J Terminal File Utilities 3-3 Programming Requirements 5-19 Peripheral Equipment Pro tection 5-19 4 CYBER 18-05 BATCH TERMINAL 4-1 Input/Output 5-20 ~ Auto-Data Transfer 5-21 LJ Model Description 4-1 CYBER 18-05 Batch Terminal Controller 4-1 6 CYBER 18-20, 18-30 TIMESHARE Batch Terminal Controlware 4-1 COMPUTER CHARACTERISTICS 6-1 ~ CDC 200 User Terminal Emulation 4-1 w mM 2780 Emulation 4-2 Model Descriptions 5-1 IBM 3780 Emulation 4-2 CYBER 18-20 Processor 6-1 r-l 1870-1 512 Instruction l\-licro Memory 6-2 5 CYBER 18-10M COMPUTER 1870-2 2-48 Instruction Micro Memory 6-3 ...J CHARACTERISTICS 5-1 1882-16 MOS Main Memory Storage 6-3 1882-32 MOS Main Memory Storage 6-3 Model Descriptions 5-1 1874-1 ECC MOS Array, 192K Bytes 6-3 '-1 CYBER 18-10M Processor 5-1 Main Memory 6-3 1870-1 512 Instruction Micro Memory 5-1 --..I Central Processor 6-3 1870-2 2048 Instruction Micro Memory 5-1 Macro Instruction Set 6-3 1882-16 MOS Main Memory Storage 5-1 ~1 Micro Instruction Formats 6-4 1882-32 MOS Main Memory Storage 5-1 ,~ Central Processor 5-1 7 ST ANDARD PERIPHERALS 7-1 Arithmetic/Logical Unit Data Transfer 5-3 --1. Transforms 5-5 1811-1 Console Display 7-1 I/O-TTY Module 5-5 1811-2 Operators Console 7-1 ~j CYBER 18-10M Instruction Description 5-6 1828-1 Card Reader/Line Printer Controller 7-1 Instruction Format 5-6 1828-2 Card Reader/Line Printer Controller/ I Communication Line Adapter 7-2

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('- 1829-30 Card Reader 7-2 1860-1 Magnetic Tape Subsystem 7-6 \ ..... ~ 1829-60 Card Reader 7-2 1860-72 Magnetic Tape Transport 7-6 1827-2 Impact Printer 7-2 1860-2 Dual Magnetic Tape Subsystem 7-6 l. .... J 1827-30/31 Line Printer 7-3 1860-3 Magnetic Tape Subsystem 7-6 1827-60 Line Printer 7-3 1860-92 Magnetic Tape Transport 7-6 1833-4 Cartridge Disk Controller 7-3 1860-4 Dual Magnetic Tape Subsystem 7-7 T' 1866-12 Cartridge Disk Drive 7-4 1860-5 Magnetic Tape Subsystem 7-7 L., 1866-14 Cartridge Disk Drive 7-4 1860-95 Magnetic Tape Transport 7-7 1833-1 Storage Module Drive Interface 7-4 1860-6 Dual Magnetic Tape Subsystem 7-8 r--- 1833-2 Storage Module Drive Interface - 1843-1 Communication Line Adapter 7-8 Dual CPU 7-4 1843-2 Eight-Channel Communication Line l_J 1833-3 Storage Module Drive Control Unit 7-4 Adapter 7-8 1867-10 Storage Module Drive 7-4 1850-1 1500 Series Equipment Adapter 7-8 r.;.. 1867-20 Storage Module Drive 7-5 1862-1 Paper Tape Read/Punch Controller 7-8 1833-5 Flexible Disk Drive Controller 7-5 CYBER 18 Configurator 7-9 L, 1865 Flexible Disk Drive 7-5 r- LJ

APPENDIX r-

l-l A MACRO INSTRUCTION EXECUTION TIMES A-I , -.

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FIGURES /'_. 1\, .._l 1-1 CYBER 18 Series Product Family 1-1 7-4 1827 -7 Impact Printer 7-3 2-1 CYBER 18 Mass Storage Operating 7-5 1827-30 Line Printer 7-3 r-- System (MSOS 5) 2-1 7-6 1827-60 Line Printer 7-3 2-2 CYBER 18 Mass Storage FORTRAN 2-4 7-7 1866 Cartridge Disk Drive 7-4 l._' 4-1 Typical CYBER 18-05 Configuration 4-2 7-8 1867 Storage Module Drive 7-5 5-1 Detailed Block Diagram of CYBER 18-10M 7-9 1865 Flexible Disk Drive 7-5 r-~ Processor 5-2 7-10 1860-1 Magnetic Tape Subsystem 7-6 L.J 5-2 Typical CYBER IS-10M Configuration 5-3 7-11 1860-4 Dual Magnetic Tape Subsystem 7-7 6-1 Typical CYBER 18-20 Configuration 6-1 7-12 1860-5 Magnetic Tape Subsystem 7-7 r'-' 6-2 Typical CYBER 18-30 Timeshare 7-13 1860-6 Dual Magnetic Tape Subsystem 7-8 Configuration 6-2 7-14 CYBER 18-05 Configurator 7-9 l. 6-3 Micro Instruction Formats 6-4 7-15 CYBER 18-10M Configurator 7-10 7-1 1811-1 Console Display 7-1 7-16 CYBER 18-20 Configurator 7-11 r 7-2 1811-2 Operators Console 7-1 7-17 CYBER 18-30 Timeshare Configurator 7-12 7-3 1829-30 Card Reader 7-2 L.

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ro- 1-1 CYBER 18 Product Line General 5-3 Enhanced Storage Reference Instruction l __ Characteristics 1-2 Addresses 5-11 5-1 Mask Register/Interrupt Addresses 5-5 5-4 Interrupt State Definitions 5-17 5-2 Storage Reference Instruction Addressing 5-8 r--- L. .-' - - \.. vi 96767850 A \.-. r

l._) 0 r-1 PREFACE I

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This manual provides general information on the CDC@ product family (that is, hardware, software, mainten C CYBER 18 family of small computer systems. More ance, education, and customer support) are available detailed information on all aspects of the CYBER 18 through your local Control Data sales representative. n l.7J n LJ r-l Iw 0 0 [:) 11 Li n lj rl lJ rJ ,--1 -1 ] l -.J ~', ( ) ./

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CYBER 18 SYSTEM

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The CYBER 18 is a series of general-purpose micro reducing the amount of irregular logic in a processor J programmable processors designed for application to a and allowing greater use of MSI/LSI circuitry. This broad range of requirements. One basic hardware de approach allows high-volume production of nearly iden sign, made up of modular elements, serves a variety of tical processors that can be tuned to a specific applica 'l functions, permitting a high degree of standardization. tion by including a selected instruction set in the micro ,.J memory, thus specifying a different virtual machine. The operation of the CYBER 18 is controlled by a The micro-programming technology provides the flexi rl "micro" program in semiconductor memory, referred bility to offer new architectures for general-purpose to as micro memory. The micro program reads macro computers with emulation capabilities and for controllers U instructions from main memory and decodes them for where emulation is not an important factor. execution in the micro processor. The semiconductor r· j memory, which is several times faster than core mem Growth is a most important feature of the CYBER 18. ory, executes several micro instructions during a Growth is available via the micro-code expansion capa u single main memory cycle. In the CYBER 18, special bility of the micro processor. New functions can be micro-programming techniques are used to emulate an added as applications require, or operating system func r', enhanced CDC 1700 system for lower cost, smaller size, tions can be included as part of the micro sequence to U and equal or better speed. improve overall system performance. This growth potential is available without sacrifice of hardware com Micro programming provides a number of long-range monality, so a common logistic base is maintained. benefits. In contrast to the conventional computer, whose C control is an irregular assembly of specially designed Figure 1-1 presents an overall view of the CYBER 18 logic functions, the micro-programmed machine embeds hardware and software products. [J the control logic in a high-speed read-only memory,

CYBER PRODUC:r CHARACTER ISTICS n I .~8-3l)ROCESSOR L • TO BYTES, 18-BIT MOS 18-30 • ERIPHERAL CAPABILITY ~ • ENHANCED 1700 MSOS SOFTWARE • TYPICAL APPLICATION: EDUCATIONAL TIMESHARE 0 t • 18-20 CPU o 32K TO 256K BYTES, 18-BIT MOS rl 18-20 o FULL PERIPHERAL CAPABILITY L) o ENHANCED 1700 MSOS SOFTWARE t o TYPICAL APPLICATION: ACCOUNTING AND MANAGEMENT CONTROL r-l o 18-10M CPU o 32K TO 128K BYTES, 18-BIT MOS L) 18-10M o FULL PERIPHERAL CAPABILITY o 1700 MSOS/RTOS SOFTWARE o TYPICAL APPLICATIONS: INDUSTRIAL CONTROL SYSTEM n r ENTRY BUSINESS SYSTEM U o 18-05 CPU o 16K BYTES, 18-BIT CORE 18-05 o LIMITED PERIPHERALS o 200 UT, 2780, AND 3780 CONTROLWARE 0 o TYPICAL APPLICATION: BATCH SYSTEM r Figure 1-1. CYBER 18 Series Product Family '--' -, ) r

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(' I TABLE 1-1. CYBER 18 PRODUCT LINE GENERAL CHARACTERISTICS \.

Basic Configuration l- Processor r-' Type General-purpose, micro-programmable digital processor Organization Register oriented or file oriented. L.I Word length 16 bits r- Micro-instruction word 32-bit format; two micro instructions per micro-memory L, address Micro-memory type Semiconductor read/write memory (RAM) and/or read r' only memory (ROM) L, Micro-memory size 512 words in 64-bit increments (on transform); maximum of 4,096 additional words available. --- Micro-memory access time 70 nanoseconds l_1 Arithmetic Binary with dynamic selection of ones or twos complement mode r· Up to four parallel unrelated operations are possible in , - ' one micro instruction ,-.. Macro Memory Requirement Variable, according to application Type Core memory: Available in 16K byte stacks, with a maximum of 32K bytes (CYBER 18-05) ( " '" MOS memory: A vaiIable in 32K or 64K byte stacks, with a max imum of 128K bytes (CYBER 18-10M), 256K bytes r' (CYBER 18-20\. or 512K bytes (CYBER 18-30)

, '- Parity and protect bits are available in the standard stack. ,....., Memory speed 750 nanoseconds average cycle

Input/Output (I/O) l,~j Interfaces Display terminal (RS232-C compatible) r-' Mechanical Construction RETMA 19-inch, rack mountable '-' Dimensions Logic Chassis: r-'

Height - 18.5 inches (47 cm) \_.1 Width - 17.5 inches (44.5 cm) Depth - 16.0 inches (40.64 cm) r Power Supply Chassis: L. Height - 8.75 inches (22.25 cm) ,.-.. Width - 17. 5 inches (44. 5 cm) Depth - 16.0 inches (40.64 cm) Weight Logic Chassis: 40 pounds (approximately) (18 kg) Power Supply: 50 pounds (approximately) (45 kg) r-

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\ I\,_.J -) TABLE 1-1. CYBER 18 PRODUCT LINE GENERAL CHARACTERISTICS (Continued)

J Basic Configuration (Continued) -1 Mechanical (Continued) J Input power 115 volts, 50/60 Hz Miscellaneous Features l Real-time clock .-l Auto-data transfer Direct memory access (CYBER 18-10M, 18-20, 18-30) l -.J

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1 ~-; -1 J -1 CYBER 18 SOFTWARE PRODUCTS 2

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l The hardware of the CYBER 18 product set is comple The component parts of MSOS 5 are shown in figure 2-1. J mented with an extensive set of software products, com prising operating systems (including program debugging MSOS 5 is a multiprogramming system designed to sup l and development aids), micro and macro assemblers, port a variety of applications requiring dedicated system I application-oriented software, and FORTRAN, BASIC, utilization, batch processing, and program checkout .-l RPG II, and PASCAL compilers. features in a real-time environment. l MSOS 5 regulates all multiprogramming on the basis of the priority level assigned to a particular operation, -.J OPERATING SYSTEMS whether the operation is program execution or input/ output. The system queues requests for I/O data trans --1 ------mission and program execution by priority level, with no -l MASS STORAGE OPERATING SYSTEM (MSOS 5) restric'tion on the number of requests that may be queued at a given time. The program task with the highest priority level is selected for execution. It remains in '-1 This operating system is the most recent in the develop ment of a sequence of mass-storage-based operating execution until completed, unless a higher priority level u systems for the 1700, 1714, 1774, and 1784 computers. interrupt is scheduled. The lower priority level task is' It takes advantage of the enhanced instructions, addition then suspended until the higher priority interrupt task is completed. ~ al registers, and firmware capabilities of the CYBER 18 Series of computers. MSOS 5 is designed for use on the LJ CYBER 18-10M and 18-20, having random-access mass memory. ,..-, _.... \

.....-/ MSOS PROTECTED PROGRAMS (FOREGROUND)

MONITOR :l CONSTANTS/TABLES REQUEST PROCESSORS ~ I/O DEVICE MANAGERS INTERRUPT HANDLERS ,.-., DISPATCHER CORE MANAGERS ~ I I I I I I ---I ---,----, UTILITIES ON-LINE DIAGNOSTICS I PROTECTED ioN-LINE DEBUG JOB FILE SMALL COM PUT ER F ORTRAN 3.2 A/B USER rl SYSTEM CHECKOUT PROCESSOR MANAGER MAINTENANCE I MULTIPROGRAMMING IApPLICATIOr- L; ENGINEERING FILE MONITOR I P ACKAGE PROGRAMS I I r) I J I RECOVERY I LIBRARY lJ (DEBUGGING EDITING I AID) I - n MSOS UNPROTECTED PROGRAMS --I (BACKGROUND) L ____ -. J'u - I I I T T 1 I I I BATCH RELOCAT- BREAK- INSTALLA- COSY MICRO PROCESS- INPUT/ I FORTRAN ABLE POINT TION FILE (SOURCE AND ING OUTPUT I 3.2 A/B BINARY (DEBUGGING MAINTE- DATA MACRO UTILITIES COMPRES- COMPILER USER LOADER AID) NANCE ASSEMBLERS I 0 SION) BATCH I JOBS I ,(t Figure 2-1. CYBER 18 Mass Storage Operating System (MSOS 5)

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On interrupt, all eight registers of the CPU may be • The file manager is a general-purpose file manage stored by a single command, making possible a very ment package. It creates and maintains both se rapid change in the program environment as a result of quential and indexed files, and offers sequential, LI interrupt. indexed, and direct methods of record retrieval, as well as variations of these. The file manager may Sixteen hardware interrupts 'are utilized to maximize be used by protected and unprotected programs and input/output efficiency and to allow concurrent input/ is FORTRAN-callable. output and computation. • The on-line diagnostics, in an on-linej real-time mode, have the capability of running peripheral The program protect feature of the hardware segregates hardware diagnostics, which facilitates problem central memory into two functional entities - protected detection and preventive maintenance. memory and unprotected memory. The minimum hardware CYBER 18-20 requirements for • Protected memory (the foreground) is reserved MSOS 5 are: for executing all parts of the operating monitor and the user's on-line high priority applications • Computer with 32K bytes main memory programs. • Console device (teletypewriter, CRT) ) • Unprotected memory (the background) is used for execution of batch job processing and program • Input device (pa er tape, cards, magnetic tape) checkout at low priority levels. MSOS 5 has the Output device (paper tape, cards, magnetic tap capability to swap (move) the contents of unpro • tected memory to mass storage and to make the • 1, 024, 000 bytes mass storage me!llor,V area protected me-mory for use by foreground programs.

MSOS 5 is extremely modular in design and provides the MIN IMUM OPERATING SYSTEM (RTOS 3) user considerable flexibility to perform on-line system modification and update. The minimum operating system for the CYBER 18-10M is the Real-Time Operating System Version 3 (RTOS 3). It The MSOS 5 system features the following main capa provides executive software and appropriate development bilities: tools in a minimum of main memory, without depend ence on random-access mass memory. • The monitor is the real-time executive for MSOS 5. It serves as the interface between the system pro RTOS 3 includes a monitor that is a compatible subset of grams and the peripheral hardware via input/ MSOS 5. The monitor requires less than 3000 b~es output drivers. It is highly modular and may be of main memory, exclusive of peripheral-device drivers parameterized for a large variety of hardware and and optional features. Up to 16 program priority levels software configurations. It contains request proc are provided, and input/output requests are also proc essors to allow for input/output, program schedul essed on a priority basis. The monitor is itself re ing, memory allocation, and background operation. entrant and minimizes the time for which interrupts are MSOS 5 provides for the execution of instructions inhibited so as to provide very fast interrupt response in 128K bytes of contiguous memory, with the times. It contains a request processor to handle the ability to access data in up to 512K bytes of following standard requests: memory. READ • The job processor is responsible for monitoring WRITE ,-. background programs running in unprotected FREAD memory. Interface is provided for batch stream FWRITE unattended jobs or for interactive operator SCHDLE controlled jobs. The job processor controls the INDm r- FORTRAN compiler, the macro assember, and EXIT numerous background utility functions.

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Optional request processors are available to process the functions of the CYBER 18 macro assembler, pro requests for: ducing listing output and relocatable binary output for input by the CYBER 18 relocatable binary loader. TIMER MOTION n 'SPACE u RELEASE MICRO ASSEMBLER CORE STATUS The micro assembler provides the ability for the user to rl EBCDIC I ' develop his own micro program using appropriate alpha U betic and numeric designations of operations to be per Other optional features include a protect processor for formed. The micro assembler provides for cross micro use while debugging ':lser-written programs, a core allo assembly on large CYBER Series computer (CYBER 170/ cator, an alternate device handler and a diagnostic timer. 70/6000/7000). The micro assembler output is in binary relocatable format, compatible with. the loader of the All MSOS 5 drivers are compatible with RTOS 3. MSOS 5 or RTOS 3 operating system.

An RTOS 3 system with a minimum of 16K bytes of main memory supports the Assembler, which is compatible with the MSOS assembler (except that macros may not FORTRAN be used). Previously compiled FORTRAN progralU~ may o be run under RTOS 3; however, FORTRAN programs There are two FORTRAN compilers for the CYBER 18 may not be compiled under RTOS 3. Series. They provide the same run-time capability but differ in compilation speed and main memory require The minimum hardware requirements for RTOS 3 are: ments. The essential components and modes of opera tion are shown in figure 2-2. • CYBER 18-10M with 16K bytes of main memory • Console device (conversational display The language is a subset of ANSI FORTRAN, so, most terminal) ANSI FORTRAN programs can be compiled with few changes; basic FORTRAN programs are immediately • Input device (card reader, magnetic tape) compiled. • Output device (magnetic tape) - optional As a product-set member of the CYBER 18 MSOS 5, Mass storage FORTRAN offers a variety of compile time options (such as run-anywhere code) and run-time ~l packages. I LANGUAGES W CYBER 18 Mass storage FORTRAN is a high-level language and, as such, is concise and provides data MACRO ASSEMBLER structuring capabilities and I/O independence. Increased program modularity and source code clarity also results. The macro assembler for the CYBER 18 Series provides a comprehensive instruction set that makes full use of The wide range of FORTRAN system configurations the CPU capabilities and includes the ability to define, allows optimum usage of available storage resources for execute, and maintain a library of macro commands. A compilation and foreground/background execution. minimum system for execution of the macro assembler (under RTOS 3) requires 16K bytes of main memory. Five basic elements comprise 1700 Mass storage FOR TRAN Version 3 - the A and B variations of the com piler and three run-time packages: re-entrant ENCODE/ DECODE, non-re-entrant ENCODE/DECODE, and FOR CROSS ASSEMBLER (CLASS) TRAN I/O.

The CLASS cross assembler is designed for use on The A variant compiler, having a larger number of CYBER 170/70/6000/7000 computers. It duplicates all --1 overlays than the B variant, requires more compilation

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,/"'" i \,- FORTRAN NON-RE-ENTRAN'I OR I/O L, ENCODE/DECODE SOURCE RUN-TIME CODE r LJ

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r-' FOREGROUND RELOCATABLE LOADER EXECUTION L· OBJECT CODE

RE-ENTRANT ENCODE/ DECODE

Figure 2-2. CYBER 18 Mass Storage FORTRAN C~ time but less core memory (16K vs. 32K bytes). The • ASCII - ASCII to hexadecimal source format for both variants is the same, while the DECHEX - Decimal ASCII to hexadecimal r--. object code produced by the two variants is nearly • identical. • AFORM - Packed ASCII to unpacked ASCII (left- L, justified blank-filled) The re-entrant ENCODE/DECODE run-time package runs I RFORM - Packed ASCII to individual ASCII char- in the foregroUnd (protected core) and is the FORTRAN • acters (right justified, zero filled) l_J multiprogramming interface. It allows FORTRAN rou tines to execute at multiple levels without interference, • FLOATG - Floating-point variable to ASCII and provides a greatly enhanced interface capability to I the MSOS monitor. Monitor requests that are provided include Read/Write L, (extensive I/O capabilities), Scheduler/Timer (causes Although the formatted I/O is nonstandard, all I/O capa execution of another routine, optionally, after a specified r'- bilities are provided through the monitor and ENCODE/ time interval). Dispatcher (discontinue execution with-

I DECODE package calls. out terminating), and Release (return core allocated for l-. execution). Given a list of variables and a FORMAT statement, EN r-' CODE and DECODE translate the variables between 10K bytes are required for the foreground ENCODE/DE- internal hexadecimal format and ASCII. The other for CODE package. If double-precision arithmetic is used, l.. matting routines do not use FORMAT statements, but an additional 5K bytes are required. translate either integer or floating-point variables. f"-' These formatting routines are as follows: Foreground programs can be checked out in the back- L. ground (unprotected core) via the (identical) interface • HEXASC - Hexadecimal to ASCn provided by the non-re-entrant ENCODE/DECODE pack- ,r-" age, without interfering with the protected programs, • HEXDEC - Hexadecimal to decimal ASCII including the monitor. ( '-

l._. 2-4 96767850 A r L, l J r I -~ The FORTRAN I/O run-time package, which also runs in Extensions to the ANSI standard are as follows: -, the background, provides standard FORTRAN I/O capa J bilities more extensive than those of the ENCODE/DE • ASSEM - Allows inclusion of assembler state CODE packages. ments in FORTRAN source code BYTE - Assigns a name to a b.it field within an· The efficiency of the produced object code is mainly due • l integer variable or array J to the compiler's extensive optimizing features, which include: • DATA - Enhanced to allow use of implied DO-loop -1 to initialize arrays • Common arithmetic subexpressions, including sub RELATIVE - Specifies externals to be linked via j scripts, are recognized within and between expres • relative addressing sions and are computed only once • SIGNED BYTE - Identical to BYTE but the high --I Index registers are optimally assigned • order bit of the field is interpreted as a sign bit ~ • One-word relative addressing is used wherever possible The minimum main memory requirement for execution of the compiler (A or B version) on a CYBER 18-10M or I Relative addressing is maximized by appropriate • a CYBER 18-20 is 64K bytes • ...) storage allocation: some constants, for instance, are duplicated, and some arrays are inserted be tween code segments J • Simple FORTRAN functions such as AND and lABS PASCAL are provided in-line PASCAL is a compiler patterned after ALGOL 60. It is IF statements are extensively analyzed, such as a I • available as a cross compiler executing on large CYBER transfer made to the next statement or to a GO TO U computers (170/70/6000/7000), producing relocatable • Expressions in logical IFs are analyzed for the binary output for loading and execution by a CYBER 18 -, method of least computation machine. ) • Arithmetic expressions are analyzed to minimize "-"' PASCAL is a high-level, algorithmic type language re code production and execution time taining the attractive features of ALGOL 60. Thus, the n • Division by a real constant generates code for grammar of PASCAL is essentially context-free. Its multiplication by the constant's reciprocal syntax is unambiguous and simple to define, properties u that are greatly appreciated by programmers. The • Integer multiplication or division by a (constant) block-oriented structure of ALGOL 60, which is particu power of 2 is accomplished by shifting larly adaptable to the use of structured programming techniques, has also been preserved. 0 The following standard statements are recognizable by the FORTRAN compiler: The basic constituents of a PASCAL program are state rl ments and declarations or definitions. Statements indi I ASSIGN FUNCTION cate the various actions that are to be carried out by a w GO TO BACKSPACE program, and declarations/definitions describe the BLOCK DATA INTEGER meaning attached to the various identifiers used in a r·1 CALL IF program. L-, COMMON OPEN CONTINUE PAUSE PASCAL provides some noteworthy extensions to the DIMENSION PROGRAM capabilities of ALGOL 60. Within the domain of state r'l DO READ ment constructs, PASCAL supports a broad variety of w DOUBLE REAL structured statements. Thus, repetitive or conditional PRECISION RETURN actions may be coded in a concise and natural ma.n.ner. REWIND END More significantly, the ALGOL 60 deficit in the area of ENDFILE SIGN structured data has been remedied by the introduction of SUBROUTINE 0 EQUIVALENCE a set of data structuring techniques. Another feature of EXTERNAL STOP PASCAL is the provision of pointer-type variables, ,rl FORMAT WRITE I 1'--.1 r;J

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[ll U along with the ability to dynamically and explicitly allo RPG II cate storage. These features extend the range of appli cability of PASCAL, as compared with that of its more The Report Program Generator II (RPG II) compiler pro L. traditional ancestor. vided as a member of the CYBER 18 software product set is closely compatible with IBM System' 3/RPG II at PASCAL programs compiled on a CYBER 170/70/6000/ the source language level. Differences from the System 7000 class of machine may be executed in a CYBER 18- 3/RPG II primarily reflect differences in peripheral L. 10 under RTOS 3 with a minimum memory of 16K bytes. characteristics; the multifunction card reader, the dual tractor printer, bisync communication, card reader stacker selection, and inquiry mode are not supported by CYBER18 RPG ll. L, BASIC RPG II provides a simple language by which a user can: The BASIC compiler provided as a component of the CYBER 18 software product. set meets the requirements • Easily describe the formats, sources of input data, L. of the proposed ANSI standard for minimal BASIC and destinations of output data (ANSI -XJ32), and provides the following additional capabilities: • - • Execute simple procedural programs with both conditional and unconditional statements L· Additional string manipulation functions • Describe the formats and sources of data in an • r--. • Matrix operations external file system Input/output formatting • CYBER 18 RPG II requires a CYBER 18-10M or 18-20 • Binary and ASCll files for compilation umer MSOS 5. • Sequential and random (indexed) file accessing

The BASIC compiler is executed interactively under TIMESHARE 3 on a CYBER 18-30. (-- \.,

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2-6 96767850 A L,' r LJ APPLICATION SOFTWARE PRODUCTS 3

TIMESHARE 3 • CYBER 18-30, the timeshare processor with 128K n bytes and the communications processor with 64K u The TIMESHARE 3 system is designed to provide inter bytes of main memory active computer capability for up to 64 concurrent users, Asynchronous communications multiplexer, with together with communication with a remote large-scale • facilities for both dial-up and dedicated lines CYBER system (70/170/6000/7000). TIMESHARE 3 requires the dual processor of the CYBER 18-30, one • Cassette tapes on both CPUs processor handling user programs, the other providing Storage module with 25M byte capacity communication with a remote host machine and I/O for • local peripherals. TIMESHARE 3 operates under • Nine-track tape, card reader, and line printer on MSOS 5. the timeshare CPU

The capabilities and characteristics of TIMESHARE 3 Optional features include: o include: • Synchronous communication interface for host • Up to 64 concurrent users on dedicated or dial-up computer link lines o • Teletypewriter-compatible terminals Interactive execution of the BASIC compiler, with • Asynchronous communication line adapters line-by-line syntax checking • c • Log-in and sign-off procedures, with password security check • A text editor for manipulation of user program and MANUFACTURING INDUSTRY data files ACCOUNTING SYSTEM Simulation of a desk calculator, providing arithme • This application software for the CYBER 18 is designed tic operations witt a minimum accuracy of six to provide a broad range of business data processing significant digits capabilities for manufacturing and distribution industries. • A formula calculator, where the user enters the The application software is supplied in modular form, algebraic formula and, under prompting by the facilitating the matching of system capabilities to a computer, the values of independent variables particular customer's requirements. The modules of the system are: • A log of system events and file of system messages available to all terminal users • Order entry and invoice preparation Utility programs for use by the CYBER 18-30 oper • • Purchase orders and accounts payable ator for starting, stopping, and determining the status of the system, transmitting a message to all • Inventory control and physical inventory n user terminals, establishing passwords, dumping, • Routing LJ reloading, and auditing files. • Bill of materials • Ability to generate batch jobs at a remote terminal, for execution either by the CYBER 18-30 in batch • Material reqUirements planning mode or by the host processor (CYBER 170/70/ Accounts receivable 6000/7000). • • Payroll Minimum hardware requirements for TIMESHARE 3 are • General ledger provided by the CYBER 18-30 Timeshare configuration Sales analysis and include: •

96767850 3-1 .Il, U The Manufacturing Industry Accounting System operates Screen formatting and X-Y cursor positioning allow the on a CYBER 18-10M or 18-20, supporting up to 16 local user to reproduce his source data form. Data entry . terminals operating on different tasks concurrently. operations can be reduced to a simple fill-in-the-blanks operation. The cursor positioning corresponds to the Minimum hardware requirements -for the system are: automatic tabbing on a typewriter. • CYBER 18-10M processor with 64K bytes of main Corrections are made by backspaCing, instead of deletion memory (supporting two terminals), 96K bytes characters. f.or up to six terminals, and 128K bytes for more than six terminals. The handler supports variable operating modes: charac ter, line, and block. • Cartridge disk Y'ith 4.4M bytes of random-access mass storage

• Line printer FILE/DATA MANAGER • Terminals wi1h optional hard copy capability Features of the file/data manager include:

INTERA CTIVE TERM INA L-ORIENTED • Files with up to 16 million (224) records are SYSTEM - supported. The maximum record size is 32, 000 (215) bytes. This application system, designed for u.:;e with the manu • The packs and cartridge are removable. Disk facturing applications programs, runs under M..C:;OS 5. It packs are labeled and file description information consists of four major modules: is maintained on the same volume as its associated files. Executive • • Sequential, relative, and indexed sequential access • Terminal handler methods are supported. Indexed sequential file key lengths are IBM standard, 29-character length. • File/d3.ta manager The initial release supports four primary level • Text editor/terminal utilities • indexing keys so the user can select and sort file records with up to four different (not multilevel) keys; for example, a file of personnel records can be keyed by age, physical location, grade,. and sex. EXECUTIVE • Improved throughput is provided with techniques The executive controls execution of user jobs. It provides such as continuous file space allocation, optional each job with a time slice, then queues the job until the sector aligned records,· and mass memory overlap next execution. seek. Multiple users may access the same file because It controls the roll in/out of jobs to/from mass storage, • lockout is now at the record level typically when input/output is initiated. It also manages main and mass memory allocation to support multiple user job streams in main memory.

TEXT EDITOR The executive isolates users from system software for system integrity. It supports serially re-entrant inter The source language text editor allows the user to enter, preters for multiple user access to common programs. store, and retrieve text as a private or common file. Files may consist of:

TERMINAL HANDLER • RPG n programs The terminal handler provides the interface between the • FORTRAN or Assembler programs to be batch system and the terminal operators. processed at a later time

3-2 96767850 A ."',I .-J

", \. I \,-----,,' • Text and data files to be exchanged with a remote DEFINE Create a file on mass storage -, host processor STATUS Print the status of the specified file(s) • Other data or text the user wishes to keep on file RELOAD Reload a file onto mass storage from '!be text editor supports the following commands: a sequentlal device. l DUMP Dump a file from mass storage to a J FILES List the names of all files belonging sequential device to the user COpy Copy a file to another file GET Retrieve a file DELETE Delete a file and release storage SAVE Save a file space associated with it BATCH Submit a file for batch processing CLEAR Release all mass storage sJllce of PURGE Discard a file file(s) specified LIST List a file LIST Print the file to the standard list n device I ' AUTO Enter file create mode RENAME Rename a specific file U CLEAR Clear the working file COMMANDS List all file utility commands DELETE Delete the text line(s) EXIT Retum to the executive SEARCH Search for a text string MOUNT '!be specified volume is available to CHANGE Replace a text string the system MERGE Insert a named file into the text DISMOUNT '!be specified volume is no longer c currently being editing available to the system ALIGN Justifies text to RPG, FORTRAN, or SA VE Save the specified volume Assembler format RESTORE Restore the specified volume [) RESEQ Resequences line numbers LOAD Load the source data records to a rl file I I l....J PURGE Release all files whose expiration dates have been exceeded

TERMINAL FILE UTILITIES INPUT Change the command inputting device o to the one specified COMPRES Delete the records marked and copy A variety of utilities is available for the manipulation this file into its existing location of information files. '!bese utilities are available from the interactive terminals as well as unitlrecord equip OUTPlIT Change the output device to the one ment. The commands are: specified

HELP Print information about the command INIT Initialize the.volume on mass storage o

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l MODEL DESCRIPTION ·CDC 200 USER TERMINAL EMULATION J Following is a brief description of the standard unit. The CDC 200 User Terminal provides the following l Descriptions of the optional peripherals are included in features: section 7, Standard Peripherals. ~ • Operator selection of Hollerith 026 or 029 card formats. CDC 200 User Terminal synchronous communica CYBER 18-05 BATCH TERMINAL CONTROLLER • tion techniques, using modems conforming to RS232-C or CCITT-V24 specifications at rates The CYBER 18-05 batch terminal controller is a unit from 1200 to 9600 baud. that can accommodate up to 32,768 eight-bit bytes (one I protect and one parity bit for each two bytes) of core • Half-duplex communication with a host computer, ---- main memory with an effective read/write cycle time using a dedicated or dial-up line of 750 nanoseconds. The 18-05 emulates the basic as Compatibility with CDC CYBER 72, 73, 74, and well as an enhanced 1700 instruction set. Basic • 6000 Series computers using KRONOS with features are: hardware multiply/divide, 16 levels each EXPORT/IMPORT or SCOPE with INTERCOM. of micro and macro interrupts, auto-data transfer, a real-time clock, and deadstart facility from peripherals. • Compatibility with CDC 3000 Series computers The 18-05 supports only A/Q-type peripherals. It using MASTER with RESPOND-EXPORT/IMPORT, includes a cabinet, an operators panel, power supplies, MARS III, or MCS III an 1811-1 communications console, an I/O controller Operator selection of transmission-line code - for the 1811-1, an I/O controller for a card reader and • external or internal BCD or Ascn a line printer, a synchronous communications line adapter, and CDC 200 User Terminal batch controlware. • Display of operator-selected operating parameters on the CRT Feature options include: n • Automatic notification of line and terminal error u conditions on the CRT • 300 or 600 card-per-minutecard reader • Selection of input and output deVices (keyooard, • 300 or 600 line-per-minute line printer n magnetic tape, card reader, or line printer) ~ • IBM 2780 or 3780 terminal batch controlware • Off-line functions, providing for transfer of data between peripherals on the terminal I~ \ I U BATCH TERMINAL CONTROLWARE A selection card loaded with the controlware permits matching the controlware to the hardware configuration and to the operating modes required. \1 The CYBER 18-05 is a batch terminal with the ability to emulate a CDC 200 User Terminal or an IBM 2780 or LJ Diagnostics are provided through the Operational Diag 3780 terminal. This emulation is accomplished by nostic System (ODS), loaded as car"d decks distinct from software supplied in absolute binary form on card decks. the controlware. A different deck is used for each emulation. The soft ware is not intended to be accessible to the user for The minimum hardware configuration is: maintenance. The use of the term controlware reflects the "black-box" nature of the software. n • CYBER 18-05 with 16K bytes of memory

\ I u The functions provided by the emulated terminals are • Card reader described below.

96767850 A 4-1 n u • Line printer • CRT display of emulated IBM 27 80 status functions • CRT display and keyboard • ASA vertical forms control • Oper ator panel • Off-line processing similar to that provided under the 200 User T erminal emulation.

IBM 27BO EMULATION

The IBM 27 80 emulation in the batc h controlware IBM 3780 EMULATION provides: The batch terminal controlware provides capabilities • Compatibility with IBM host computer s capable of similar to those of the IBM 27 80 emulation, with the communicating wi.th .'2 7 13 0 terminals addition of: • Emulation of IBM bisync communication techniques, • Compatibility with IBM's Telecommunications with equipment and capabilities similar to those of Access Method (TCAM) under as, and with BT AM the emulated 200 User Terminal. under as or DOS. • Operator selection of EBCDIC or ASCII code, with Interruption of terminal operation by host CPU transparent text mode • Vertical and horizontal formatting of printed data • Selection of number (up to 30) of retransmit • attempts • Restart of terminal by host CPU • Selection of print-line length and of use of end-of record feature to eliminate trailing blanks on card

Figure 4-1. Typical CYBER 18-05 Configuration

·4-2 96767850 A ,.--) CYBER 18-10M COMPUTER CHARACTERISTICS. 5 ! I I "- - '\ \_~) ,'-' )

MODEL DESCRIPTIONS 1870-2 2048 INSTRUCTION MICRO MEMORY

Following are brief descriptions of the standard units. '!be 1870-2 micro memory provides storage for up to Descriptions of optional peripherals are included in 2048 32-bit micro control instructions for the processor. section 7, Standard Peripherals. '!be memory is a read or write RAM and can be loaded un externally or under control of the micro program. It is designed for micro program storage in those applications Ii that require the processor to be programmed at the I CYBER 18-10M PROCESSOR micro level. ~ The CYBER 18-10M is a micro-programmable proc essor unitj;hat accommodatel:J from 32, 768 to 131, 072 eight-bit bytes (one protect and one parity for each 1882-16 MOS MAIN MEMORY STORAGE two bytes) of MOS main memory, with an effective read/write cycle time of 750 nanoseconds. The 18-10M The 1882-16 provides 32,768 eight-bit bytes of read/ n emulates the basic as well as the enhanced 1700 instruc write MOS memory. One protect bit and one parity bit U tion set. Basic features of the processor include are provided with each two bytes. The effective read/ hardware multiply/divide, 16 levels each of micro and write cycle time is 750 nanoseconds. The 1882-16 occu macro interrupt s, auto-data transfer, a real-time clock, pies one memory position within the processor unit. deadstart facility from peripherals, an A/Q I/O port that supports up to nine peripheral controllers, and a DMA I/O port that supports up to four DMA-type devices. Feature options are 512- through 4096-instruction read/ 1882-32 MOS MAIN MEMORY STORAGE write micro memory with minimum instruction execution time of 168 nanoseconds for user micro programs, a The 1882-32 provides 65,536 eight-bit bytes of read/ programmable micro/macro breakpoint controller, and write MOS memory. One protect bit and one parity bit a breakpoint panel. The 18-10M includes a cabinet, are provided with each two bytes. The effective read/ operators panel, power supplies, an I/O controller to write cycle time is 750 nanoseconds. The 1882-32 occu support the 1811-1 Console Display., and a flexible disk pies one memory position within the processor unit. drive with controller. No main memory or read/write micro memory is included. CENTRAL PROCESSOR

1870-1 512 INSTRUCTION MICRO MEMORY The CYBER 18-10M central processing unit (CPU) con figuration consists of an ALU card, a status mode The 1870-1 micro memory provides storage for up to interrupt (SMI), two control cards, the I/O-TTY card, 512 32-bit micro control instructions for the processor. and the standard CYBER 18-10M transform card" '!be The memory is a read or write RAM (random-access detailed organization of the CYBER 18-10M is shown in memory) and can be loaded externally or under control figure 5-1. This diagram shows registers interconnec of the micro program. It is designed for micro pro ted primarily by selectors. A selector is a multiplexer (l gram storage in those applications that require that the that transfers one of several inputs to an output. They LJ processor be programmed at the micro level. are either one, eight, 12, 16, or 32 bits wide. ru

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w 96767850 A 5-1 I tBITTEST IT 55 (MA) (8) J T 58 (KIN) (8) I IT 57 (1) I r------, A t (16 INPUTS) T Dr SrTUS~ l T (16 INPUTS) T fff11TT1 : to t I (16) J: INTERRUPTS (32) 1 0"00' 'OJ E" §--- I I l ______...l ;-- 1 SPECIAL INTERRUPT (32) DELTA (16) r--I-- IXT INTERFACE 5 J OPTION I (16) .- INTERRUPT ADDRESS (5) 81 I ENCODE (16) I+-- ~ 51 S I - or ~ l~ (LSB) ,------, ~=;;.ACE :::: I MICRO OF Mml MAIN CPU TRISTATE BUS MEMORY 1(32) ,--____...L.. ____ -, (32) I C M1R (32) rr;-= --=-;:; ------, r-1~T-~rr~-.~------~~------~ pDATA FROM I I 11!!.,.E~9~!._J I I ~~~~E~ I I ~~ I i~ I~J : AB (16) I: CrR cL t'--____---. I I MEMORY DATA : Ic T TEST (1) I L~~R~M~M~R~_IN:::R::'AC':" _____ J :------l 1(16 INPUTS) f L BIT TEST (57) • ~ K7 I DATA D(16) ~ I TEST I I ~--L--r----~~~---.--~---' I 86 I CONDITIONS I I 18 SM1 (16) Ic (12) I I ~~t---'t~-~r-~~-~--r---~-..--~ ~I--+-----If JR~ I 110 Y (16) I I ADDR I 5300 TO PANEL ICIe (12)54 J ~ ~O ~~R:'A:: ~ ___ J rINTER,..F_A_CE______f- _____-. I t (N3-NT) and (K0-K6) TRANSFORM ~(RTJ) ,----'-.1.---'--, A 53 (16) J I FILE 1 ADDR/~ (LSB) I RTJ J Ie . (12t T TEST 5 RlILl L8 l' K7 I '--'~I~_---' e K (8) MICRO MEMORY A ALU (16) J AND1NSFORM ;:tc I TA TB INC/DECR INC/~ECR ORCLR ORCLR SI (16) S2 (16) IA I IA I f T J I ~Jl I I.LIt I L~~~RATO~ I OPTIONAL TRISTATE BUS INPUT TO BE LECTOR 51 AND 52 • FILE 11 FILE 21 A,:265) (32) ~-NT lmaHIIR11 (VIA F1 INPUTS i 1 J 8 E 8MI I I C = CONTROL2 1(16) P (16) A (16) F C16! X (16) Q (16) A IA A I A = ALU IA IA IA T = TRANSFORM f t t t t t

*FIIe 1 18 furD1.hed as an option.

Figure 5-1. Detailed Block Diagram of'CYBER lS-10M Processor

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Figure 5- 2. Typical CYBER 18- 10M Configuration

The data transfer organization of the CYBER. 18- 10M AR ITHMETIC / LOGICAL UNIT DATA TRANSFER provides for storing data in one of six working reg ister s a nd two files, and for selecting data for processing The ALU provides the arithme tic and logical capabilities through the ALU. ALU results are transferred mck to of thc CPU. This lUlit combines two 16-bit input words one of the regis ters or out of the organization to control according to the function code specified il1 the micro external eqUipment. ins truction. The r esult is immedia te ly available at the the output of the ALU for possible shifting via selector The primary data rcgisters are I, P, A, F, X, and Q . S3 a nd delivery to the destination register, memory interface, panel interface, and I/O. The lUlshifted The following are bricf descriptions of the primary output of the ALU is de livered to the status mode and registers: mask registers. The ALU output can be ignored on an operation. The results of the ALU operation regarding • I R.egister - A 16-bit register whose only input and sign, zero, and magnitude (by means of carryout level) output is the selector S1. This register should not are available to the test bit logic for instruction sequencing.

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be confused with the 1700 I register (location • status/Mode Register (SM) - The SM register 00FF )· allows the micro program to control the mode of 16 LI operation and also allows the micro program to P Register t - A '16-bit, general-purpose register • examine the status of certain internal and external that receives data from the AL U and provides out conditions. The CPU can access one of twoSM r put to S1. Normally it is used to hold the software registers, SM1 and SM2. instruction counter. L The SM register module contains 16 bits of SM1 A Registert - A 16-bit, general-purpose register • and 16 bits of SM2. All 32 bits of an 8M module r that receives data from the ALU and provides out can be set or reset by the micro program by put to S1. The A register is mechanized as a shift L, transferring information to the SM register from ing register, and can be shifted left or right with the output of the ALU. Master clear will also clear out using the AL U. The A register may also be SM1 and SM2. r combined with the Q register to form a double length shifting register that operates independently • Interrupts and Mask Register - The interrupt L... of the ALU. system is implemented as a sampled data system at the micro-program level, instead of a true /' F Register - A 16-bit, general-purpose register • vectored interrupt system as used in conventional L. that receives data from the AL U and provides data computers. to S1 or'S2 as ALU input. This register is also used as the file entry register and contains infor The mask register enables the micro processor to mation written into the files when they are used as disable/enable interrupts. The CPU can access the destination of an ALU operation. two mask registers, M1 or M2. For each mask L bit there is a corresponding bit in the interrupt • X Register - A 16-bit, general-purpose register register. that receives data from the ALU and provides data to S1 or S2. M1 is available to the 1700 programmer through the DMI instruction, while M2 (referred to as M) • Q Register t - A 16-bit, general-purpose register is available through the basic inter-register that receives data from the ALU and provides out instruction. put to S2. The Q register is mechanized as a ...... shifting register. It may be shifted left or right in Interrupts are identified by their corresponding conjunction with the A register without using the mask bits, which are assigned to control the inter ALU. rupt recognition. The bits in the mask registers are identified as follows: other major portions of the standard CYBER 18-10M are: -Mask Register 1 (M1): M100 through M115 • File 2 - A 32-word scratchpad file that may be -Mask Register 2 (M2): M200 through M2i5 used as a general-purpose, word-sized register. Interrupt addresses are generated by the interrupt It delivers its output to S1 and S2; data input is address encoder, according to the assignments provided by the F register. File 2 is reserved for given in table 5-1. the emulator, except for registers R1, R2, R3, I._' and R4, which are available to the 1700 program The interrupt priorities correspond to the mer through enhanced instructions. interrupt address generated; that is, interrupt address 00 is ~ssociated with the highest priority r-" • Bit Generator (BG) - The BG circuit generates interrupt line and interrupt address 31 is LJ one bit at any position in a word as input to the B associated with the lowest priority interrupt line. side of the ALU. Control to drive the bit generator For example, an interrupt associated with M112 r is derived from either the micro instruction (bits would have priority over an interrupt associated 27 to 31) or the lower five bits of the N register. with M1ll, and an interrupt address of 3 L, Control is usually obtained from the micro instruc would be developed by the interrupt address tion. A bit setting in an SM register determines encoder. ,... the input that will drive the bit-generator. I • K Register - An eight-bit counter that can be ~ cleared, incremented, or decremented. It is used to address file 1 in addition to any program r t Available to the 1700 programmer. usage as a counter. ( -- L)I 5-4 96767850 A r ~ -1

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TABLE 5-1. MASK REGISTER/INTERRUPT • N Register - An eight-bit counter that may be ADDRESSES cleared, incremented, or decremented. It is used to address file 2, control shifts, control Mask Interrupt Address the scale operations, and may be used as an Bit Mask. Register 1 iteration counter that controls micro-instruction l execution. .J M100 15 Lowest Priority (M1) N/K Register - The Nand K registers may be M101 14 • I combined to provide operand addresses outside I M102 13 the current operating micro page. M103 12 M104 11 M105 10 I M106 09 I TRANSFORMS I...J MI07 OS M108 07 Transforms enable quick and efficient decoding of an M109 06 emulated instruction. A transform can be designed to MIlO 05 extract bits from a register or registers, shift the bits MIll 04 to the required position, and add a base address or M112 03 constant bits. This result can then be transferred to M113 02 the micro-memory address register (transform jump) MU4 01 or to the K or N register (transform register load). MU5 00 Highest Priority (M 1) For example, when a 1700 instruction is read from Mask Interrupt Address macro memory, one micro-instruction transform jump Bit Mask Register 2 transfers control to one of 108 micro-memory locations. o Without the transform feature the above operation would require many micro instructions • .M200 31 Lowest Priority (M2) M201 30 The transform hardware is packaged on a separate M202 29 printed circuit card and is implemented using three M203 28 selectors. The transform module includes 1,024 micro M204 27 instructions (512 words) in read-only memory. The . M205 26 majority of these instructions are used to execute the o M206 25 1700 emulator. The ROM also contains instructions for M207 24 the panel interface simulation via the I/O-TTY ~ard. M20S 23 n M209 22 u M210 21 M211 20 M212 19 I/O.TTY MODULE M213 is M214 17 The I/O-TTY module includes the following components: M215 16 Highest Priority (M2) • Real-Time Clock - In conjunction with the micro Note: The interrupt address generated is the code it appears as a 1700 peripheral to the macro same as its priority level; i. e., the level programmer. highest priority interrupt generates a • I/O Teletypewriter/Display Control - This con O' interrupt address and the lowest troller is an integral part of the module. It inter priority interrupt generates a 31 faces to Control Data RS232-C-compatible con interrupt address. versational display terminals. rJ

96767850 A 5-5 nu , c ;' • Internal Peripheral Controller Bus - Provides all inter-register, skip, and shift instructions~ The en I/O data lines, interrupts, and control signals hanced instruction set is divided into the enhanced L necessary to generate, in conjunction with the storage reference, field reference, enhanced inter micro code, an internal CDC 1700 A/Q (input/ register, enhanced skip, decrement and repeat, and r output) bus. 'This TTL-level bus is intended to miscellaneous instructions. interface with controllers located in the basic LJ chassis. ,-. • Panel Interface Simulation - A logic section that BASIC INSTRUCTION SET is required when a panel/program device is used for operator input in the panel mode. L

r--" The CPU is interfaced to the I/O module as follows: Storage Reference LJ • ALU Output - All output data and address informa The storage reference instructions shown in the tion is provided from the output of the ALU via S3. following illustration contain three fields: instruction, I' • " SM Register -All commands to peripheral con address mode, and delta. The instruction field contains 'L. trollers are generated by micro code manipulation the operation code. of the status mode register. r-- The address mode field contains flags for indexing, • CPU Control - Timing and control information for indirect addressing, and relative addressing. The controlling internal I/O module data gating is pro L_, delta field is a signed eight-bit address modifier in vided from the CPU control Signals. which the most significant bit is the' sign bit. Storage reference instructions have the following format:

I~ ,~ CYBER 18-10M 15 12 11 10 9 8 '1 o INSTRUCTION DESCRIPTION

Instruction Delta (.6) INSTRUCTION FORMAT

The CYBER 18-10M computer instruction word shown in L. the following example consists of 16 bits, numbered right to left as 0 to 15, with the leftmost bit, 15 being Index Register 2 Flag cu the most significant and the rightmost bit, 0, being the (I Register) ~ least significant. L. Index Register 1 Flag (Q Reglster) ,..--.' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Indirect Addr~ss Flag t.-.

Instruction Word Rel~ti ve Address Flag I I r t t L. Most Significant Bit Least Significant Bit Five types of addresses and/or address methods are created by these Instructions: r Hexadecimal" (base 16) notation is used in this computer. • Instruction Address - The address of the instruction being executed; also called P L" The computer is composed of a basic and an enhanced instruction set. The basic set is 1700-compatible and • Indirect Address - A storage address that r- is divided into storage reference, register reference, contains an address rather than an operand l __

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~ il • Base Address - The operand address after all • Eight-Bit Relative (address mode blts = 8, 9, A, u indirect addressing but before modification by or B) - The relative flag is set to· 0, and delta is the Index1registers. The base address is the not set to O. The base address is equal to the effective address when no indexing is specified. instruction address P plus the value of delta with sign extended. The contents of the index Effective Address - The final address of the 0 • registers, when specified, are added to the base operand. At certain times the effective address address to form the effective address. equals the operand for read-operand type instructions (refer to table 5-2). • Eight-Bit Relative Indirect (address mode bits = C, D, E, or F) - Both relative and indirect flags are 0 Indexing - The computer has two index • set to 1. If delta is not set to 0, the value of the registers. Index register 1 is the Q regis instruction address P plus the value of delta with ter; index register 2 is storage location OOFF 16 sign extended is an indirect address. If bit 15 of (I register). The bas"3 address may be modi 0 the contents of this indirect address is 0, the fied by either or both of th,9 in:lex registers. contents of this indirect address is the base If the index 1 flag is set, the contents of the Q address. If bit 15 of the contents of the indirect register are added to the base address to form address is set when the computer is in 32K C the effective address. If the index register 2 mode, another indirect address is indicated. flag is set, th,e contents of storage locatio!} OOFF 16 (I register) are added to the base address to • Absolute Constant (address mode bits = 0, 1, 2, form the effective address. If both index or 3) - Both relative and indirect flags and delta 0 register flags are set, the contents of Q are are set to O. added to the base address; then the contents When the address mode bits are set to 0, P + 1 is of OOFF 16 are added to the result to form the the effective address. When the address mode effective address. B (for both) is used for 0 bits are set to 1, 2, or 3, the contents of P + 1 indexing both the Q and I register. Ind'3xing plus the contents of one or both index registers occurs after completion of indirect addressing. form the effective address. The effective address is taken as the operand for read-operand type [J Instructions. The computer uses the 16-blt ones complement_adder during indexing operations. Consequently, the index • 16-Bit Storage (address mode bits = 4, 5, 6, or register contents are treated as signed quantities (bit 7) - The relative address flag and delta are set to 0 15 is the sign bit). o and the indirect flag is set to 1. The contents of location P + 1 is an indirect address. When the The storage reference instructions (refer to table 5-2) base address is formed (indirect addressin.,g !l have eight different types of addressing modes: eight complete), the contents of one or both Index U bit absolute, eight-bit absolute indirect, eight-bit registers, if specified, are added to form the relative, eight-bit relative Indirect, absolute constant, effective address. n 16-bit storage, 16-bit relative, and 16-bit relative • 16-Bit Relative (address mode bits = 8, 9, A, u indirect. or B) - The relative address flag is set to 1, and the indirect address flag and delta are set to O. • Eight-Bit Absolute (address mode bits = 0, 1, 2, If no indexing is specified, the instruction address or 3) - Both relative and indirect flags are set P + 1 plus the contents of location P + 1 form the n 0 O. u to and delta is not set to The base address base address or effective address. If indexing is equals delta. Delta has no sign·bit. The contents specified, the contents of the specified index of the Index registers, when specified, are added register(s) are added to the base address to form r to the base address to form the effective address. the effective address. ~ • Eight-Bit Absolute Indirect (address mode bits = • I6-Bit Relative Indirect (address mode bits = C, 4, 5, 6, or 7) - The relative address flag is set D, E, or F) - Both relative and indirect flags are n to 0, the indirect flag is set to 1, and delta is not set to 1. In 65K mode, the contents of P + 1 + : I u set to O. The eight-bit value of delta is an (P + l)t is the base address. Then the contents indirect address. Delta is a magnitude quantity 'I for this operation (no sign bit). t ( ) Denotes contents of expression u

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; TABLE 5-2. STORAGE REFERENCE INSTRUCTION ADDRESSING

L, Binary A Address of Mode 111098 Hex. Delta Effective Address Next Instruction ,

8-Bit Absolute 0000 0 10 A P+l L, 0001 1 A+(OOFF) 0010 2 A+(Q) r 0011 3 A+(Q)+(OOFF) L 8-Bit Absolute Indirect tt 0100 4 (A) 0101 -5 (A)+(OOFF) 1"" 0110 6 (A)+(Q) LJ 0111 7 (A)+(Q)+(OOFF) r 8-Bit Relative I 1000 8 P+~ 1001 9 P+~+(OOFF) L, 1010 A P+A+(Q) 1011 B P+A+(Q)+(OOFF)

8-Bit Relative Indirecttt 1100 C (P+.6) LJ 1101 D (P+.6)+(OOFF) 1110 E (P+.6)+(Q) r 1111 F (P+.6)+(Q)+(OOFF) l., Absolute Constant 0000 0 =0 P+1 P+2 0001 1 (P+ l)+(OOFF) t r 0010 2 (P+1)+(Q)t 0011 3 (P+1)+(Q)+(00FF)t ,----. 16-Bit Storage tt 0100 4 (P+1) 0101 5 (P+1)+(00FF) L 0110 6 (P+1)+(Q) 0111 7 (P+1 )+(Q)+(OOFF) ,--.

16-Bit Relative 1000 8 P+1+(P+1) LJ 1001 9 P+1+(P+1)+(00FF) 1010 A P+1 +(P+1 )+(Q) 1"" 1011 B P+1 +(P+ l)+(Q)+(OOFF) L 16-Bit Relative Indirecttt 1100 C (P+1 +(P+1» 1101 D (P+1 +(P+l»+(OOFF) 1"" 1110 E (P+1 (P+1 »+(Q) L. 1111 F (P+1 +(P+l»+(Q)+(OOFF) r L

t Effective address Is the operand for read-operand type instructions. ttMultilevel only in 32K word mode r c

L 5-8 96767850 A l .J

of the index registers, when specified, are added Skip to the base address to form the effective address. In 32K mode, P + 1 + (P + 1) = base address if Skip instructions (F 1= 1) are identified by a 1 in the ., bit 15 of (P + 1) is 0; if 1, then P + 1 + (P + 1) address mode field and a 0 in the instruction mode forms an indirect address. This process field: J continues until bit 15 = O. 15 1211 8 7 4 3 o r I 10 0 0 010 0 0 I --l Register Reference • Register reference instructions use the address mode Instruction Sub- Skip Skip n Instruction Instruction Count u field for the operation code. These instructions are identified by Os in the upper four bits of an instruction (Fl) (F2) and the Fl instruction operation code (address mode field) cannot be a one, eight, or 15: un When the skip condition is met, the contents of the skip count + 1 is added to P to obtain the address of the next 15 12 11 8 7 o instruction (e.g., when the skip count is 0, go to P + 1). n When the skip condition is not met, the address of the i I U Fl next instruction is P + 1 (skip count ignored). The skip count does not have a sign bit. Instruction Modifier (~) Operation o Code Shift [) Shift instructions are identified by a 15 in the address Inter-Register mode field and a 0 in the instruction mode field. These instructions shift A or Q, or QA left or right for the Inter-register instructions (Fl = 8) are identified by an number of places specified by the five-bit shift count. The sign is extended on right shifts. Left shifts are end nu 8 in the address mode field and a 0 in the instruction mode field. These instructions cause data from certain around. This instruction has the following format: combinations of origin registers to be sent through the adder to any combination of destination registers. o Various operations, selected by the adder control 15 12 11 8 7 5 4 0 lines, are performed on the data as it passes through 0 0 1 1 F2a the adder. The inter-register instruction format is: I0 o 11 11 I o '---y----1 Shift Count n 15 12 11 8 7 6 5 4 3 2 0 L o 0 001 0 0 Q M A Q M ENHANCED INSTRUCTIONS

Instruction formats for enhancements to the 1700 Adder {L<>gical Product instruction repertoire are upward-compatible with Control Exclusive OR Operand 2 existing 1700 com puters. They· make use of preViously Origin Registers 0 d undefined instruction formats. { peran 1 r.LJ Destination Registers

96767850 A 5-9 n U r L.J

r-'

(~-. ,--. Enhanced Storage Reference The addressing mode fields contain four fields: L These Instructions have the following format: 1. Delta determines eight- or 16-blt addressing. If delta is 0, a third word wlll be required to r specify a 16-blt address. ~ 15 12 11 8 7 6 5 3 2 o 2. Flag r is the relative address flag. I F=O Fl = 4 r Ra Rb Flag i is the indirect address flag. r i I I 3. 4. Register Ra is the index register • ~ F4 F5 .!l The addressing modes are similar to the basic storage r • instructions. The basic set allows indexing by one or ~: 16 bit address. if.!l = 0 , L.J 1l4,L ______J ' two registers (I and Q); while the enhanced set allows in dexing by anyone of seven registers (1, 2, 3, 4, Q, A, ,--. or 1). Table 5-3 specifies the addressing modes, the ef fective address, and the address of the next instruction. L,

The enhanced storage reference instructions are The addressing mode fields determine the effective identified when the F field is 0, the F I field is equal address for operand A. Register Rb and the instruction to 4, and the r, i, Ra, and Rb fields are not all o. mode field (F5) determine the address for operand B •. L) (If these fields are all 0, the instruction is an EIN.) Note that for character addressing, the effective address This instruction is made up of two (or three, if delta (operand A and register Rb) are combined to ascertain ,--. is 0) words. the actual character effective address. Operand B is always the A registerfor character addressing. L., The enhanced storage reference instructions are similar to the basic storage references in that they (- contain four parts: Instruction field (F4), instruction CAUTION \....- mode field (F5), addressing mode fields (delta, r, i, For character addressing, selection of ---.J and Ra), and register Rb. Two op~rands (A and B) absolute (r = 0), no indirect (i = 0), no are specified for executing the instruction. index register (Ra = 0), and no charac r-' ter register (Rb = 0) will result in an L, The F4 field determines the instruction (e. g., add, EIN instruction. subtract, etc.). The F5 field determines the instruction ,..-. mode: Any unspecified combinations of F4, F5, and Rb~ are reserved for future expansion. l_, F5 = 0 Word processing; register destination 1 Word processing; memory destination The following definitions apply to the description of r addressing modes: 2 Character processing; register w destination • Instruction Address - The address of the 3 Character processing; memory instruction being executed, also called P. r destination • Indirect Address - A storage address that L_, contains an address rather than an operand. Note that there is no multilevel indirect. r NOTE addressing for enhanced storage reference L, F5 is not used for subroutine jumps instructions. and subroutine exit. The register/ • Base Address - The operand address after all r memory destination bit of F5 is not indirect addressing but before modification by an used for compare instructions (see index register. The base address is the effective L, below). address if no indexing is specified. r C

L., 5-10 96767850 A r i L,I --1

I .-J l -0 ] TABLE 5-3. ENHANCED STORAGE REFERENCE INSTRUCTION ADDRESSES Addressing Address of Next Mode Delta ] r i Ra Effective Address (EA) Instruction 8-Bit Absolute 6#0 0 0 0 6 P +2 0 0 1 6 + (1) P +2 0 0 2 6 + (2) P +2 ] 0 0 3 6 + (3) P +2 0 0 4 6 + (4) P +2 0 0 5 6 + (Q) P +2 l 0 0 6 6 + (A) P +2 --1 0 0 7 6 + (1) P +2

~1 8-Bit Absolute Indirect 6,,!0 0 1 0 (6) P + 2 --1 0 1 1 (A) + (1) P +2 0 1 2 (A) + (2) P +2 0 1 3 (A) + (3) P +2 0 1 4 (A) + (4) P +2 0 0 1 5 (6) + (Q) P +2 0 1 6 (6) + (A) P +2 0 0 1 7 (6) + (I) P +2 8-Bit Relative t 6#0 1 0 0 P + 1 + 6 P +2 ...-"\ 1 0 1 P + 1 + 6 + (1) P +2 1 0 2 P + 1 + 6 + (2) P +2 [ J 1 0 3 P + 1 + 6 + (3) P +2 1 0 4 P + 1 + 6 + (4) P +2 n 1 0 5 P + 1 + 6 + (Q) P +2 \ I 1 0 6 P + 1 + 6 + (A) P +2 U 1 0 7 P + 1 + 6 +(1) P +2

8-Bit Relative Indirectt 6#0 1 1 0 (P+1+6) P +2 0 1 1 1 (P + 1 + 6) + (1) P +2 1 1 2 (P + 1 + 6) + (2) P +2 1 1 3 (P + 1 + 6) + (3) P +2 n 1 1 4 (P + 1 + 6) + (4) P +2 LJ 1 1 5 (P + 1 + A) + (Q) P +2 1 1 6 (P + 1 + A) + (A) P +2 0 1 1 7 (P + 1 + 6) + (I) P +2 0 nu t For these addressing modes, delta Is sign extended. n Note: ( ) Denotes contents of expression. Lt:J C 96767850 A 5-11 C f'

["'

( 1,,--- f' TABLE 5-3. ENHANCED STORAGE REFERENCE INSTRUCTION ADDRESSES (Continued) l_l Addressing Address of Next Modes Delta r i Ra Effective Address (EA) Instruction f' ~ Absolute Constant ~=O 0 0 0 P +2 P +3 0 0 1 P + 2 + (1) P+3 ,.. 0 0 2 P + 2 + (2) P +3 0 0 3 P + 2 + (3) P +3 L 0 0 4 P + 2 + (4) P +3 0 0 5 P + 2 + (Q) P + 3 f' 0 0 6 P + 2 + (A) P + 3 ~ 0 0 7 P + 2 + (I) P +3

f' 16-Bit Storage ~=O 0 1 0 (P +2) P +3 0 1 1 (P + 2) + (1) P +3 ~ 0 1 2 (P + 2) + (2) P + 3 0 1 3 (P + 2) + (3) P+3 :-' 0 1 4 (P + 2) + (4) P+3 L.J 0 1 5 (P + 2) + (Q) P +3 0 1 (P + 2) + (A) 6 P +3 r 0 1 7 (P + 2) + (I) P +3 L__

16-Bit Relative ~=O 1 0 0 P + 2 + (P + 2) P + 3 1 0 1 P + 2 + (P + 2) + (1) P +3 1 0 2 P + 2 + (P -+- 2) + (2) P +3 C .. -.l 1 0 3 P + 2 + (P + 2) + (3) P +3 1 0 4 P + 2 + (P + 2) + (4) P +3 r 1 0 5 P + 2 + (P + 2) + (Q) P +3 1 0 6 P + 2 + (P + 2) + (A) P +3 l_, 1 0 7 P + 2 + (P + 2) + (I) P +3 ,.. 16-Bit Relative Indirect ~=O 1 1 0 (P + 2 + (P + 2» P+3 L, 1 1 1 (P + 2 + (P + 2» + (1) P +3 1 1 2 (P + 2 + (P + 2» + (2) P+3 1 . 1 3 (P + 2 + (P + 2» + (3) P +3 1 1 4 (P + 2 + (P + 2» + (4) P+3 L, 1 1 5 (P + 2 + (P + 2» + (Q) P +3 1 1 6 (P + 2 + (P + 2» + (A) P +3 r 1 1 7 (P + 2 + (P + 2» + (I) P +3 L r L.

/1 I ~

Note: ( ) denotes contents of expression :

_I C L, 5-12 96767850 A \1 ~ l -'1 \--~ I • Effective Address - The final address of the If no indexing takes place, the addresses that can operand. be referenced in the eight-bit relative mode are J restricted to the program area. Delta is eight • Indexing - If specified, the contents of register bits long, thus the computer references a Ra is added to the base address to form the location between P - 7E16 and P + 80 inclusive. ] effective address. Indexing occurs after 16 addressing is completed. Eight-Bit Relative Indirect (r = 1, 1 = 1, and .' .6. I- 0) - The address of the second word of the The computer uses the 16-bit ones complement instruction, P + 1, plus the value of delta with ] adder during indexing operations. Consequently, sign extended is an indirect address. The the index register contents are treated as signed content of this address is the base address. The quantities (bit 15 is the sign bit). contents of index register Ra, when specified, • Registers - Registers Ra and Rb are defined as are added to the base address to form the ] follows: effective address. Register Value • Absolute Constant (r = 0, i = 0, and .6. = 0) - The address of the third word of the instruction, None 0 P + 2, is the base address. The contents of the c 1 1 index register Ra, when specified, are added to 2 2 the base address to form the effective address. 3 3 Thus, when Ra is not specified, the contents of 4 4 P + 2 is the value of the operand. o Q 5 A 6 Note that there is no immediate operand condition I 7 (1. e., indexing is specified and the instruction is a read-operand type) as there is for basic storage o reference addressing. Enhanced storage reference instructions (table 5-3) have the following types of addressing modes: • 16-Bit Storage (r = 0, i = 1, and.6. = 0) - The base address equals the contents of P + 2. The [J • Eight-Bit Absolute - (r:: 0, i = 0, and Lll- 0) - contents of index register Ra, when specified, The base address equals delta and the sign bit of are added to the base address to form the delta is not extended. The contents of index effective address. register Ra, when specified, are added to the o base address to form the effective address. • 16-Bit Relative (r = 1, i = 0, and .6. = 0) - The base address equals the contents of P + 2 plus • Eight-Bit Absolute Indirect (r = 0, i = 1, and P + 2. The contents of index register Ra, when .6. I- 0) - The eight-bit value of delta is an specified, are added to the base address to form o indirect address. The sign bit of delta is not the effective address. extended. The content of this address in low 16-Bit Relative Indirect (r = 1, i = 1, and core (addresses 0001 to .OOFF16) ~s the base 16 • address. The contents of mdex regIster Ra, Ll = 0) -,The address of the third word of the o when specified, are added to the base address instruction, P + 2, plus the contents of the third to form the effective address. word of the instruction is an indirect address. The content of this address is the base address. • Eight-Bit Relative (r = 1, i = 0, and .6. -I 0) - The The contents of the index register Ra, when o base address is equal to the instruction address specified, are added to the base address to form plus one, P + 1, plus the value of delta with sign the effective address. extended. The contents of index register Ra (when specified) are added to the base address o to form the effective address. D 0 1 oI-.J 96767850 A 5-13 o Field Reference Enhanced inter-register instructions are identified when the F field is 0, the Fl field is 7, and the F2a, !(a, mid These instructions have the following format: Rb fields are not all O. (If these fields are all 0, the instruction is C PB. )

15 12 11 8 7 6 5 3 2 o Enhanced inter-register instructions (similar to the basic) inter-register instructions, such as TRA Q) contain F=O Fl = 5 r /11 Ra I F3a three parts: operation field (F2a) and two register fields (Ra and Rb). The F2a field determines the operation FLDSTR FLDLTH-l t:;. (e. g. ,transfer). The Ra and Rb fields specify two operands. c-:JI + : 16-bit address, if t:;. = 0 • ~I • Note that F2a = 1, F2a = 2, F2a = 3, Ra = 0, and Rb = 0 '- - -- .. - - - - .------... are reserved for future expansion.

Field reference instructions are identified when the F The instruction description is: field is 0, the Fl field is equal to 5, and the r, i, Ra, and F3a fields are not all O. (If these fields are all 0, Transfer Register XFr R the instruction is an lIN.) F2a = 0 Ra = 1, 2, 3, 4, 5, 6, or 7 Field reference instructions contain four parts: r = 1, 2, 3, 4, Q, A, or 1 operation field (F 3a), addre ssing mode fields (t:;., r, i, and Ra), FLDSTR, and FLDLTH-l fields. The F3a Transfer the contents of register r to register R. field determines the operation (e. g., load, store). The Note that R = 1, 2, 3, 4, Q, A, or I implies that addressing mode fields are defined exactly as the Rb = 1, 2, 3, 4, 5, 6, or 7. enhanced storage reference instructions.

FLDSTR defines the starting hit of the field. For example, F LDSTR = 0 indicates that the field starts Enhanced Skip at hit O. FLDLTH-l defines the length of the field minus one. FLDLTH-l = 0 indicates that the field is The skip instructions have the following format: one hit long. If FLDLTH-l = 0, the field reference instructions become bit reference instructions. 15 12 11 8 7 4 3 o A field starts at the bit specified by F LDSTR and includes the contiguous FLDLTH bits to the right of F=O Fl = 0 F2 SK that bit. No field may cross a word boundary (i. e. , FLDSTR-FLDLTH-l must be greater than or equal to 0). If FLDSTR = 0, the field length must be one bit Enhanced skip instructions are identified when the F long (FLDLTH-l = 0). and Fl fields are both 0, and the F2 and SK fields are not both O. (If these fields are both 0, the instruction is "Note that F3a = 0, F3a = 1, and FLDSTR-FLDLTH-l< 0 an SLS.) are reserved for future expansion. Enhanced skip instructions (similar to the basic skips; such as SAZ) contain two parts: operation field (F2) and skip count (SK). The F2 field determines the Enh anced Inte r-Reg iste r operation (i.e., skip on register 1, 2, 3, or 4 if zero, nonzero, positive, or negative). The skip count These instructions have the following format: specifies how many locations to skip if the skip condition is met. 15 12 11 8 7 5 4 3 2 0 When the skip condition is met, the skip count plus one F " 0 Fl ~ 7 Ra F2a I Rb is added to the P register to obtain the address of the next instruction (e. g. , when the skip count is one, go to

5-14 96767850 A ] l

I 'I J P + 2). When the skip condition is not met, the address Miscellaneous of the next instruction is P + 1 (skip count ignored). ] The skip count does 'not have a sign bit. Miscellaneous instructions have the following format:

If F2 = 0 (S4Z), the skip count cannot be 0 because the ] instruction would be an SIB. 15 12 11 8 7 5 4 3 o

F '" 0 Fl = B Ra I0 I F3 I

] Decrement an,d Repeat Miscellaneous instructions are specified when the F These instructions have the following format: field is 0, the Fl field is equal to a decimal 11 (hexadecimal B), bit 4 is 0, and Ra and F3 fields are ] not both O. (If these fields are both 0, the instruction is 15 12 11 8 7 5 4 3 o an NOP.) All of the miscellaneous instructions are privileged instructions; i.e. , if they are executed by an F=O Fl = 6 SK unprotected program, they will cause a program protect ] Ra H violation.

Decrement and repeat instructions are specified when Miscellaneous instructions contain two parts: operation ] the F field is 0, the Fl field is 6, bit 4 is 0, and the field (F3) and ~egister field (Ra). Ra and SK fields are not both O. (If these fields are

both 0, the instruction is a SPB.) If Ra is nonzero t the F3 operation field can select up to 16 miscellaneous instructions with register Ra used to Decrement and repeat instructions contain two parts: specify an operand. If Ra is 0 t the F3 operation field 0 register field (ra) and skip count (SK). The register can select up to 15 more miscellaneous instructions field specifies which register is to be decremented by without any explicit operand specified. one and checked for the skip condition. The skip count [~ specifies how many locations to repeat (go backwards) The miscellaneous instruction formats are: if the skip condition is met. 1. Load Micro Memory When the skip condition is met, the skip count is 0 subtracted from the P register to obtain the address of the next instruction (e. g. , when the,skip count is one, ~ 15 1 0 go to P - 1). When the skip condition is not met, the ~ ~ address of the next instruction is P + 1. The skip fIl 0 Micro Address "6D 0 count does not have a sign bit. Q.) ~ Note that Ra = 0 and bit 4 = 1 are reserved for future Upper micro instruction --~ expansion. o 0 1 Lower micro instruction The instruction description is:

Decrement and Repeat if Positive DrP SK Initially t the Q register contains the number of 32-bit 0 micro-memory instructions to be transferred (if Q = 0, Ra = 1, 2, 3, 4, 5, 6, or 7 no instructions will be transferred). Register 1 r = 1, 2, 3,4, Q, A, or I contains the starting address of micro memory. Decrement the contents of register r by one. Register 2 contains the starting address of the macro 0 memory. Operation on overflow is the same as for the ADD instruction. Repeat (go backwards) SK locations The most significant bit (15) of the contents of the if the contents of register r are positive (bit 15 is starting address will be transferred to the most 0 0), otherwise execute the next instruction. significant bit of the first micro instruction. The least significant bit (0) of the contents of the starting address

~ ~~'-'''\ j 0'-"' g6767850 A 5-15 0 r \, '. plus one will be transferred to the least significant bit. 15 14 o r-' This instruction is interruptible after storing each 32- bit micro memory instruction, and when registers I, 2, ADT Table Address I- and Q are incremented/decremented to allow the instruction to be restarted after any interruption. When AI ~Auto~a I' the instruction is completed, these registers will transfer L, contain the following rather than their original values:

I' Q - 0 15 14 12 11 o Rl- (Rl)i+(Q)i L-.J R2 - (R2)i +2*(Q)i A

r-' Where: i is the initial value before execution. LJ 2. Set/Sample Output or Input transfer

When bit 15 of the A register is set to a 1, a jump is 15 1110 9 76 43 1 0 L-.J made to the upper micro instruction of the page/micro Q o memory in bits 0 to 14. A section of micro memory is assumed to have been previously loaded, and it must process the micro interrupt properly and return control L Port No. to the current macro instruction address (P) by jumping Set/Sample to the lower micro instruction of micro-memory r condition bit address 3E16 in micro page zero. Registers P, A, Q and all of file 2 should not be altered, and return must L be within 12. 5 microseconds. 3. Sample Position Status (-

I ...... CAUTION ,~_J 15 11 10 9 76 o The micro function, SUB-, must not be r 0 used. Extreme caution should be exercised in ______O______QI~ ______~~L-III ~ ~ using this option, since it provides an escape L JI from the 1700 .emulation being performed. Port• No. r-- 5. Exec'ute Micro Sequence I_ .. 1 15 12 11 8 7 54 2 1 0 AI 0 Status 0 IPosition I 0 15 12 11 8 7 o I I I LJ LLSB R 1~ ______o ______~ ____p_a_g_e ___ ~I~M___ i_c_ro_-_M ___ e_m_O_r_y __ A_d_d_r_e_s_s~1 r 4. Define Micro Interrupt An EMS to non-existant micro memory may cause an L indeterminate result. Control should be returned to the 15 14 43 0 next macro-instruction address (P + 1) by jumping to r-- Micro ~he lower micro instruction of micro-memory address 0 I Interrupt Ql 3E16 in micro page zero. Registers P, A, Q, and all L, No. of file 2 should not'be altered, and return must be / disable Nos. 12-15 are -.J within 12.5 microseconds (or the micro sequence must r- t ~nable be interruptible). interrupt not used L,

r LJ ,~-- I (" LJ 5-16 96767850 A r L o c~ (,j [J CAUTION MASK REGISTER Extreme caution should be exercised in using The mask register is the enable for each interrupt state this option, since it provides an escape from or line. Bit 0 of the mask register corresponds to the n the 1700 emulation being performed. interrupt line 0, bit 1 to line 1, etc. To enable an inter LJ rupt line, its corresponding bit in the mask register INTERRUPT SYSTEM must be set. The mask register is set by the inter register instruction. The interrupt system enables the program to establish o an interrupt priority so that an interrupt of high priority can interrupt the machine while it is processing an inter PRIORITY rupt of a lower priority. The return path to the inter rupted program is clearly established and saved. D The computer program controls the interrupt priority by establishing an interrupt mask for each interrupt state, which enables all higher priority interrupts and INTERRUPT TRAP LOCATIONS disables all lower priority interrupts. When an o interrupt state is entered, the mask for that state is Trap locations are established for each interrupt line. placed in the mask register. Therefore, there may be They are in the range of addresses 0100 through 013C. up to 16 levels of priority. It is possible to change These addresses are reserved for interrupts unless that priority during execution of a program. o particular interrupt is not being used. The assignment for each interrupt state or line is shown in table 5-4. n INTERNAL INTERRUPTS u TABLE 5-4. INTERRUPT STATE DEFINITIONS Interrupts are also generated by certain conditions Value ofll. Location Location of First arising within the computer. These are called internal [) Interrupt to of Return Instruction after interrupts. If such a condition occurs, it generates State Exit State Address Interrupt Occurs interrupt 00 (interrupt mask bit 00). Normally, internal interrupts are assigned the highest priority. 00 00 0100 0101 The internal interrupts are: o 01 04 0104 0105 • Storage Parity Error 02 08 0108 0109 • Program Protect Fault o 03 OC 010C 010D • Power Failure 04 10 0110 0111 05 14 0114 0115 o 06 18 0118 0119 OPERATION 07 lC 011C 011D The computer can distinguish between up to 16 (1 08 20 0120 0121 o internal, 15 external) macro interrupts. Each of these 09 24 0124 0125 interrupts has its respective address to which control is transferred when the interrupt is recognized. 10 28 0128 0129 o 11 2C 012C 012D When the computer is processing a particular interrupt, it will be defined as being in that interrupt state (state 12 30 0130 0131 00 through 15). Thus, the interrupts and their c· 13 34 0134 0135 respective bits in the interrupt mask register are numbered 00 through 15. An interrupt in bit 7 will put 14 38 0138 0139 the computer in interrupt state 7, etc. 15 3C 013C 013D

96767850 A 5-17 o r l.J

r-' e, Before the computer can recognize any interrupt, the 543210 mask bit for that interrupt must be set and the interrupt Ll system must be activated. The mask register may be Mask 1 1 1 1 1 1 1 Mask used for main program set by an inter-register command and the interrupt Mask 2 1 0 0 11 1 Mask used for state 03, 04 system can be activated by an enable interrupt command. I Mask 3 o 0 0 0 1 1 Mask used for state 02, 05 l.J When an interrupt is recognized, the computer Mask 4 o 0 0 0 0 1 Mask used for state 01 automatically stores the return address in the storage I' location reserved for that interrupt state. If 32K Main Program State 02 Program multilevel indirect mode has been selected, bIt 15 of the LJ storage location is set or cleared to record the current Set mask register to Mask 1 Store registers state of the overflow indicator. If 65K multilevel Enable interrupt Set mask to Mask 3 r indirect mode has been selected, all 16 bits are required Enable interrupt ~ to save the return address. Thus, the program must check for an overflow condition with an SOV or SNO r instruction and record this condition for restoration of Inhibit interrupt the overflow indicator. In both 32K and 65K modes the Replace registers L interrupt system is de-activated and control is Exit interrupt 02 transferred when the interrupt occurs. In 32K mode r-' the overflow is cleared, while in 65K mode the SOV or State 01 Program State 03 Program SNO instruction must first be executed. The program ~ Store registers then stores all registers, including the mask register, Store registers Set mask to Mask 4 Set mask to Mask 2 in addresses reserved for this interrupt state and loads r Enable interrupt Enable interrupt the mask register with the mask to be used in this state. The Is in the mask indicate the interrupts that have a ~ higher priority than the interrupt being processed. The mask should not have a 1 in the position of the interrupt Inhibit interrupt Inhibit interrupt being processed; this would lose the return link. The Exit interrupt 01 Replace registers •. .-l program then activates the interrupt system and C Exit interrupt 03 processes the interrupt. r-' State 04 Program State 05 Program The computer exits from an interrupt state when the Ll program inhibits the interrupt and restores the Store registers Store registers Set mask to Mask 2 Set mask to Mask 3 registers (including the mask register). After loading r-' the register, the program executes the exit interrupt Enable interrupt Enable interrupt command with delta equal to the lower eight bits of the l.J base address of the interrupt state. This command reads the storage location where the return address is I' sto/red. The overflow indicator is set or cleared as specified by bit 16. The interrupt system is activated Inhibit interrupt Inhibit interrupt ~ and control is transferred to the return address. Replace registers Replace registers Exit interrupt 04 Exit interrupt 05 r LJ EXAMPLE I' The following listing and sample program steps apply L if there were five different possible interrupts and three levels of priority: I Interrupt 01 High priority L.J 02 Mid-priority 05 } 03 I' } Low priority l_j 04 (-,I

LJ 96767850 A 5-18 [ o

PROGRAM PROTECT STORAGE PARITY ERRORS RELATED TO PROGRAM PROTECTION The CYBER 18-10M computer has a program protect system to protect a program in the computer from any If a nonprotected instruction is attempting to write into other nonprotected program alsa in the computer. The storage and a storage parity error is present or occurs, system is built around a program protect bit contained the word in storage is not altered and a Storage Parity o in each word of storage. If the bit is set, the word is Error interrupt is enabled. an operand or an instruction of the protected program. All operand and instruction locations of the protected If a protected instruction is attempting to write into program must have the program protect bit set. None storage and a storage parity error occurs, the word is c of the instructions or operands of the nonprotected written into storage and a Storage Parity Error program can have the program protect bit set. interrupt is enabled. c Whenever a violation of the program protect system, If the computer attempts to execute a SPB or CPB other than a direct storage access violation, is detected, instruction and a storage parity error occurs, these the program protect fault flip-flop is set and an internal become Pass instructions and a storage parity error interrupt is generated. A violation indicates that the interrupt is enabled. o nonprotected program has attempted an operation that could harm the protected program. o SET/CLEAR PROGRAM PROTECT BIT PROGRAM PROTECT VIOLATIONS The program protect instructions (SPB or CPB) and the bounds instructions (LUB and LLB) are the only way in o The following are the program protect violations: which the program protect bit may be set or cleared in each word of storage. • A nonprotected instruction attempts to write in a protected storage location. The contents of the [J storage location are not changed. • An attempt is made to write into a protected PROGRAMMING REQUIREMENTS storage location via external storage access when The following program requirements must be met: a nonprotected instruction was the ultimate source c of the attempt. The contents of the storage • The program package that handles all interrupts location are not changed. for the nonprotected program must be completely • An attempt is made to execute a protect ed checked out. This program must also be part of c instruction following execution of a nonprotected the protected program. instruction. The protected instruction is executed • The protected program must be a completely as a nonprotected selected stop instruction. checked-out program. However, it is not a violation if an interrupt c caused this sequence of instructions. • An attempt is made to execute the following instructions when they are not protected: any PERIPHERAL EQUIPMENT PROTECTION interregister instructions with bit 0 = 1, EIN, TIN, EXI, SPB, CPB, or any miscellaneous All peripheral equipment that is essential to the instructions (OBxx). Those instructions become a operation of the protected program must have a bit in nonprotected selective stop instruction under these the FeR to designate if the device is protected. If the 0' circumstances. bit is set, the peripheral device responds with a reject to all nonprotected commands (except status request) Program protect is enabled by setting bit 8 in the func addressed to it. All protected commands have a c tion control register. If this bit is not set, then none normal response. If the bit is not set, the peripheral of the above violations are recognized, with the excep device responds in the normal manner to protected tion of the external storage access protect violation. and nonprotected commands. C ---"\ (J

C 96767850 A 5-19 o r

INPUT /OUTPUT Bit (A Register) Function Operation When referencing the input/output devices, the Q register should contain either 009016 or 009116 06 ADT Mode Auto-data transfer according to the foHowlng table:· operation LJ Computer instruction 07 Not used Q Register Output from A Input to A 08 Select Write An output operation; r Mode does not clear the 0090 Write Read alarm status. 0091 Director Function (1) Director Status (2) 09 Select Read An input operation Mode 10 Connect Printer Select a mode of operation in which the r DIRECTOR FUNCTION (1): printer (with the paper tape punch, when used) Bit and the tape reader (A Register) Function Operation (when used) are both connected to the 00 Clear ControHer Clear all interrupt controller. Data read requests. Clear busy, from the paper tape in interrupt, data, alarm, this mode will also be and manual interrupt printed (and punched). [ conditions. Select read mode. Connect printer. 11 Not used Any interrupt request 12 Not used bit wlll take precedence 13 Disconnect Select a mode of c .~ over this function. Printer operation in which the Clear Controller is also printer (and paper tape used in conjunction with punch when used) is bits 11, 12, 14, and 15. disconnected from the 01 Clear Interrupt Clear all Interrupt controller. Data read requests and the manual from paper tape is not interrupt. Any interrupt printed (or punched). L_, request bit will take This mode allows precedence over this non-ASCn codes and function. binary information to be transmitted to the 02 Data Interrupt Send an interrupt signal computer. Request whenever a data status is active. 14 Not used

03 End-of-Operation Send an interrupt 15 Not used Interrupt Request signal when the controller is not busy. All nonconflicting functions may be performed simultaneously. Select write mode and select read I In the EOP state the L-l controller will accept a mode are rejected when the controller is busy. other mode change. functions are always performed. When several functions are issued simultaneously and some of them can be 04 Alarm Interrupt Send an interrupt performed, the output from the A instruction exists Request signal when the Lost normally (Reply), but those functions that should be Data Status is active. rejected are not performed. When none of the functions r' 05 Not used can be performed, the output from the A instruction is rejected. ('

5-20 96767850 A {1 L ]

~ l_.:\~ DIRECTOR STATUS (2): Bit ~1 (A Register) Status Description -J Bit (A Register) Status Description 07 Parity Error A parity error occurred

00 Ready Unit is ready. 08 Release Release reserve o interrupt; this interrupt 01 Busy Read mode - The is generated when the controller is in the CRT or TTY has been process of receiving a' reserved for the panel c character from the interface and is returned. TTY/CDT, or the holding register 09 Read Mode The controller is contains data for conditioned for input o transfer to the operation. computer. The busy 10 Reserved Indicates if the TTY or status will drop upon CRT is currently completion of the data assigned to the panel transfer. interface and is Write mode - The data unavailable to the TTY register contains data controller. o and is in the process of 11 Manual A manual interrupt has transferring it to the Interrupt occurred. TTY/C DT. The busy status will drop when 12 Not used Always 0 o the transfer is 13 Not used Always 0 completed. 14 Not used Always 0 02 Interrupt An interrupt condition [J exists in the controller. 15 Not used Always 0 03 Data Read mode - The holding register contains AUTO·DATA TRANSFER o data for transfer to the computer. The data Auto-data transfer (ADT) provides for pseudo direct status will drop when memory transfers of data blocks to or from a device. the transfer is At the macro level, the transfer appears as a direct completed. c memory access (DMA) transfer. At the micro level, Write mode - The the 1700 emulator processes each data interrupt and ,n controller is ready to inputs or outputs the next data in a Singular fashion. U accept another character Thus, ADT takes less time than input/output via the from the computer. INP, OUT, or SIO instructions, but more time than a true DMA transfer. 04 Always the inverse of c busy (bit 01) To accomplish an ADT for a particular device, perform 05 Alarm Parity error or lost data the following: or field error (no stop bit when expected) 1. The device and its controller must adhere to the c occurred. auto-data transfer specifications in the Micro programmable Computer I/O Specification. 06 Lost Data The holding register '1 contained data for 2. The macro programmer must execute a DMI LJ transfer to the computer, instruction. This command specifies where and the TTY/CDT began the block of data is, how long it is, the direction to send a new sequence. (input/output), and the device's address.

96767850 A 5-21 o r L

/1 C _J 3. The ADT operation is then initiated by an INP, 2. ADT Table for Multiple A/Q Devices: r--" OUT, or S10 instruction as specified by the particular device. l.. j 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Equipment r' While the ADT operation is in progress, the emulator 0 0 0 0 0 1 0 1 0 1 0 0 0 No. Is executing instructions. After each instruction is ~ executed, interrupts are checked. When the particular r 2 T15 Tl-1 TU Tn TlO 1r9 1r8 T7 r6 1'5 T4 1r3 r2 [1'1 To ADT micro interrupt becomes the highest active 12 r interrupt, the next data is input or output. Mter the interruption, the next instruction is executed, except 3 T31 rrro T29 T28 1r27 [fa; tr2) tra! rrm rz T2l TID r19 T18 rry' T16 L) when another interrupt is active. r-"" 4 Not Used When the ADT operation is completed (or if there is an L error), a macro interrupt is generated. The macro 5 0 1 I%l 0 I%l EqUipment Station/Director programmer may then disable the ADT micro interrupt C No. r or initiate another ADT operation to or from the device. FWA-l and CWA For MOS devices, an SPS instruction must be 6 ~ performed to clear the macro interrupt. r ...... 7 LWA The following are the four types of ADT tables specified L by DMI instructions. 8 Not used t"-""

I 1. ADT Table for a Single A/Q Device: L, ~ :

15 0 r· .-I "--. .~; 1 + 1 0 Equipment 0 Station/Director ~ 0 l7cl IZ1 Statton/Director ..... C No. * r 2 FWA-l and CWA ~ ~ FWA-l and CWA l . *..... 3 LWA ~ LWA r"~' l'..... L .. 4 Not used '1 ~ Not used ..... * r

l~-, This type of ADT table consists of 1*4+4 words, where I is the number of multiple A/Q devices (up to 32) on r one micro interrupt. 1:.j

i' LI

! l_.J

r-' C'·_,• _J l:..J 5-22 96767850 A [ o

3. ADT Table for the Clock.

15 14 13 12 11 10 7 8 o c Station / Director o 2 Clock Counter 3 Clock Limit o 4 Not used c· o o CJ c

C.J fl L..; c c o

96767850 A 5-23 o r

r-'

I l.J

) t......

r l-i CYBER 18-20 COMPUTER CHARACTERISTICS AND 6 CYBER 18-30 TIMESHARE SYSTEM

MODEL DESCRIPTIONS The 18-20 e mulates the basic as well as the enhanced 1700 instruction set. Basic features of the processor are The CYBER 18-20 Com puter and CYBER 18-30 Time hardware multiply/divide, 16 levels each of micro and share system provide all features of the CYBER 18-10M, macro inte rrupts , auto-data transfer, a real-time clock, a nd are upward- compatible product set members of the de adstart facil ity from peripn..e rals, an A/Q I/o port that CYBER 18 Series of small systems. supports up to nine pe ripheral controlle r s, and a DMA I/O port that supports up to four DMA-type devices. Feature options are 512- through 4096-instruction read/ write micro memory with minimum instruction exe CYBER 18-20 PROCESSOR cution time of 168 nanoseconds for user micro pro grams, a programmable micro/macro breakpoint con The CYBER 18- 20 (figure 6-1) is a micro- programmable troller, and a breakpoint panel. The 18-20 includes a processor unit that accommodates from 32,768 to cabinet, operators panel, power supplies, an I/ O con 262, 144 eight-bit bytes (one protect a nd one parity bit are troller to support the 1811-1 Console Display, and a provided for each two bytes) of MaS main memory with flexible disk drive with controller. No main memory an effective r ead/ write cycle time of 750 nanoseconds. or read/ write micro memory is included.

Figure 6-1. Typical CYBER 18-20 Configuration

96767850 A 6-1 CYBER 18-30 TIMESHARE SYSTEM module drive with controller, a 300-line-per-minute printer, a 300-card-per-minute card reader, one nine The CYBER 18-30 (figure 6-2) consists of dual micro track, 25 ips, NRZI magnetic tape transport, and programmable processor units, each accommodating a communications multiplexer. Feature options of from 32, 768 to 262, 144 eight-bit bytes (one protect bit the CYBER 18-30 Timeshare system include addi and one parity bit for each two bytes) of MOS main mem tional main memory, synchronous and asynchronous ory with an effective read/ write cycle time of 750 nano communications line adapters, additional magnetic seconds. Each pro.cessor can address the memory of the tape transports, user terminals (CRT or TTY), and other for a total capability of 524,288 eight-bit bytes of additional storage module drives. main memory. The processors emulate the basic as well as the enhanced 1700 instruction set. Basic features of each processor are hardware multiply/ divide, 16 levels each of micro and macro interrupts, auto-data transfer, a real-time clock, deadstart facility from peripherals, an A/Q I/O port that supports up to nine peripheral con trollers, and a DMA I/O port that supports up to four 1870-1 512 INSTRUCTION MICRO MEMORY DMA devices. The 1870-1 micro memory provides storage for up to The CYBER 18-30 Timeshare system provides a 512 32-bit micro control instructions for the processor. basic configuration that is sized for 16 concurrent The memory is a r e ad or write RAM (random-access users. The basic CYBER 18-30 Timeshare system me mory) and can be loaded externally or under 'control provides one 64K byte processor, one 128K byte pro of the micro program. It is designed for micro pro cessor, one 1811-11 Conversational Display Terminal, gram storage in those applications that requi re that the two cassette tape units, one 25 million byte storage processor be programmed at the micro level.

F igure 6- 2. Typical CYBER 18- 30 Timeshare Configuration

6-2 96767850 A o

1870.2 2048 INSTRUCTION MICRO MEMORY and program protect bits are generated and tested in the interface cards. The two interface cards handle up to The 1870-2 micro memory provides storage for up to four stacks (256K bytes) in the main CYBER 18-20 or 2048 32-bit micro control instructions for the processor. CYBER 18-30 chassis. The interlace cards also pro The memory is a read or write RAM and can be loaded vide the dual-CPU access capability used in the CYBER externally or under control of the micro program. It 18-30 dual processor system. o is designed for micro program storage in those appli cations that require the processor to be programmed at the micro level. o CENTRAL PROCESSORS The description of the CYBER 18-10M central processor 1882.16 MOS MAIN MEMORY STORAGE applies to the CYBER 18-20 and 18-30, with the addi o tions of a memory page file. The memory page file The 1882-16 provides 32,768 eight-bit bytes of read/ provides 64 nine-bit words that specify the most sig n write MOS memory. One protect bit and one parity bit nificant seven bits of the 18-bit memory address (512K I ' are provided with each two bytes. The effective read/ byte memory addressing). The total memory is divided write cycle time is 750 nanoseconds. It occupies one into 128 4K-byte pages. memory position within the processor unit. o MACRO INSTRUCTION SET 1882.32 MOS MAIN MEMORY STORAGE The following macro level instructions are provided n The 1882-32 provides 65,536 eight-bit bytes of read/ with the CYBER 18-20 and 18-30, in addition to those u write MOS memory. One protect bit and one parity bit provided with CYBER 18-10M: are provided with each two bytes. The effective read/ write cycle time is 750 nanoseconds. It occupies one • APM (OBOB16) - Absolute page mode is specified. [J memory position within the processor unit. Only the first 128K bytes of memory can be addressed. • PMO (OBOC16) - Page mode 0 is specified. Seg n ments of 2048 words (totaling 128K bytes can be w 1874.1 ECC MOS ARRAY, 192K BYTES addressed via the 32 page mode 0 registers. • PM1 (OBOD16) - Page mode 1 is specified.. Seg The 1874-1 provides storage for the five-bit error cor ments of 2048 words (totaling 128K bytes can be n rection code (ECC) for up to 192K eight-bit bytes of addressed via the 32 page mode 1 registers. LJ 1882-16/1882-32 read/write MOS memory. The ECC facility corrects single bit errors and detects double • WPR R (OB23 16' OB43 16' ..• OBE316) - Write bit errors. All interlace control to ECC module is the contents of register R (bits 0-8) into the page perlormed by the MOS memory interlace module. The register specified by bits 10 through 15 of regis ECC module occupies one memory position within the ter R. Bit 10 is 0 or 1 for a page mode 0 or 2 processor unit. It limits the maximum memory size register, respectively. Bits 11 through 15 specify ,11 of the 18-20/18-30 processors to 192K eight-bit bytes. one of the 32 page registers. Bit 9 is unused and I should be O. l-l • RPR R (OB2416' OB4416, . . . OBE416) - Read the contents of the page register. specified by i1 MAIN MEMORY bits 10 through 15 of register R. into the A regis u ter. Bit 10 of register R is 0 or 1 for a page mode Main memory for the CYBER 18-20 and 18-30 consists o or 1 register, respectively. Bits 11 through 15 of 32K- or 64K-byte MOS memory stacks and two inter specify one of the 32 page registers. Bits 0 face cards. The interlace cards provide the control and through 9 are unused and should be zero. nu interlacing required for CPU/memory function and peripheral (DMA) equipment/memory functions. Parity • ECC R (OB2516• OB4516, ... OBE516) - Input fl the ECC status of the memory word, specified by l, the address in register R, into the A register. r· J ~ 96767850 A 6-3 o MICRO INSTRUCTION FORMATS

Each micro memory address specifies the location of two micro instructions. Each 32-bit micro instruction is divided into five main sections and is numbered from left to right as bits 0 to 31. The M field specifies one of three addressing modes to Function be used to obtain the next micro instruction pair from 1ill!. micro memory and specifies the format to be used in 0,1 Mode (M) field specifies format of S and C interpreting bits 19 to 31 of the micro instruction as field and sequencing mode to obtain next follows: micro instruction pair. Format for 2-15 ALU control field specifies ALU operation, M Addressing Mode Bits 19 to 31 sources of operands, and destination of result of operation. 00 Return Format 1 16-18 Test (T) field specifies method of selecting 01 Sequential Format 1 which micro instruction of next micro 10 Jump Format 2 instruction pair to execute. 11 Sequential Format 3 19-23 Special (S) field specifies subformat selec tion and special operation. 24-31 Constant (C) or suboperation field specifies Figure 6-3 shows all the micro instructIon formats. constants or other codes. Note that format 1 and format 2 mIcro instructions have two subformats, which are selected by the value of bit The total instruction appears as follows: 19 (SF).

o 12 6 7 910 1213 1516 18 -- --1 I M I F I A I B I D I T I I -----I I I I I

SHIFT AND I SCALE I I I I .------__ ------_.I r- ... I o 1 +19 20 2324 31+ ~ SF S C

R 0 S C' fOOl FORMAT 1 ~ S 1 S ~T T' C"

(7Ol J 0 S NMA FORMAT 2 ~ J 1 PAGE NMA S NK S C FORMAT 3

Figure 6-3. Micro Instruction Formats

6-4 96767850 A (·1 L~ .~ The S field specifies operations, such as main memory The ALU control fields specify the sources of two oper read or write operations, or alternate codings to be (-) ands on which an arithmetic, logical, shift, or scale used in the A, B, and D fields. The TIT' bit specifies operation is to be performed and specify the destination Ll that the code in the T field is to be interpreted as the of the result of the operation. For arithmetic and logi normal T code (T IT'=O) or as the alternate T' code cal operations, the ALU control fields consist of the (TIT'=I). The subformat select bit, bit 19, determines ALU function (F), A source (A), B source (B), and n whether bits 25 through 31 are to be interpreted as C' destination (D) fields, shown as follows: u codes or as C" codes. The C' code can contain a con stant for driving the bit generator, additional informa tion to control the main memory read or write, or other 2 6'7 9JI0 1213 15 operations. The C" codes are associated with o F A I B I D I transforms.

11 Format 2 is specified when the M field contains 10 (jump U For shift and scale operations, the A and B fields are mode) as follows: interpreted as follows: Format 2 .19 20 2324 31 nI I U 2 6 7 8 9 1011 1213 15 S NMA F H I I o - 111 PAGE I NMA I The F field specifies shift or scale operation. Bits 7 and 8 specify right or left shifting. Bit 9 specifies If a jump is specified to a micro instruction pair within whether the A register alone or the A and Q registers the same micro memory page, the subformat select bit togeth~r are to be shifted or scaled. Bit 10 is not used, is OJ bits 20 to 23 contain a special operation code as in and bits 11 and 12 specify the shift control code. The D format 1. Bits 24 through 31 contain the micro memory field contains a no-operation code for shift and scale address of the next micro instruction pair. The sub [J operations. format select bit is 1 when a jump is specified to a dif ferent m~cro memory pagej bits 20 through 31 contain The T field is the conditional branch of the micro the complete micro memory address of the next micro o instruction and specifies which micro instruction, upper instruction pair. or lower, of the next micro instruction pair to execute. The test can be based on the result of the ALU opera Format 3 is specified when the M field contains ·11 tion of the current micro instruction or on some other (sequential mode), as follows:

I ...-..I condition • Format 3 The codings in the Sand C fields depend upon the con tents of the M field. The S and C fields are coded in 1920 23 24 31 three formats. Format 1 is specified when the M field C contains 00 (return mode) or 01 (sequential mode) as t~ S l follows: Format 1 This format allows one special operation to be per formed as specified by the S code and also causes the 31 eight bits of the C field to be transferred to the N regis ter (bit 19=1) or to the K register (bit 19=0). S

1920 23 24 25 l-.J 1_11 _ S/PAGE IliJT'I l --'

-JI

96767850 A 6-5 ] L .... -,

C-J

\'--

I U r I l'r"

[ STANDARD PERIPHERALS 7

The following paragr aph s descr ibe standa r d peripherals for the CYBER 18 product line. The a va ilability of a give n pe r ipheral w ith respect to the CYBER 18- 05 , 18- 10M, 18- 20, and 18- 30 Ti meshare products can be determined by referring to the configuration drawings at the end of this section.

1811-1 CONSOLE DISPLA Y

The 1811-1 shown in figure 7- 1 is a self- c')ntained, s ingle- s tat ion CRT keyboard d is play te r m inal. It pro vides a 1920- chara cter (24 line s of 80 cha racters) d is play unit with characte r -by- chara cte r , line- a t-a time, o r page- a t- a - t ime data transmission in e ithe r ha lf or full duplex mode . The data r ate is s electa.ble from 110 to 9600 bits pe r s econd . The inte rface mects nS232- C and CClTT. V24 r ecommenda ti ons a s applied to Figure 7-1. 1811-1 Cons ole Display asynch ronous data communication. The character reper toi re inc ludes 128 symbols di sp layed w ithin a 9 by 7 dot ma.trix.

1811-2 OPERATORS CONSOLE

The 1811- 2 shown in figure 7-2 is a self- contained. single station CRT keyboard display terminal. It pro vides a 1920- character (24 I ines of 80 characters per l ine) display. a 95 - character a lphanumeric kcyboard that inc ludes control functions a nd numeric pad. and character- at- a - time tr ansmission in ha Ir or fu ll d uplex mode. in page or scroll mode . The data rate is select able fr o m 110 to 9600 bits per second . 'I1w communica t io n inte rface mcct s RS232- C a nd CC I TTV. 24 r ccom men mendations . The console inc ludes the cables r equired fo r connection to the processor .

This product is not a va il able with systems tilat use the F igllre 7- 2 . 1811-2 Ope r ato r s Console 1890 -1. 1890- 2. or 1890- 3 batch termina l contro lwar e . The 1811 - 1 Console Dis play is r equired whe r e the 1828-1 CARD READER/LINE PRINTER ba tch contr ol\\'a 1'e is used . CONTROLLER

The 1828-1 provide s two inde pendent controllers fo r connection of one cru·d r eade r and / o r one line printe r to the proce ssor unit; it occupies one A/ Q card position

96767850 A 7-1 within the processor unit. Card reader controller fea tures are data/control interlace b~tween the processor and one card reader; it accepts card reader input data in form of Hollerith code, binary code, or any other desired format; it provides facil ity for deadstart opera tion of the processor unit; it perlorms Hollerith- to ASCII code conversion during deadstart operation; and it perlorms normal data transfers under program con trol. The line printer controller features are datal control interlace between the processor and one line printer; it perlorms data transfers under program con trol; and it has data buffer facility. An additional fea ture is the test mode capability of closed-loop operation under software control for diagnostic purposes. Cables are included as part of the ca r d reader or line printer.

1828-2 CARD READER/LINE PRINTER CONTROLLER/COMMUNICATION LINE ADAPTER

The 1828-2 provides two independent controllers for Figure 7-3. 1829-30 Card Reader the connection of one card reader and/ or one line printer to the processor. It provides one communica tion line adapter for the processor, and occupies one read speed, 1000 card hopper/ stacker capacity, an position in the processor. 80-column punch card input medium, and a photo electric read station with light/dark read checking The card reader accepts Hollerith, binary, or other facility. One 7-foot interace cable is supplied. The code formats, provides a facility for processor dead 1829-30 operates from 120 V ac, 60 or 50 Hz source start, and perlorms Hollerith-to-ASCII conversion power. Option 1888-1 is available for 220 Vac during deadstart. operation.

The line printer provides a data buffer facility and test mode using loop-back to card reader control under software supervision. 1829-60 CARD READER

The communication line adapter provides interlace to The 1829-60 is a self-contained desk top unit provided synchronous or asynchronous modems that conform to with interlace control logic and an operator control/ EIA RS232-C or CCITT RFC V.24 standards. It pro indicator panel. Functional characteristics of the unit vides asynchronous baud rates of 110, 150, 300, 600, are 600 card-per-minute read speed, 1000 card/hopper 1200, 2400, 4800, 9600, and 19,200, and synchronous stacker capacity, an 80-column punch card input baud rates of 1200, 2400, 4800, and 9600. It includes medium, and a photoelectric read station with light/ an internal cyclic encoder for checkword generation and dark read checking facil ity. One 7 -foot interlace cable one 20-foot modem cable. is supplied. The 1829-60 operates from 120 V ac, 60 or 50 Hz source power, Option 1888-1 is available for 220 V ac operation.

1829-30 CARD READER

The 1829-30, shown in figure 7-3, is a self-contained 1827 -7 IMPACT PRINTER desk-top unit provided with interlace control logic and an operators control/indicator panel. Functional The 1827-7 shown in figure 7-4 is a desk top line printer characteristics of the unit are 300 card-per-minute with 7 by 7 dot matrix printing. It produces up to four

7-2 96767850 A 1827-60 LINE PRINTER

The 182 7-60 shown in,figure 7-6 is a 600-line-per minute printer in a quieti zed cabinet. Jt prints 63 ASClT characters in up to 132 columns at 10 characters per inch and 6 or 8 line~ pe r inch . 1ne line printer includes an operator control panel. one line buffe r. a test print feature. fault indicators. a pa per basket. one 63 - ASCII character banel. and one 20-foot I/ O cable . It operates on 120 Vac, 50 /-60 Hz .

Figure 7- 4 . 182 7- 7 Impact P r inter

copies plus one origi nal. 'nle impact printer prints up to 132 columns a a nomina l speed of 70 lines PCI' m inute . a nd prints 94 ASC II symbols. Tt inc ludes parity check. a 100- character buffer. a self- test. format tape. a nd 10- foo t I/ O cable. and automatic motor eOl1h',,I.

1827-30/31 LINE PRINTER

111e 1827-30/ 31 shown in figure 7-5 is a 300 line- per minute dru m pr inte r in a quie tized cabinet. It provides full line buffer facility . a 136-column print line, 12 VF U channels, a 64- character print d rum, an:! s ix or eizht line- pe r -inch print line spacing . TI18 1827- 30/ 31 includes 20 feet of interface ca ble . 'The 1827- 30 operates from 120 Vac. 60 Hz sou rce power. The 1827- 31 ope rates from 220 Vac, 50 Hz source power. Figure 7-6. 1827-60 Line Printer

1833-4 CARTRIDGE DISK CONTROLLER

The 1833-4 provides a single direct memory access (DMA) channel connection. The controller has absolute cylinder addressing and a daisy chain capability to control up to four cartridge disk drives with seek overlap in any combination. It has an autoload capability with automatic re-try. The controller includes cables and relay stations, and occupies one DMA position in ~he processor.

Figure 7-5. 1827-30 Line Printer

96767850 A 1866-12 CARTRIDGE DISK DRIVE cabinet and requires an 848-29 Disk Cartridge, which is not included. The 1866-12 is a cartridge disk drive with voice coil positioning. It stores 2.2 million bytes on a fixed disk plus 2. 2 million bytes on a removable surface. The disk has 29 sectors per track and 96 words per sector. 1833-1 STORAGE MODULE DRIVE The average positioning time is 35 milliseconds, the INTERFACE rotational speed is 2400 ri m, and the transfer rate is 156, 000 words per second. The cartridge disk drive The 1833-1 provides a single CPU A / Q-DMA channel includes a floor mount cabinet and requires an 848- 29 interface to the 1833- 3 Storage Module Control Unit. Disk Cartridge, whi::: h is not included. The interface handles all control and status operations via the A/Q channel and all data transfers via the DMA channel. The interface supports the control unit con nection of up to eight 1867 -xx drives in any mix. Con 1866-14 CARTRIDGE DISK DRIVE nection to the 1833-3 control unit is via two 25-foot (7. 62m) cable assembl ies. The interface occupies one The 1866-14 is a cartridge disk drive with voice coil A/Q-DMA position within the processor unit. positioning. It stores 4.4 million bytes on. a fixed disk plus 4 . 4 million bytes on a removable disk. Each disk has two surfaces, 200 tracks per surface, 29 sectors 1833-2 STORAGE MODULE DRIVE per track, and 96 words per sector. The average INTERFACE DUAL CPU positioning time is 35 milliseconds, the rotational speed is 2400 rim, and the transfer rate is 156, 000 words per The 1833-2 provides the A/Q-DMA channel interface for second. The cartridge disk drive includes a floor mount the second CPU in a dual-CPU SMD subsystem. The inte rface handles all control and status operations via the A/ Q channel and all data transfers via the DMA channel. The interface supports the 1833-3 control unit connections of up to eight 1867-xx drives in any mix. Connection to the first' computer' s 1833-1 is via two 25-foot (7. 62m) cable assemblies. The interface occu pies one A/ Q-DMA position within the processor unit.

1833-3 STORAGE MODULE DRIVE CONTROL UNIT

The 1833-3 is the control unit for the 1867-10/11/20/21 Storage Modul e Drives . It provides control for up to e ight drives in any ill ix of 25 million 8-bit bytes and 50 million 8-bit bytes of formatted data capacity. The control unit handles all SMD data transfers, formatting, and error recovery. It provides for either single or dual CPU connection via the 1833-1 and 1833-2 SMD interface . The control unit is physically housed in the base cabinet of the first SMD in the subsystem. Input power may be either 50 or 60 Hz, 120 or 220 vac, single phase.

1867 -10 STORAGE MODULE DRIVE

The storage module drive is a random-access device, Figure 7-7. 1866 Cartridge Disk Drive using r emovable disk packs as the storage medium. It

7-4 96767850 A has a formatted data capacity of 25 million bytes. The 1833-5 FLEXIBLE DISK DRIVE maximum data transfer rate is 1. 2 million bytes per CONTROLLER second. The average access time is 30 milliseconds. The 1833-5 provides single CPU A/Q-DMA channel The drive includes a base cabinet, one 10-foot A cable interface and control for one or two 1865-1/2 Flexible (daisy chain) and one 20-foot B cable (star). The 876 Disk Drives. The controller is capable of handling all disk pack is not included. The 1867-10 operates from data, control, and status operations via the A/Q channel 120 Vac, 60 Hz source power. The 1867-11 is available, only or buffered data transfers via the DMA channel. which operates from 220 V ac, 50 Hz source power. The controller is capable of reading and writing in e ither the IBM 3740 format (128 b;tes/sector) or the CDC 1700 rotating mass storage format (192 bytes/sector). It occupies one A/Q or A/Q-DMA position within the 1867 -20 STORAGE MODULE DRIVE processor.

The storage module drive is a random-access device using removable disk packs for the storage medium. 1865 FLEXIBLE DISK DRIVE It has a formatted data capacity of 50 million bytes. The maximum data transfer rate is 1.2 million bytes The flexible disk drive (figure 7-9) is a random-access per second. The average access time is 30 milliseconds. device using removable diskettes for the storage medium. The drive includes the base cabinet, one 10-foot A cable It has a formatted data capacity of 256K bytes when using (daisy chain) and one 20-foot B cable (star). The 877 the IBM format (128 bytes/ sector) or 280K bytes using disk pack is not included. The 1867-20 operates from the CDC 1700 format (192 bytes/ sector). The data trans 120 V ac, 60 Hz source power. The 1867-21 is available, fer rate is 31. 2K bytes per second. The average access which operates from 220 V ac, 50 Hz source power. time is 343 milliseconds. The 1865-1 is the first drive (unit 0) within an FDD subsystem and connects to the 1833-5 via a 10-foot unit 0 cable. The 1865-2 Flexible Disk Drive is the second unit in a dual flexible disk drive subsystem. The 1865-3 and 1865-4 Flexible Disk Drives operate from 220 V ac, 50 Hz source power ani are unit 0 and unit 1, respectively, in an FDD subsystem.

Figure 7-8. 1867 Storage Module Drive Figure 7-9. 1865 Flexible Disk Drive

96767850 A 7-5 1860-1 MAGNETIC TAPE SUBSYSTEM 1860-72 MAGNETIC TAPE TRANSPORT

The 1860-1 (figure 7-10) is a seven-track magnetic tape The 1860-72 is a seven-track magnetic tape transport subsystem that includes the cabinet and the controller. that operates in 800 bit-per-inch NRZI mode, 25 inches The controller features the functional capabilities of per second, and 20K six-bit characters per second. It read record, write record, write filemark, backspace, rewinds at 150 inches per second. The transport does erase, rewind to loadpoint, rewind unload, recovery not include skins and must be housed in an 1860-1 read, and controlled backspace. The magnetic tape ope cabinet. It requires an installation kit (1 860-201) for rates at 25 inches per second, 800 bits per inch NRZI, lower cabinet installation. The 1860-72 operates from with a 20K six-bit character-per-second transfer rate. 120 Vac, 50 or 60 Hz source power. Option 1888-1 is It rewinds at 150 inches per second. The drive is in available for 220 V ac operation. stalled in the upper half of the cabinet. The 1860-1 operates from 120 Vac, 50/60 Hz source power. 1860-2 DUAL MAGNETIC TAPE SUBSYSTEM

The 1860-2 is a dual seven-track magnetic tape sub system that includes the cabinet and controller. The magnetic tape operates at 25 inches per second, 800 bits per inch NRZI mode, with a 20K six-bit character per second transfer rate. It rewinds at 150 inches per second. Both drives are installed in one cabinet. The 1860-2 operates from 120 V ac, 50 or 60 Hz source power.

1860-3 MAGNETIC TAPE SUBSYSTEM

The 1860-3 is a nine-track magnetic tape subsystem that includes the cabinet and controller. The magnetic tape operates at 25 inches per second, 800 bits per inch NRZI mode, with 20K eight-bit character-per second transfer rate. It rewinds at 150 inches per second. The drive is installed in the upper half of the cabinet. The 1860-3 operates from 120 V ac, 50 or 60 Hz source power.

1860-92 MAGNETIC TAPE TRANSPORT

The 1860-92 is a nine-track magnetic tape transport that operates in 800 bit-per-inch NRZI mode at 20K eight-bit characters per second. It rewinds at 150 inches per second. The transport does not include skins and must be house in an 1860-3 cabinet. It requires an installation kit (1860-201) for lower cabinet installation. The 1860-92 operates from 120 V ac, 50 or 60 Hz source power. Option 1888-1 is available for 220 V ac operation. Figure 7-10. 1860-1 Magnetic Tape Subsystem

7-6 96767850 A 1860-4 DUAL MAGNETIC TAPE 1860-95 MAGNHIC TAPE TRANSPORT SUBSYSTEM The 1860-95 is a nine-track dual-mode m :..gnetic tape The 1860-4, shown in figure 7-11, is a dual nine-track transport t.lJ.at operates in 800 bits per inch NRZI mtKle magnetic tape subsystem that inc ~udes th3 cabinet and or 1600 bits per inch ph~s e encoded mode, 50 inches per controller. 1he magnetic tape operates a t 25 inches per second, with 40K and 80K eight-bit character- per-second second, 800 bits per inch NRZI mode, with 20K eig!lt transfer rate. It rewinds at 160 inches per seco!ld. The bit character-per-second transfer rate. It rewinds at magnetic tape transport does not include skins and mu:>t 150 inches pe.r second. Both drives are installed in 0:1'3 b,3 housed in an 1860- 5 cabi~t. The 1860-95 requires an ca~in'~ t. The 1860- 4 operates from 120 Vac, 50 or 60 1860-201 installation '

Figure 7-11. 1860- 4 Dual Magnetic Tape Subsystem

1860-5 MAGNETIC TAPE SUBSYSTEM

The 1860-5, shown in figure 7-12, is a nine-trac!, dual mode magnetic tape subsystem that in::ludes fhe cab:net, formatter, and controller. The magnetic tap.e o~erates at 50 inches per second, 800 bits p'~ r inch NHZI mode, o r 1600 bits per inch phase encoded mode. It ha;, a transfer rate of 40K or 30K eight-bit characters per second, and rewinds at 160 inches per second. The drive is installed in the upper half of the cabinet. Figure 7-12. 1860-5 Magnetic Tape Sub:>ystem

96767850 A 7-7 1860-6 DUAL MAGNETIC TAPE 2400, 4800, and 9600 in the synchronous mode may be SUBSYSTEM selected. The 1843-1 features software selection and control of half duplex or full duplex operation, char The 1860-6 shown in :igure 7-13 is a nine-track dual acte r code lengths of 5, 6, 7 , or 8 bits, stop bit length mode magnetic tape subsystem that includes the cabinet of lx, 1. 5x, or 2x, odd, even, o r no parity bit genera formatter, and controller. It operates at 50 inches per' tion and checking, and variable input/output speeds. second, 800 bits per inch NRZI mode or 1600 bits per An additional feature is an internal cyclic encoder for inch phas·~ enc0ded mode, with a 40K or 80K eight- bit cyclic checkword generation. The 1843-1 occupies one character- per-second transfer rate. It rewinds at 160 A/Q position within the processor unit. On e 20 -foot inches per second. Both drives are installed in one modem cable is supplied. cabinet.

1843-2 EIGHT-CHANNEL COMMUNICATION LINE ADAPTER

The 1843-2 provides interface for up to eight asynchro nous communications devices that conform to CCITT RFC V. 24 or EIA RS232- C standards. It provides baud rates of 75, 110, 150, 300, 600, 1200, and 3600 and switch selectable full or half dup~ex mode. The 1843-2 includes a program-selectable word length of 5, 6, 7, or 8 d~ta 1:lits and 1, 1.5, or 2 stop bits, even or odd parity, and error detection, parity, line break, and buffer overrun. The 1843-2 occupies one card position in the processor.

1850-11500 SERIES EQUIPMENT ADAPTER

Th,e 1850-1 provides interface f.or 1500 Se ries 10M equipments and accommodates an products normally installed in a 1750-1. It includes the CYBER 18 inter fa'Je controller, terminator, power supply, and cable. It interfaces to a 1750-1.

1862-1 PAPER TAPE READ /PUNCH CONTROLLER

The 1862-1 controls paper tape I/ O with FACIT 4020 Figure 7-13. 1960-6 Dual Magnetic Tape Subsystem reader and 4070 punch paper tape devices (non-CDC su;>plied equipment). Data transfer is in 8-bit character mode. The controller occupies O::ll~ position in the pro cessor. Connection to the paper tape devices is by 1843-1 COMMUNICATIONS LINE means of a 15-foot (maximum) cable from the c0ntroller ADAPTER ' to an I/O relay station. Two 5-foot (maximll:n ) cables The 1843-1 controller provides multiplexed dual channel from the relay station connect to tile devices, one cable interfaces for connection of two synchronous or asyn per device. The 1862-1 includes the ca'::Jles ani relay chronous modems that conform to CCITT recommenda station. tions V24 or EIA RS232-C interface standards. A selectable baud rate of 110, 150, 300, 600, 1200, 2400, 4800, 9600, and 19,200 in asynchronous mode or 1200,

7-8 96767850 A "l

- -' "\ .. -..-/ CYBER 18 CONFIGURATOR 1 .1

] CYBER 18-05 1890-2 BATCH TERMINAL CONTROLLER - 2780 CONTROLWARE .200 UT CONTROLWARE l • READ/WRITE MEMORY (16KB) • OPERATOR CRT • COMM. LINE ADAPTER I • CARD READER/LINE PRINTER 1890-3 ...J CONTROLLER - 3780 CONTROLWARE

-, I ! .J J

--, 1827-30 1829-30 I, 300 LPM 1------( OR OR)-----4 300 CPM I ..-'" PRINTER CARD READER

'I I -1 1827-60 1829-60 600 LPM 600 CPM 'I PRINTER CARD READER .J

NOTE: 50 Hz UNITS ARE NOT SHOWN o Figure 7-14. CYBER 18-05 Configurator o I L

96767850 A '1-9 c I

r'~ i I

7153-10 18n-l 1811-2 NON~JMPACT CONSOLE OPERATORS L PRINTER DISPLAY CONSOLE Y r CYBER IS-10M 1865-2 • PROCESSOR FLEXIBLE L • FLEXIBLE DISK CONTROLLER DtSKDMVE ANDDMVE

1827-30 LINE 1882-16 1 'PRlNTER STORAGE INCREMENT, 32K BYTE, MOO L MIN. 32K BYTES MAX. 128K BYTES OR 1882-32 STORAGE INCREMENT r 1827-1\1) 65K BYTE, MOS I LINE 1828-1 L.. PRINTER CARD READER/ - LINE PRINTER FIELD 1860-1 1860-72 CONTROLLER UPGRADE MAGNETIC TAPE, 7-TRACK, MAGNETIC TAPE. ------#' OPTION 1829-30 NR~I - SINGLE TAPE 7-TRACK CARD - L READER 1828-2 CARD ·READER! 1860-2 OR - LINE PRJNTER/ ~ - M~GNETIC TAPE, 7-TRACK, COMMUNICATION NRZI - DUAL TAPE CON'rROLLER L 1829-60 CARD FIELD READER 1860-3 1360-92 UPGRADE' 1870-1 - MAGNETIC TAPE, 9,TRACK MAGNETIC TAPE, #' OPTION 512 x 32-mT NRZI - SlNGLE TAPE 1----- 9-TRACK READ/WmTE MICRO MEMORY

1860-4 ~ MAGNETIC TAPE, 9-TRACK 1871)-2 NRZI - DUAL TAPE 2048 X 32-mT .. _' REAOIWRITE MICRO MEMORY FIELD 1860-5 1860-95 UPGRADE r ~ MAGNETIC TAPE, 9-TftACK -- MAGNETIC TAPE, II1/" OPTION NRZI OR PE - SINGLE TAPE 9-TRACK DUAL mm 1875-2 1875-1 BREAKPOINT BREAKPOINT PANEL CO:,{TROLLER 1860-6 ~ M~GNETIC TAPE, 9-TRACK NRZI OR PE - D~AL TAPE 1850-1 L 1750-1 DCB 1500 SERIES 1866-12 1500 EQUIPMENT ------CARTRIDGE ADAPTER DISKD:!IIVE 1833-4 MAXI MUM ~ CARTRIDGE DISK 4DRI VES 1862-1 ' OR . " FAClT PAPER L PAPER TAPE CONTROLLER PER 1833-4 TAPE EQUIPMENT------READER/PUNCH (USER-FURNISHED) ~. 1866-14 co~rROLLER CARTRIDGE

i DISK DRIVE L) 1843-1 2 LINES, COMMUNICATION SYNC OR ASYNC UNE ADAPTER I I I TOTAL 1890-1 1890-2 1890-3 8 LINES [ 200 u'r 2780 3780 ASYNC 1843-2 1827-7 CONTROLWARE CONTROLWARE CONTROLWARE COMMUNICATION PRINTER ------UNE ADAPTER r I 0573 L.

Figure 7-15. CYBER 18-10M Configurator

I L..i 7.-10 96767850 A c o

753-10 1811-1 A 1811-2 NO~-IMPACT CPNSOLE OPERATORS PRINTER DISPLAY Y CONSOLE CYBEIt 18-20 1865-2 • PROCESSOR FLEXIBLE DISK DRIVE • FLEXIBLE DISK CONTROLLER AND DRIVE r 1827-30 LINE B82-16 PRINTER STORAGE INCREMENT U 32K BYTE, MOS MIN, 32K BYTES MAX. 256K BYTES OR 1882-32 STORAGE INCREMENT 1827-60 65K BYTE, MOS LINE PRINTER 1828-1 l r-- CARD ·READE'R/ flE LD LINE PRINTER 1860-1 1860-72 ~'J PGRADE CO~TROLLER - MAGNETIC TAPE, 7-TRACK, ----- MAGNETIC TAPE, OPTION 1829-30 NRZI - SINGLE TAPE 7-TRACK CARD f-- o READER 1828-2 CARD READER/ 1860-2 OR LINE PRINTER MAGNETIC TAPE, 7-TRACK. -- COMMUNICATIONS - t NRZI - DUAL TAPE CONTROLLER

1829-60 CARD FIE LD 1860-3 1860-92 READER H70-1 UPGRADE MAGNETIC TAPE, 9-TRACK, MAGNETIC TAPE, 512 x 32-BIT - ... ----- ,&/' 0 PTlO~ NRZI - SINGLE TAPE 9-TRACK READ/WRITE MICRO MEMORY

1860-4 - M4.GNETIC TAPE, 9-TRACK, 1870-2 NRZI - DUAL TAPE 2048 x 32-BIT c READ/WruTE MICRO MEMORY FIE LD 1860-5 1860-95 UPGRADE f--- MAGNETIC TAPE. 9-T8ACK, -----. MAGNETIC TAPE, OPnON [) NRZI OR PE - SINGLE TAPE 9-TRACK DUAL MODE V 1875-2 !S75-1 BREAKPOINT BREAKPOINT PANEL CONTROLLER 1860-6 i---- MAGNETIC TAPE, 9-TRACK. NRZI OR PE - DUAL TAPE 185'.1-1 1750-1 DCB 1500 SERIES 1866-12 1500 EQUIPMENT ------ADAPTER CARTRIDGE DISK DRIVE 1833-4 MAXIMUM ~ CARTRIDGE DISK 4 DRIVES 1862-1 FACIT PAPER CONTROLLER OR PER 1833-4 PAPER TAPE TAPE EQUIPMENT------READER/PUNCH (USER-FURNISHED) 1865-14 CmITROLLER CARTRIDGE ~ D~SK DRIVE B74-1 - ECC MOS ARRAY 1843-1 2 LINES, COMMTJ~CATIO~ SYNC OR ASYNC ....., LINE ADAPTER 1867-10 I 8 UNITS STORAGE MODULE TOTAL MAX. -.J 8 LINES DRIVE, 25M BYTES 1843-2 1833-1 I- __ M~£' 1827-7 ___ STORAGE STORAGE,,~-, COMMTJNICA TION t-- PRINTER MODULE DRIVE MODULE DRIVE [OR LINE ADAPTER INTERFACE CONTROL UNIT

1867-20 ] I I I 8 UNITS STORAGE MODULE lx8 2x8 MAX. 1800-1 1890-2 1890-3 DRIVE, 50M lJYTES 200 UT 2780 3780 , CONTROLWARE CONTROLWARE CONTROLWARE I TO/FROM .J 0571 1833-2 (2ND SYST EM)

Figure 7-16. CYBER 18-20 Configurator

96767850 A 7-11 1 -.1 r I L

C,\_J

1811-1 L.; CRT r , ~ p-______J ~__ ------~ ~ I ~ CYBER 18-30 CYBER 18-30 PROCESSOR 1 PROCESSOR 2 CASSETTE (COMMUNICATIONS (TIMESHARING CASSETTE r TAPE TAPE PROCESSOR) PROCESSOR) L, 64KBYTES 128KBYTES ...-.,

L; COMMUNICATIONS 1832-4 MULTIPLEXER MAGNETIC TAPE r-- ~ CONTROLLER (NRZI) L. e16 OPTIONAL ASYNCHRONOUS OPTIONAL EXPANSION COMMUNICA TION liNE ADAPTERS r UP TO 64 e16 OPTIONAL USER CRTs/TTYs } I UNITS L, 1860-92 MAGNETIC TAPE TRANSPORT C'

OPTIONAL EXPANSION r UPT04 UNITS L., 1833-1 STORAGE r MODULE DRIVE 1828-1 L .. INTERFACE CARD 1829-30 - READER/LINE --~ CARD r PRINTER READER I CONTROLLER L 1833-3 STORAGE r MODULE DRIVE CONTROL UNIT w 1827-30 ...... LINE PRINTER r I I 1867-1 G STORAGE MODULE r DRIVE I 25M BYTE L,

r-". 1 Figure 7-17. CYBER 18-30 Timeshare Configurator I C· \-,

~ 7-12 96767850 A [ l J l MACRO INSTRUCTION EXECUTION TIMES A

~(~--" -(\~ "-'!, e. I j ] When calculating the instruction execution times listed 2. For an enhanced storage reference field on the following pages, the user must consider the instruction, add the following address mode time -, I follOWing parameters: to the execution time given in this appendix. .J 1. For basic storage reference instructions, add the Additional following addressing mode time to the execution Addressing Mode Delta Execution Time I time given in this appendix. I -.J 0 ~O .00 Additional Additional Fl Delta Execution Time Fl Delta Execution Time 1 .67 l 0 ~O .00 0 =0 .29 2 .28 l 1 .00 1 ~51 3 .78 : 2 .00 2 .51 Additional Addressln& Mode Delta Execution Time 3 .29 3 .51 0 =0 .22 4 .80 4 .80 1 .72 5 .80 5 .80 2 .72 6 .80 6 .80 3 '1.50 7 .80 7 .80 J 3 • Add .72 microseconds for the following 8 .00 8 • 80 instructions:

9 .29 9 .80 SJI

10 .29 10 .80 ARJ

I 11 .57 11 1.07 SB! ~ 12 .80 12 1.57 ANI

13 .80 13 1.57 LR!

14 .80 14 1.57 OR!

15 .80 15 1.57

o 96767850 A A-I r I G

r (,-,

Execution lJ

\ Mnemonic , De fin ltlon Times VLsec) OP Code r AAB Transfer Arithmetic Sum A, Q+M 1. 74, 1.91,2.08, 0 8 3 8-F ~ 2.25 r AAM Transfer Arithmetic Sum A, M 1. 74, 1.91,2.08, 0 8 2 8-F 2.25 L AAQ Transfer Arithmetic Sum A, Q 1. 10, 1. 34, 1.51, 0 8 3 0-7 r 1.54t LJ ADD ADD A 1. 76 8 o to F .:1- :-" ADQ ADDQ 1. 76 F o to F 1 L ALS A Left Shift 1. 62 + • 056 * N 0 F C/D O-F r---

5.68 0 4 o to F o to F AMr AND Memory 1--.; { A 1 .:1- I r-' AND AND with A 1. 62 A o to F 6 L. 0 4 o to F 10 to F ANr AND Register 5.40 { A 0 .:1-

0 4 to to C ,-.J ARr Add Register 5.40 o Flo F { 8 0 r ARS A Right Shift 1. 62 + .056 * N 0 F 4/5 O-F L. ASC Accumula tor Scale 2. 88 + • 056 * N 0 B 0 A r-' CAB Transfer Complement Logical Product 1. 63, 1.80, 1. 96, 0 8 F 8-F L A, Q+M 2.13t :- CAM Transfer Complement Logical Product A, M 1.63, 1.80, 1. 96, 0 8 E 8-F

I 2.13t l.-J

CAQ Transfer Complement Logical Product A, Q 1. 18, 1. 34, 1.34, 0 8 F 0-7 r 1.51 t L, CBP Clear Breakpoint Interrupt 2.19 0 B 0 '7 r 0 4 O-F O-F CCE Compare Character Equal 6.14 L.. { E 2 .:1- I r 1 t For inter-register instructions, the first execution time is for A or Q register destinations, the second time L.i Is for M, A and M, or Q a'nd M registers, the third time is for A and Q, and the Jourth time for A and Q andM. 1

I l_. C L

A-2 96767850' A I' I LJ ]

--, I I

Executlon Mnemonic Definition Times (J,Lsec) OP Code

0 5 + 6 ! CLF Clear Field 6.64 I I { o to F OtoF ~ .J

CLR Clear to Zero 1. 18~ 1~ 34, 1.34, 0 8 4 o to 7 ] 1.51t CPB Clear Program Protect 1.72 0 7 0 0

0 4 o to F o to F CrE Compare Register Equal 5.23, 5.46tt J { E 0 ~

'I DMt Define Micro Interrupt 3.43 0 B 0 6 I --1 DrP Decrement and Repeat 2. 22ttt 0 6 tttt o to F

DVI Divide Integer 10.48 3 o to F a o EAB Transfer Exclusive OR A, Q, M 1. 63 1. 80, 1. 96, 0 8 7 8 to F 2.13 t

EAM Transfer Exclusive OR A, M 1. 63, 1. 80, 1. 96, 0 8 6 8 to F o t 2.13

EAQ Transfer Exclusive OR A, Q 1. 18, 1. 34, 1.34, 0 8 7 o to 7 [) 1.51t n EIN Enable Interrupt 1. 40 0 4 0 0 u EMS Execute Micro Sequence 6.20ttttt 0 B r,o 2

ENA Enter A .95 0 A a n I u ENQ Enter Q .95 0 C 6- I EOR Exclusive OR with A 1. 62 B o to F a n\ U . I Ext Exit Interrupt State 1. 85 0 E a I

t For "inter-register instructions, the first execution time is for A or Q register destinations, the second time is for M, A and M, or Q and M registers, the third time is for A and Q, and the fourth time for A and Q and M. ttFor compare instructions, the first execution time listed is for unequal conditions, and the second time is for equal conditions. tttAdd. 62 microseconds for the DIP instruction. n tttt I ! 2, 4, 6, 8, A, C, E U tttttPlus micro-seauence time n G (.J,---, r ~ 96767850 A A-3 o r L.

\ ...... __ .. Execution Mnemonic Definition Times (psec) OPCode l_

I"' GPE Generate Character Parity Even 3.92 0 B 0 8 LJ GPO Generate Character Parity Odd 3.92 0 B 0 9

TIN Inhibit Interrupt 1.40 0 5 0 0 I L.J INA Increase A .95 0 9 A I : '3.77 min. INP Input to A t 0 2 A L 15.63 max I INQ Increase Q .95 0 D A 1"" I LJ JMP Jump 1.17 1 o to F A

f' LAB Transfer Logical Product A, Q+M 1. 63, 1. 80, 1.96, 0 8 B 8 to F 2. 13tt ~

LAM Transfer Logical Product A, M 1. 63, 1. 80, 1. 96, 0 8 A 8 to F I' 2. 13tt L.; LAQ Transfer Logical Product A, Q 1.10, 1.34, 1.34, 0 8 B o to 7 1.51tt C- 0 4 o to F o to F .-i LCA Load Character to A 5.80 { C 2 A I 1"" LDA Load A 1.62 C o to F A l-.J I LDQ LoadQ 1.62 E o to F A 1""

5 o to F[4 or C L., LFA Load Field 6.19 + .056 * N {o t: F o to F A - r LLB Load Lower Unprotected Bounds 2.14 0 B r,o 1 w LLS Long Left Shift 2.30 + .056 * N 0 F ElF o to F r LMM Load Micro Memory 2.42 + 3.5 * N 0 B 0 1 L LRG Load Registers 13.80 0 B 0 2 r I I L.. t Maximum time is for Internal reject \ ttFor inter-register instructions, the first execution time is for A or Q register destinations, the second time is for M, A and M, or Q and M registers, the third time is for A and Q, and the fourth time for A and Q L, andM. r'

L.. C

L. A-4 96767850 A r L I ./ I ~

Execution Mnemonic Definition Times (s.&sec) OP Code

0 4 otoFlotoF I LRr Load Register 5.40 { C 0 ~ J LRS Load Right Shift 2.30 + .056 * N 0 F 6/7 o to F l LUB .J Load Upper Unprotected Bounds 2.14 0 B r,o 0 5.62 min. MUI Multiply Integer 2 o to F l 7.49 max. ~ -.J NOP No Operation 1.17 0 F o to 1 o to F

'I I 0 4 o to F o to F OMr OR Memory 5.68 { D 1 ~

0 4 otoFlotoF ORr OR Register 5.40 { D 0 ~

3.49 min. I OUT Output from A 0 3 ~ n 15.63 max. t u QLS Q Left Shift - 1. 96 + • 056 * N 0 F A orB o to F [J QRS Q Right Shift 1. 96 + .056 * N 0 F 2 or 3 o to F RAO Replace Add lin Storage 2.22 D o to F ~ r"I I I RTJ Return Jump 1.69 5 o to F ~ U SAM Skip If A = - 1.23, 1. 52tt 0 1 3 o to F [J SAN Skip If A -:F +0 1.23, 1. 52 tt 0 1 1 o to F -- SAP Skip If A = + 1.23, 1. 52tt 0 I 2 o to F l u SAZ Skip If A = +0 1.23, 1.52 tt 0 1 0 o to F 0 4 o to F o to F SBr Subtract Register 5.47 'I { 9 0 ~ I -.J 0 4 o to F 10 to F SCA Store Character from A 6.53 { C 3 ~ I , t Maximum time Is for internal reject I ttFor skip instructions, the first execution time is for no skip, and the second is for skip. U

96767850 A A-5 o ,...

_..1 ~- I \ '-.. Execution Mnemonic Definition Times (#.&sec) OP Code l-.J ,... 0 5 o to FI7 orF SEF Set Field 6.64 { o to F OtoF A L;

SET Set to 1s 1.18, 1.34, 1.34, 0 8 8 o to 7 I' 1.51t L, 5 o to F 5 or D SFA Store Field 7.15 * .056N {O t~ F o to F A r l..; 5 to F' 13 or B SFN Skip if Field Nonzero 5.85, 6.08tt o {O t: F o to F A ,... 5 to F 12 or A SFZ Skip if Field Zero 5.85, 6.08tt o U {o t~ F o to F A r--- SIO Set/Sample Output or Input 3.88 0 B 0 4 L, 0 4 o to F o to F SJE Subroutine Jump Exit 4.50 { 5 0 A ,...

0 4 o to F 10 to F LJ SJr Subroutine Jump 4.67 { 5 0 A I SLS Select Stop 1.35 0 0 0 0 C ._J SNF Skip on No Program Protect Fault 1.17, 1. 46tt 0 1 B o to F ["' SNO Skip on No Overflow tt 1.17, 1. 46 0 1 F o to F L, SNP Skip on No Storage Parity Error 1. 35, 1. 46tt 0 1 D o to F r-- SOV tt Skip on Overflow 1.17, 1. 46 0 1 A o to F L.

SPA Store A, Parity to A 2.18 7 o to F A r

SPB Set Program Protect 1. 72 0 6 0 l L.,

SPE Skip on Storage Parity Error 1.35·, 1. 46tt 0 1 C o to F r

SPF Skip on Program Protect Fault 1.17, 1. 46tt 0 1 E o to F L r

t For inter-register instructions, the first execution time is for A or Q register destinations, the second time L- is for M, A and M, or Q and M registers, the third time is for A and Q, and the fourth time for A and Q andM. ["' tt For skip instructions, the first execution time is for no skip, and the second is for skip. L r I L_, ( ~, i

l._. A-6 96767850 A r L. o n L'

0 0,48 o to F [~ SrZ Skip if Register Zero 1.91, 2.02 t 0 C

STA Store A 1.69 6 OtoF ~ I c ~ STQ Store Q 1.69 4 o to F I , 9 o to F ~ c SUB Subtract 1. 76 SWN Skip if Switch not Set 1.12, 1.40t 0 1 9 o to F

SWS Skip if Switch Set 1.12, 1.40t 0 1 8 oto F

TCA Transfer Complement A 1. 18, 1. 34, 1.34, 0 8 6 o to 7 1 1. 51tt ...J TCB Transfer Complement Q+ M 1. 46, 1.62, 1. 79, 0 8 5 8 to F 1. 96tt l --.J t For skip instructions, the first execution time is for no skip, and the second is for skip. ttFor inter-register instructions, the first execution time is for A or Q register destinations, the second time l is for M, A and M, or Q and M registers, the third time is for A and Q, and the fourth time for A and Q -l andM.

96767850 A A-7 r J r

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' ..... -~ Execution Mnemonic Definition Times (J.&sec) OP Code L

r-- TCM Transfer Complement M 1. 46, 1.62, 1. 79, 0 8 4 8 to F 1.96t L,

TCQ Transfer Complement Q 1. 18, 1.34, 1.34, 0 8 5 o to 7 1.51t [ TRA Transfer A 1. 18, 1. 34, 1.34, 0 8 A o to·7 1. 51t r

TRB Transfer Q+M 1. 46 1.62, 1. 79, 0 8 9 8 to F L-.J 1. 96 t r-' TRM Transfer M. 1. 46, 1. 62, 1. 79, 0 8 8 8 to F 1. 96t l..J

TRQ TransferQ 1. 18, 1.34, 1.34, 0 8 9 o to 7 1. 51t

XFr Transfer Register 2.47tt 0 7 0, 1 to 7 1 to 7

t For inter-register instructions, the first execution time is for A or Q register destinations, the second time is for M, A and M, or Q and M registers, the third time is for A and Q, and the fourth time for A and Q andM. ttAdd. 67 microseconds for XFI instruction. r-'

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~ MANUAL TITLE CYBER 18 System Summary

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