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TPA2016D2 2.8-W/Ch Stereo Class-D Audio Amplifier With

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TPA2016D2 2.8-W/Ch Stereo Class-D Audio Amplifier With Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPA2016D2 SLOS524E –JUNE 2008–REVISED MAY 2016 TPA2016D2 2.8-W/Ch Stereo Class-D Audio Amplifier With Dynamic Range Compression and Automatic Gain Control 1 Features 3 Description The TPA2016D2 device is a stereo, filter-free Class-D 1• Filter-Free Class-D Architecture audio power amplifier with volume control, dynamic • 1.7 W/Ch Into 8 Ω at 5 V (10% THD+N) range compression (DRC), and automatic gain • 750 mW/Ch Into 8 Ω at 3.6 V (10% THD+N) control (AGC). It is available in a 2.2 mm × 2.2 mm • 2.8 W/Ch Into 4 Ω at 5 V (10% THD+N) DSBGA package and 20-pin QFN package. • 1.5 W/Ch Into 4 Ω at 3.6 V (10% THD+N) The DRC and AGC function in the TPA2016D2 is 2 • Power Supply Range: 2.5 V to 5.5 V programmable through a digital I C interface. The DRC and AGC function can be configured to • Flexible Operation With or Without I2C automatically prevent distortion of the audio signal • Programmable DRC and AGC Parameters and enhance quiet passages that are normally not • Digital I2C Volume Control heard. The DRC and AGC can also be configured to • Selectable Gain from –28 dB to 30 dB in 1-dB protect the speaker from damage at high power Steps (When Compression is Used) levels and compress the dynamic range of music to fit within the dynamic range of the speaker. The gain • Selectable Attack, Release, and Hold Times can be selected from –28 dB to +30 dB in 1-dB steps. • 4 Selectable Compression Ratios The TPA2016D2 is capable of driving 1.7 W/Ch at 5 • Low Supply Current: 3.5 mA V or 750 mW/Ch at 3.6 V into 8-Ω load or 2.8 W/Ch • Low Shutdown Current: 0.2 μA at 5 V or 1.5 W/Ch at 3.6 V into 4-Ω load. The device • High PSRR: 80 dB features independent software shutdown controls for each channel and also provides thermal and short- • Fast Start-Up Time: 5 ms circuit protection. • AGC Enable or Disable Function In addition to these features, a fast start-up time and • Limiter Enable or Disable Function small package size make the TPA2016D2 an ideal • Short-Circuit and Thermal Protection choice for cellular handsets, PDAs, and other • Space-Saving Package portable applications. – 2.2 mm × 2.2 mm Nano-Free™ DSBGA (YZH) Device Information(1) 2 Applications PART NUMBER PACKAGE BODY SIZE (NOM) DSBGA (16) 2.20 mm × 2.20 mm TPA2016D2 • Wireless or Cellular Handsets and PDAs QFN (20) 4.00 mm × 4.00 mm • Portable Navigation Devices (1) For all available packages, see the orderable addendum at • Portable DVD Players the end of the data sheet. • Notebook PCs Simplified Application Diagram • Portable Radios To Battery • Portable Games 10m F AVDD PVDDL PVDDR • Educational Toys TPA2016D2 CIN 1m F INL– • USB Speakers Analog OUTL+ Baseband INL+ or INR– Codec INR+ OUTL– OUTR+ 2 I C Clock OUTR– Digital 2 SCL Baseband I C Data SDA Master Shutdown SDZ AGND PGND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPA2016D2 SLOS524E –JUNE 2008–REVISED MAY 2016 www.ti.com Table of Contents 1 Features .................................................................. 1 9.3 Feature Description................................................. 12 2 Applications ........................................................... 1 9.4 Device Functional Modes........................................ 21 3 Description ............................................................. 1 9.5 Programming........................................................... 21 4 Revision History..................................................... 2 9.6 Register Maps......................................................... 24 5 Device Comparison Table..................................... 4 10 Application and Implementation........................ 29 10.1 Application Information.......................................... 29 6 Pin Configuration and Functions ......................... 4 10.2 Typical Applications .............................................. 29 7 Specifications......................................................... 5 11 Power Supply Recommendations ..................... 32 7.1 Absolute Maximum Ratings ...................................... 5 11.1 Power Supply Decoupling Capacitors................... 32 7.2 ESD Ratings.............................................................. 5 7.3 Recommended Operating Conditions....................... 5 12 Layout................................................................... 32 7.4 Thermal Information.................................................. 5 12.1 Layout Guidelines ................................................. 32 7.5 Electrical Characteristics........................................... 6 12.2 Layout Examples................................................... 34 7.6 I2C Timing Requirements.......................................... 6 12.3 Efficiency and Thermal Considerations ................ 36 7.7 Dissipation Ratings ................................................... 6 13 Device and Documentation Support ................. 37 7.8 Operating Characteristics.......................................... 7 13.1 Device Support...................................................... 37 7.9 Typical Characteristics.............................................. 8 13.2 Community Resources.......................................... 37 8 Parameter Measurement Information ................ 11 13.3 Trademarks ........................................................... 37 13.4 Electrostatic Discharge Caution............................ 37 9 Detailed Description ............................................ 12 13.5 Glossary ................................................................ 37 9.1 Overview ................................................................. 12 9.2 Functional Block Diagram ....................................... 12 14 Mechanical, Packaging, and Orderable Information ........................................................... 37 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (August 2009) to Revision E Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 Changes from Revision C (October 2008) to Revision D Page • Added Feature: 2.8 W/Ch Into 4 Ω at 5 V (10% THD+N) ...................................................................................................... 1 • Added Feature: 1.5 W/Ch Into 4 Ω at 3.6 V (10% THD+N) ................................................................................................... 1 • Added the RTJ (QFN) pin out package.................................................................................................................................. 4 • Changed the RTJ Package Options to the Available Options Table...................................................................................... 4 • Changed ISWS Softwre shutdown 3.6V From: Max 60 to: 70 µA ............................................................................................ 6 • Changed ISWS Softwre shutdown 5.5V From: Max 100 to 110 µA ......................................................................................... 6 • Changed Output offset TYP From 0 mV To: 2 mV................................................................................................................. 6 • Added the RTJ (QFN) package to the Dissipation Ratings Table.......................................................................................... 6 • Deleted Table of Graphs from the Typical Characteristics..................................................................................................... 8 • Added 4Ω Efficiency Graph .................................................................................................................................................... 9 • Added 4Ω Total Power Dissipation Graph ............................................................................................................................. 9 • Added 4Ω Total Supply Current Graph .................................................................................................................................. 9 • Added QFN Output Power Graph......................................................................................................................................... 10 • Added text notes 4 and 5 to the Test Setup for Graphs....................................................................................................... 11 2 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPA2016D2 TPA2016D2 www.ti.com SLOS524E –JUNE 2008–REVISED MAY 2016 Changes from Revision B (June 2008) to Revision C Page • Changed RLOADfrom 6.4 Ω to 3.2Ω ......................................................................................................................................... 5 Changes from Revision A (June 2008) to Revision B Page • Changed Feature High PSRR From: 75 dB at 217 Hz To: 80 dB.........................................................................................
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