Digitally Controlled AGC with Programmable-Gain Amplifier for DVB-T/H

WSEAS TRANSACTIONS on ELECTRONICS Jia-Chun Huang, Muh-Tian Shiue

JIA-CHUN HUANG, MUH-TIAN SHIUE Department of Electrical Engineering, Nation Central University, Digitally Controlled AGC with Jhongli, Programmable-Gain TAIWAN Amplifier for DVB-T/H [email protected], [email protected] Jia-Chun Huang1,∗ and Muh-Tian Shiue2,∗∗ Abstract. This paper describes a digitally controlled automatic gain control (AGC) subsystem for the analog 1 front-endDepartment (AFE) of Electrical supporting Engineering, the Nation digital Central video University, broadcasting Jhongli, in Taiwan DZIF (double conversion with zero second IF) architecture.Abstract. The receiveThis paper path describes contains a digitally a programmable-gain controlled automatic gain amplifier control (AGC) (PGA) subsystem with self-tuning for the analog gain circuit. The dynamicfront-end range (AFE) of the supporting PGA theis 51 digital dB videocontrolled broadcasting by a indigital DZIF (doubleloop to conversion form a first with order zero second control IF) system. The third-harmonicarchitecture. distortion The receive is less path than contains -60 dB a programmable-gain for differential amplifier input signal (PGA) up with to self-tuning 160 mVpp. gain circuit.The supply voltage The dynamic range of the PGA is 51 dB controlled by a digital loop to form a first order control system. The used is 1.8third-harmonic V and the distortionpower consumption is less than -60 dBof designed for differential chip input is signal13 mW. up to The 160 mVpp.nonlinearity The supply of voltagethe proposed design verified byused HSPICE is 1.8 V andpost-layout the power consumption simulation of is designed better chipthan is -60 13 mW. dB Theat every nonlinearity MOS of corner, the proposed which design is suffcient for the systemverified specification. by HSPICE This post-layout chip simulationis fabricated is better on thanTSMC’s -60 dB standard at every MOS 0.18 corner, m 1P6M which isCMOS sufficient technology. for the system specification. This chip is fabricated on TSMC’s standard 0.18 µm 1P6M CMOS technology. Keywords: Programmable-Gain Amplifier, Video Broadcasting, Multimedia Technology

1 Introduction

With the advance of the multimedia technology and the network universalizing, the audio and video information can be transmitted in the binary data. The advances in digital transmission for mobile video-casting are now widespread thanks to the solutions for digital video broad- cast to hand-held devices (DVB-H) and video streaming. Hence the Cell phone with TV receivers can catch the latest news, sports, view your favorite comedy show, or Figure 1. A typical architecture of wideband IF receiver with double conversion. watch cartoons with high quality entertainment even that there is no network access. The DVB-H standard was for- mally adopted as an European Telecommunications Stan- Table 1. DVB-T/H baseband channel requirement [1][2]. dards Institute (ETSI) standard in November 2004 [3]. Furthermore, DVB-H is officially endorsed by the Euro- pean Union as the "preferred technology for terrestrial mobile broadcasting from March 2008 [4]. The concept of the single-chip tuner presented in this paper is based on attempting to capture the advantages and eliminate the disadvantages of some existing architectures. Fig. 1 shows a typical architecture of the double conversion system with zero second IF (DZIF). As its name sug- gests, the DZIF system is a combination of a double conversion superheterodyne and a zero-IF tuner. It is similar ital bitstream to be transmitted being broken down from in structure to that proposed in [1] and [2], with a high one high-rate stream into many lower rate streams. Each rather than a low first IF. The interest RF channel is trans- lower rate stream is transmitted on a separate OFDM sub- lated to higher IF using a tunable LO. Table 1 summa- carrier; using QPSK, 16-QAM, or 64-QAM constellations. rizes the baseband channel requirements for the DVB-T The required signal to noise ratio (SNR) at the receiver de- COFDM modulation scheme and the main requirements pends on the constellation size of QAM. For a bit error rate for this tuner. This receiver RF signal is translated to an (BER) of 10−7 in ADSL system, for example, 64-QAM re- 8MHz signal bandwidth for the required ADC. quires about 27.7 dB whereas 16-QAM only requires 21.5 The COFDM (Coded Orthogonal Frequency Division dB on an additive white gaussian noise (AWGN) channel. Multiplexing) modulation scheme used in DVB-T is well The dynamic range and linearity of the ADC (analog to suited to the difficulties of a terrestrial transmission chan- digital converter) can be briefly defined according to the nel. OFDM is a multi-carrier modulation, with the dig- PAPR (peak to average power ratio) and the averaged sig- ∗e-mail: fi[email protected] nal strength. Unfortunately the PAPR is especially large ∗∗e-mail: [email protected] in multi-carrier systems and hard to calculate precisely in

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wireless system. While the AGC adjusts the averaged sig- overshot which might cause gain error and power waste. In nal strength to a constant level, what importance is to de- the beginning of iteration and optimization shown in Fig.3, termine the reference power level. The paper is relevant one reasonable goal is to minimize a simple function of the to reduce the gain error and minimize the converged time difference between the power of the sampled signal s[k] with the high linearity AGC. and the desired power d2 [14]. For instance, it is a popular cost function to minimize the averaged squared error in the powers of s and d, defined as follows: 2 Digital Feedback Loop AGC J (a) Typically, there are two types of AGC scheme, which are LS 1 feed-forward AGC and feedback AGC. The feedback type = avg{ (s2[k] − d2)2} AGC has the more advantages such as more precise per- 4 1 formance and lower frequency noise. However, the acqui- = avg{(eβa(k) · r(k))2 − d2)2} (1) sition time is rather long because the loop bandwidth is 4 much smaller than the frequency of signal proceeded. In The output signal level of PGA is function of its control a wired communication system with time-invariant chan- signal. The exponential model for PGA is adopted in the nel, it is popular that the feedback type AGC is considered design since the small signal PGA gain a is proportional to [5][6][7][8][9]. For wireless systems, the feedback AGC is the control signal only and independent on the input signal still employed in spite of the fact that the wireless channel r(t). Applying the steepest descent strategy yields is time-variant [10][11][12][13]. dJ (a) a[k + 1] = a[k] − µ LS | (2) da a=a[k] 2.1 VLSI AGC Architecture According to Equ. (2) and (3), the following algorithm is A traditional analog gain control structure is less flexible obtained: than digital one. Fig. 2 show the proposed control architecture to combine the digital gain control loop with a[k + 1] = a[k] − µ · avg{s2[k] − d2} (3) narrow bandwidth and the wide bandwidth analog signal path. Notably, the former need a DAC (digital to analog converter) to convert the digital feedback signal from the 3 PGA in AGC Loop DSP into analog signal. A decoder is used here instead . As mentioned before, the main function of the AGC is to limit the dynamic range of the A/D converter. The re- From Second Mixer 10bit, To Anti-Aliasing Filter quirement of the AGC is to have a large dynamic range. PGA 20Msps It’s tough to use a single VGA to realize a wide dynamic ADC range (DR) of tuning. The three stages of individual PGAs Recitifier to attain the required 51dB gain range is proposed. While some dynamic range is alleviative in the RF-AGC of RF Decoder Integrated & Dump front-end, the rest DR design in baseband is shown in Fig. 5. The priority of the gain partition is considered about the Analog low noise enhancement, but it is also a trade-off between Digital Ref Loop Filter SNR and NF (noise figure).

Figure 2. Block diagram of the proposed AGC 3.1 Schematic of PGA

The PGA cell shown in Fig.4 has a current feedback topology of the circuit [6]. For the system consideration, the 2.2 First Order Approximation Analysis variable gain amplifier with constant bandwidth is what we want. The shunt-shunt structure can provide the im- mutable bandwidth while changing the resistor network Sampler Ra, and the overall voltage gain is ratio of R f a/Ra. The r(t) s(kT) = s[k] a input stage, M6-M9, is the super-source follower provid- ing low output impedance. The variable resistors, Ra and Rb, are two digitally-controlled switched resistor networks Quality as shown in Fig. 6. These resistors are weighted to obtain Assessment a linear-dB gain step with a step size of 1dB. Two resistors Figure 3. Brief diagram of the of AGC networks are been designed for 6 dB of coarse tuning and 1dB of fine tuning. The required resistor values are shown in Table 2. It’s not important to confirm neither the abso- Is there an adaptive element that can accomplish task? lute nor the relative value of the resistors, since the gain of In the past, almost all AGC structures have been con- mismatch which is caused by the process variation can be structed as a first-order loop [5]. Since it can eliminate the fixed by the digital feedback loop.

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V V V V V V BP M6 M10cmfb M5 BP M11 BP cmfb BP

M7 M2

V V R1 Rf1 i+ M8 i- + M vi I/V vo+ Current Cc1 V Amplifier M1 o- Ra Rfa V Rfb Rb vi- I/V vo- o+ Rf2 R2 Iin+ Iin- V V BN M9 M4 M3 BN (a) The brief diagram of PGA circuit

Buffer Current Amplifier Buffer (b) The schematic circuit of PGA Figure 4. The Programmable-Gain Ampliﬁer circuit

Digital Control Bits R1 R2 R3 R4 R5 R6

Vi Vo

PGA PGA PGA

CMFB CMFB CMFB

0dB~24dB 0dB~24dB 0dB~5dB Figure 6. Schematic of Variable Input Resistors Gain step 6dB Gain step 6dB Gain step 1dB Figure 5. Gain Partition of Proposed AGC

Vbp Vbp Mb0 Mb1 Vcm The high-gain current amplifier has low input Vi+ Vi- impedance and high output impedance with the gain- Mb2 Mb3 Mb4 Mb5 boosting scheme. To enable the capability of common- mode rejection, the second gain stage is implemented us- Vcmfb ing source-coupled pair. Fig. 7 shows the continuous-time Mb6 common-mode feedback which is employed to stabilize the common-mode voltage. The transfer characteristic of the current amplifier is linearized by two fixed resistors, Rfa and Rfb. The open loop gain of the current amplifier Mb7 is summarized as follows:

gmR f Figure 7. Common mode feedback circuitry Aiv = · RL · (gmro) · A2nd (4) 1 + gmR f Table 2. Aiv Common mode feedback circuitry Aclose_loop = (5) 1 + Aivβg Required Resistor Value A A β Resistor Coarse Tune Fine Tune where 2nd is the gain of M2 and M3. From Eq. (5), iv g R1 500Ω 4kΩ should be large enough to assure that the ideal formula of R2 500Ω 500Ω feedback topology is correct. A high Aiv and large feed- R3 1kΩ 550Ω R4 2kΩ 610Ω back resistor Rfa is what the commentary cites above. R5 4kΩ 695Ω R6 775Ω 3.2 Linearity of PGA

The primary issue of this design is the noise analysis of the PGA. There are two part of the noise source, one is

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> 60dB Bias

1063 SRA 1 CA 1

μ m SRA 2 CA 2

SRA 3 CA 3 Figure 8. Simulation PGA’s output two-tone spectrum at 1 Mhz; 500 kHz and 80 mVpp output. The third order intermodulation is less the 60 dB.

1063μm CA -- Current Amplifier the electronic noise source, and another is generated by SRA – Switch Resistors Array the circuit nonlinearity which is also called interference Figure 9. Layout of Programmable-Gain Amplifier noise. Some examples of inherent noise are thermal, shot, and flicker noise. While total harmonic distortion is often used to describe nonlinearities of analog circuits, it is also popular to define third harmonic as the measures of nonlin- ear behavior. The main PGA circuit is the key component of the distortion source, but the resistors and the output buffers which connect two stages are also important. It is not allowed in spite of one of them does not match the specification. The third-order intermodulation simulation of fundamental circuit is shown Fig. 8. It may be a more (a) appropriate parameter to verify the workability of an communication integrated circuit since the signal is averagely spread on the frequency spectrum in a multi-carrier system.

4 Simulation Result (b) Figure 10. AGC close-loop simulation with settling time using Matlab The analog forward path of AGC is fabricated in a TSMC (Taiwan Semiconductor Manufacturing Company) standard 0.18 µm 1P6m CMOS process through the CIC ad- vanced service; Fig. 9. shows the chip layout where all the I/O pads are protected by the ESD circuit which is AC_Response_3 (879x317x16M jpeg) provided by ITRI. Active silicon area for the analog circuit was about 0.25 mm. Fig. 10. shows the AGC output waveform when the input level is 0.22 mVpp. As expected, the output magnitudes are maintained at a constant level of 1 Vpp, and the converge speed is about 14 symbol pe- Figure 11. AC Response of four corner simulation in HSPICE riods. Using 20 Mhz ADC sampling rate, it needs one more symbol periods (one symbol period plus cyclic pre- fix) as the integrated and dump to make sure that it has the invariable gain in one symbol. The minimum voltage 5 Conclusion input needs the longest settling time and the critical converge speed is 14 symbol periods. It still can make the An automatic gain control system with programmable digital circuit work ordinarily. The four-corner (FF/0oC, gain amplifier system has been designed and fabricated FS , SF and SS/80oC transistors model) post-layout sim- in 0.18 − µm CMOS process. Besides, the overall sys- ulations of bandwidth and the maximum gain are revealed tem has been simulated in Matlab with the relative ana- in Fig. 11. Table 3 shows the simulation performance of log PGA mathematical model. There is a small gain error PGA. The proposed design preserves the high linearity and and almost fixity gain jitter due to the digital feedback de- high dynamic gain range with fast settling time. sign. The post-simulation results show the −66dB third-

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Table 3. Programmable Gain Amplifier Performance Summary [5] Chorng-Kuang Wang and Po-Chiun Huang, "An automatic gain control architecture for SONET OC-3 VLSI," IEEE Trans. on circuits and Systems, PartII, vol. 44, pp. 779 - 783, Sep. 1997. [6] C. C. Hsu et al., "“A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier," IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1663–1670, Oct. 2003. [7] K. Findlater, T. Bailey et al., "A 90nm CMOS dual- channel powerline communication AFE for homeplug AV with a Gb extension," IEEE ISSCC Dig. Tech. Pa- pers, pp. 464-465, Feb. 2008. [8] G. Cesura, A. Bosi et al., "A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver," IEEE harmonic distortion and 85n( √v ) with 49 gain dynamic ISSCC Dig. Tech. Papers, pp. 108-109, Feb. 2009. Hz range. [9] Szu-Yao Hung, Kai-Hsiang Chanet al., "A high dynamic range programmable gain amplifier for Home- Plug AV powerline communication system," Proc. Acknowledgment IEEE Int. Symposium Circuits and Systems, Beijing, China, 19-23 May 2013. The author would like to thank Prof. Po-Chiun Huang and [10] Muh-Tian Shiue, Kuang-Hu Huang, Cheng-Chang Yi-Da Wu for their support and encouragement. Besides, Lu, Chorng-Kuang Wang, and Winston I. Way, "A Chia- Wei Su offers a lot of help during the period. Finally, VLSI design of dual-loop automatic gain control for he also expresses his appreciation for Chip Implementa- dual-mode QAM/VSB CATV modem," Proc. IEEE Int. tion Center (CIC) for chip fabrication. Symposium Circuits and Systems, Monterey, CA, 1998. [11] O. Jeon, R.M. Fox, and B. A. Myers, "Analog AGC References Circuitry for a CMOS WLAN Receiver," IEEE J. Solid- State Circuits, Vol.41, No. 10, pp.2291-2300, Oct. [1] Mark Dawkins, Alison Payne Burdett, and Nick Cow- 2006. ley, "A Single-Chip Tuner for DVB-T," IEEE Journal [12] C.-C. Wang, C.-C. Huang al., "70 dB dynamic range of Solid-State Circuits, vol. 38, no. 8, pp. 1307 - 1317, CMOS wideband digital variable gain amplifier for Aug. 2003. AGC in DVB-T/H receivers," Circuits, Systems, and [2] Olujide A. Adeniran, Andreas Demosthenous et al., Signal Processing, vol. 27, no. 3, pp. 367 – 379, June "A CMOS Low-Power ADC for DVB-T and DVB-H 2008. Systems," IEEE International Symposium on Circuits [13] H. Liu, X. F. He al., "A wideband analog-controlled and Systems, vol. 1, pp. 209 - 212, May 2004. variable gain amplifier with dB-linear characteristic [3] European Telecommunications Standards Inst. for 60 GHz application," IEEE Trans. Microw. Theory (ETSI), ETSI EN 302 304 V1.1.1 (2004-11): Digital Tech.,, Vol. 64, no. 2, pp. 533 - 540, Feb. 2016. Video Broadcasting (DVB); Transmission System for [14] C. Richard Johnson and William A. Sethares, Handheld Terminals (DVB-H), 2004. "Telecommunications Breakdown: Concepts of Com- [4] http : //europa.eu/rapid/press − releaseI P − 08 − munication Transmitted via Software-Defined Radio," 451en.htm?locale = en Pearson Prentice Hall, 2003.

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