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Digitally Controlled AGC with Programmable-Gain Amplifier for DVB-T/H

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Digitally Controlled AGC with Programmable-Gain Amplifier for DVB-T/H WSEAS TRANSACTIONS on ELECTRONICS Jia-Chun Huang, Muh-Tian Shiue Digitally Controlled AGC with Programmable-Gain Amplifier for DVB-T/H JIA-CHUN HUANG, MUH-TIAN SHIUE Department of Electrical Engineering, Nation Central University, Digitally Controlled AGC with Jhongli, Programmable-Gain TAIWAN Amplifier for DVB-T/H [email protected], [email protected] Jia-Chun Huang1;∗ and Muh-Tian Shiue2;∗∗ Abstract. This paper describes a digitally controlled automatic gain control (AGC) subsystem for the analog 1 front-endDepartment (AFE) of Electrical supporting Engineering, the Nation digital Central video University, broadcasting Jhongli, in Taiwan DZIF (double conversion with zero second IF) architecture.Abstract. The receiveThis paper path describes contains a digitally a programmable-gain controlled automatic gain amplifier control (AGC) (PGA) subsystem with self-tuning for the analog gain circuit. The dynamicfront-end range (AFE) of the supporting PGA theis 51 digital dB videocontrolled broadcasting by a indigital DZIF (doubleloop to conversion form a first with order zero second control IF) system. The third-harmonicarchitecture. distortion The receive is less path than contains -60 dB a programmable-gain for differential amplifier input signal (PGA) up with to self-tuning 160 mVpp. gain circuit.The supply voltage The dynamic range of the PGA is 51 dB controlled by a digital loop to form a first order control system. The used is 1.8third-harmonic V and the distortionpower consumption is less than -60 dBof designed for differential chip input is signal13 mW. up to The 160 mVpp.nonlinearity The supply of voltagethe proposed design verified byused HSPICE is 1.8 V andpost-layout the power consumption simulation of is designed better chipthan is -60 13 mW. dB Theat every nonlinearity MOS of corner, the proposed which design is suffcient for the systemverified specification. by HSPICE This post-layout chip simulationis fabricated is better on thanTSMC’s -60 dB standard at every MOS 0.18 corner, m 1P6M which isCMOS sufficient technology. for the system specification. This chip is fabricated on TSMC’s standard 0.18 µm 1P6M CMOS technology. Keywords: Programmable-Gain Amplifier, Video Broadcasting, Multimedia Technology 1 Introduction With the advance of the multimedia technology and the network universalizing, the audio and video information can be transmitted in the binary data. The advances in digital transmission for mobile video-casting are now widespread thanks to the solutions for digital video broad- cast to hand-held devices (DVB-H) and video streaming. Hence the Cell phone with TV receivers can catch the latest news, sports, view your favorite comedy show, or Figure 1. A typical architecture of wideband IF receiver with double conversion. watch cartoons with high quality entertainment even that there is no network access. The DVB-H standard was for- mally adopted as an European Telecommunications Stan- Table 1. DVB-T/H baseband channel requirement [1][2]. dards Institute (ETSI) standard in November 2004 [3]. Furthermore, DVB-H is officially endorsed by the Euro- pean Union as the "preferred technology for terrestrial mo- bile broadcasting from March 2008 [4]. The concept of the single-chip tuner presented in this paper is based on attempting to capture the advantages and eliminate the disadvantages of some existing architectures. Fig. 1 shows a typical architecture of the double conver- sion system with zero second IF (DZIF). As its name sug- gests, the DZIF system is a combination of a double con- version superheterodyne and a zero-IF tuner. It is similar ital bitstream to be transmitted being broken down from in structure to that proposed in [1] and [2], with a high one high-rate stream into many lower rate streams. Each rather than a low first IF. The interest RF channel is trans- lower rate stream is transmitted on a separate OFDM sub- lated to higher IF using a tunable LO. Table 1 summa- carrier; using QPSK, 16-QAM, or 64-QAM constellations. rizes the baseband channel requirements for the DVB-T The required signal to noise ratio (SNR) at the receiver de- COFDM modulation scheme and the main requirements pends on the constellation size of QAM. For a bit error rate for this tuner. This receiver RF signal is translated to an (BER) of 10−7 in ADSL system, for example, 64-QAM re- 8MHz signal bandwidth for the required ADC. quires about 27.7 dB whereas 16-QAM only requires 21.5 The COFDM (Coded Orthogonal Frequency Division dB on an additive white gaussian noise (AWGN) channel. Multiplexing) modulation scheme used in DVB-T is well The dynamic range and linearity of the ADC (analog to suited to the difficulties of a terrestrial transmission chan- digital converter) can be briefly defined according to the nel. OFDM is a multi-carrier modulation, with the dig- PAPR (peak to average power ratio) and the averaged sig- ∗e-mail: fi[email protected] nal strength. Unfortunately the PAPR is especially large ∗∗e-mail: [email protected] in multi-carrier systems and hard to calculate precisely in E-ISSN: 2415-1513 109 Volume 10, 2019 WSEAS TRANSACTIONS on ELECTRONICS Jia-Chun Huang, Muh-Tian Shiue wireless system. While the AGC adjusts the averaged sig- overshot which might cause gain error and power waste. In nal strength to a constant level, what importance is to de- the beginning of iteration and optimization shown in Fig.3, termine the reference power level. The paper is relevant one reasonable goal is to minimize a simple function of the to reduce the gain error and minimize the converged time difference between the power of the sampled signal s[k] with the high linearity AGC. and the desired power d2 [14]. For instance, it is a popular cost function to minimize the averaged squared error in the powers of s and d, defined as follows: 2 Digital Feedback Loop AGC J (a) Typically, there are two types of AGC scheme, which are LS 1 feed-forward AGC and feedback AGC. The feedback type = avgf (s2[k] − d2)2g AGC has the more advantages such as more precise per- 4 1 formance and lower frequency noise. However, the acqui- = avgf(eβa(k) · r(k))2 − d2)2g (1) sition time is rather long because the loop bandwidth is 4 much smaller than the frequency of signal proceeded. In The output signal level of PGA is function of its control a wired communication system with time-invariant chan- signal. The exponential model for PGA is adopted in the nel, it is popular that the feedback type AGC is considered design since the small signal PGA gain a is proportional to [5][6][7][8][9]. For wireless systems, the feedback AGC is the control signal only and independent on the input signal still employed in spite of the fact that the wireless channel r(t). Applying the steepest descent strategy yields is time-variant [10][11][12][13]. dJ (a) a[k + 1] = a[k] − µ LS j (2) da a=a[k] 2.1 VLSI AGC Architecture According to Equ. (2) and (3), the following algorithm is A traditional analog gain control structure is less flexible obtained: than digital one. Fig. 2 show the proposed control ar- chitecture to combine the digital gain control loop with a[k + 1] = a[k] − µ · avgfs2[k] − d2g (3) narrow bandwidth and the wide bandwidth analog signal path. Notably, the former need a DAC (digital to analog converter) to convert the digital feedback signal from the 3 PGA in AGC Loop DSP into analog signal. A decoder is used here instead . As mentioned before, the main function of the AGC is to limit the dynamic range of the A/D converter. The re- From Second Mixer 10bit, To Anti-Aliasing Filter quirement of the AGC is to have a large dynamic range. PGA 20Msps It’s tough to use a single VGA to realize a wide dynamic ADC range (DR) of tuning. The three stages of individual PGAs Recitifier to attain the required 51dB gain range is proposed. While some dynamic range is alleviative in the RF-AGC of RF Decoder Integrated & Dump front-end, the rest DR design in baseband is shown in Fig. 5. The priority of the gain partition is considered about the Analog low noise enhancement, but it is also a trade-off between Digital Ref Loop Filter SNR and NF (noise figure). Figure 2. Block diagram of the proposed AGC 3.1 Schematic of PGA The PGA cell shown in Fig.4 has a current feedback topol- ogy of the circuit [6]. For the system consideration, the 2.2 First Order Approximation Analysis variable gain amplifier with constant bandwidth is what we want. The shunt-shunt structure can provide the im- mutable bandwidth while changing the resistor network Sampler Ra, and the overall voltage gain is ratio of R f a=Ra. The r(t) s(kT) = s[k] a input stage, M6-M9, is the super-source follower provid- ing low output impedance. The variable resistors, Ra and Rb, are two digitally-controlled switched resistor networks Quality as shown in Fig. 6. These resistors are weighted to obtain Assessment a linear-dB gain step with a step size of 1dB. Two resistors Figure 3. Brief diagram of the of AGC networks are been designed for 6 dB of coarse tuning and 1dB of fine tuning. The required resistor values are shown in Table 2. It’s not important to confirm neither the abso- Is there an adaptive element that can accomplish task? lute nor the relative value of the resistors, since the gain of In the past, almost all AGC structures have been con- mismatch which is caused by the process variation can be structed as a first-order loop [5].
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