A CMOS Automatic Gain Control Design Based on Piece-Wise Linear Circuits

A CMOS Automatic Gain Control design based on Piece-wise Linear circuits

By David Moro Frías

A Dissertation Submitted to the Program in Electronics Science, Electronics Department in partial fulfillment of the requirements for the degree of

PhD. IN ELECTRONICS SCIENCE

at the

National Institute for Astrophysics, Optics and Electronics June 2013 Tonantzintla, Puebla

Advisors:

Dra. Ma. Teresa Sanz Pascual, INAOE Dr. Carlos A. de la Cruz Blas, UPNA

Abstract

In many electronic systems, a circuit capable of reducing the dynamic range of a signal is needed. An Automatic Gain Control (AGC) system is a complex circuit that maintains its output signal amplitude relatively constant, independently of the input variations. The time response of the AGC must also be constant, in order to maximize the system bandwidth and to reduce acquisition times. In this thesis a novel method to design and implement an AGC loop is presented, based on piece-wise linear (PWL) circuits. This PWL technique is used to design an exponential and logarithmic pre-distortion circuits which are implemented inside the AGC loop in order to have a linear-in-dB system and, as a consequence, to obtain a constant settling time AGC response. Also, two exponential variable gain ampliﬁers (VGA) and a peak detector were designed using the PWL pre- distortion circuits mentioned before. Thus, a complete AGC loop is implemented and tested at the laboratory to probe the validity of the proposed blocks. In Chapter 1 a brief introduction is presented, describing the principal AGC blocks, its basic operation, types of AGCs and ﬁnally AGC applications are mentioned. In Chapter 2 a PWL exponential pre-distortion circuit was proposed, based on current mirrors and a Winner-Take-All circuit. This approach is technology-independent, as it does not rely on the quadratic behavior of MOS transistors in strong inversion, and remains therefore valid for deep submicron CMOS processes, as opposed to former exponential approximations found in literature. Moreover, the proposed exponential pre-distortion circuit is not limited to a certain range of validity. In other words, the range of validity can be extended by adding segments to the implementation, at a cost of area and power consumption. The proposed approach was validated with experimental results from a 6-segment

i ii prototype, which showed a very wide linear-in-dB range of 41.97dB with 2.55dB maximum error. Besides the PWL exponential proposal, two WTA circuits were proposed in order to improve time response to abrupt changes of input signals. Both proposals, WTA I and WTA II, preserve the main characteristics of Lazzaro’s cell, such as compactness and area and power consumption optimization, whereas improving time response. The WTA II showed the fastest time response to abrupt input changes and was therefore used as a main block of the exponential pre-distortion circuit. In Chapter 3, the proposed PWL construction method was expanded to implement a logarithmic circuit based on current mirrors and a LTA. A 6-segment prototype was fabricated and tested, showing an input range of almost 28dB with 1.59dB maximum error. Additionally, the peak detector to be used within the AGC was designed with a WTA based full wave rectifier and an external capacitor. One of the main blocks of an AGC is the variable gain amplifier. In order to take full advantage of the proposed PWL exponential block, two VGAs with wide gain control range were designed, the first one based on the Gilbert cell (VGA I) and the second based on a I-V converter (VGA II). Both VGAs were characterized considering their amplification core and the pre-distortion block as unity. VGA I was designed in 0 .35 µm technology, with a gain variation range and power consumption of 33dB and 5.1mW, respectively. On the other hand, VGA II was designed and implemented in 0 .13 µm technology, and experimental results showed a wider gain variation range (41.94dB) and a lower power consumption (3.1mW). Because of this, the VGA II was used in the final AGC design. PWL implementation shows a not limited exponential range validity, so the gain variation range of the VGA depends practically on the amplifier design itself. So, a careful VGA core design must be taken into account for a wide gain range VGA circuit. Finally, employing all the proposed circuits, an AGC circuit was integrated and tested, as shown in Chapter 4. Experimental results shown almost constant time response around of a few microsecons and a compression factor equal to 3.55. iii

The circuits designed in this thesis were fabricated in 0 .13 µm CMOS technology from STMicroelectronics. Simulation and experimental results were presented in order to validate the fulﬁllment of the objectives proposed in Chapter 1. iv Resumen

En muchos sistemas electrónicos es necesario un circuito que sea capaz de reducir el rango dinámico de la señal a procesar. Un lazo de control automático de ganancia (AGC) es un circuito que mantiene la amplitud de su señal de salida relativamente constante, independientemente de las variaciones de la señal de entrada. El tiempo de respuesta de un AGC debe ser constante, con el objetivo de maximizar el ancho de banda del sistema donde se encuentra el AGC. En esta tesis se presenta un método novedoso para diseñar e implementar un lazo AGC basado en circuitos Piecewise-Linear (PWL). La técnica PWL es utilizada para diseñar un circuito de predistorsión exponencial y logar´ıtmico, los cuales son implementados dentro del lazo AGC para poder obtener un sistema lineal en dB y, como consecuencia, obtener un AGC con tiempo de establecimiento constante. Además, se diseñaron dos amplificadores de ganancia variable exponenciales (VGA) y un detector de picos utilizando los circuitos de predistorsión PWL mencionados anteriormente. As´ı, se implementóun lazo AGC completo, el cual fue medido en el laboratorio para comprobar la validez de los bloques propuestos. En el cap´ıtlo 1 se presenta una breve introducción, describiendo los bloques principales del AGC, su operación básica, tipos de AGC y, finalmente, las distintas aplicaciones de estos lazos. En el cap´ıtulo 2 se propone un circuito de predistorsión exponencial PWL, basado en espejos de corriente y en un circuito Winner-Take-All (WTA). Esta propuesta es independiente de la tecnolog´ıa de diseño debido a que no depende del comportamiento cuadrático de los transistores MOS en inversión fuerte y, por lo tanto, esta propuesta se mantiene válida para procesos CMOS submicrométricos, contrario a las aproximaciones exponenciales encontradas en la literuatura. Más aún, el circuito de predistorsión exponencial propuesto no

v vi estálimitado a un rango de validez dado, es decir, el rango de validez puede ser extendido aumentando el número de segmentos a la implementación, con un costo de área y consumo de potencia. Esta propuesta fue validada con resultados experimentales con un prototipo de seis segmentos, el cual mostróun amplio rango lineal en dB de casi 42dB con un error máximo de 2.55dB. Además del circuito exponencial PWL, se proponen dos circuitos WTA que buscan mejorar el tiempo de respuesta a cambios abruptos en las señales de entrada. Ambas propuestas, WTA I y WTA II, conservan las caracter´ısticas principales de las celdas de Lazzaro, tal como su diseño compacto y bajo consumo de área y potencia, mientras que mejoran el tiempo de respuesta. El WTA II mostró el tiempo de respuesta más rápido a cambios abruptos en las entradas y fue, por lo tanto, utilizado como bloque principal en el circuito exponencial PWL propuesto. En el cap´ıtulo 3, el método de diseño basado en la técnica PWL fue expandido para implementar un circuito logar´ıtmico basado en espejos de corriente y un circuito Loser-Tale-All (LTA). Se fabricóy midióun prototipo de seis segmentos, mostrando un rango de entrada de casi 28dB con un error máximo menor de 1.6dB. Además, se diseñóel detector de picos utilizando un WTA de dos entradas, como rectificador de onda completa, y un capacitor externo al chip. Uno de los bloques principales del lazo AGC es el VGA. Con el objetivo de obtener la máxima ventaja del circuito exponencial propuesto, se diseñaron dos VGAs con amplio rango de control de ganancia, el primero basado en la celda de Gilbert (VGA I) y el segundo basado en un convertidor corriente-voltaje (VGA II). Ambos VGAs fueron caracterizados considerando el amplificador de ganancia variable y el bloque de predistorsión exponencial como una unidad. El VGA I fue diseñado en tecnolog´ıa de 0 .35 µm , obteniendo un rango de variación de ganancia de 33dB con un consumo de potencia igual a 5.1mW. Por otro lado, el VGA II fue diseñado e implementado en tecnolog´ıa de 0 .13 µm , obteniendo como resultados experimentales un mayor rango de variación de ganancia (casi 42dB) y un menor consumo de pontencia (3.1mW), comparado con el VGA I, por lo que el VGA II fue utilizado en el diseño final del AGC. Debido a que la implementación exponencial PWL propuesta no tiene un rango de validez espec´ıfico, la variación de ganancia del VGA depende prácticamente del propio diseño del amplificador. As´ı, se debe vii prestar especial atención al diseño del VGA para poder obtener un amplificador de amplio rango de variación de ganancia. Finalmente, utilizando todos los circuitos propuestos en esta tesis, se integróy midióun lazo AGC, el cual es descrito en el cap´ıtulo 4. Resultados experimentales muestran un tiempo de respuesta prácticamente constante de alrededor de unid- ades de microsegundo. Los circuitos diseñados en esta tesis fueron fabricados en tecnolog´ıa de 0 .13 µm de ST Microelectronics. viii Agradecimientos

En primer lugar quiero agradecer a la Dra. Ma. Teresa Sanz P. por haberme aceptado como su alumno de doctorado, por su apoyo, consejos y paciencia durante el desarrollo de esta tesis. También quiero agradecer al Dr. Carlos A. de la Cruz B. quien fue un gran apoyo todo este tiempo, por aceptarme como su alumno durante mi estancia en la UPNA y porque fue parte fundamental en el desarrollo de esta tesis. Les estoy infinitamente agradecido. Al Dr. Alejandro D´ıaz Sánchez, Dr. Alejandro D´ıaz Méndez, Dr. Mónico Linares Aranda, Dr. Esteban Tlelo Cuautle y Dr. Miguel Angel´ Garc´ıa Andrade por haber sido parte del jurado de mi examen y por sus valiosos comentarios. Un agradecimiento muy especial al Dr. Esteban Tlelo y Dr. Arturo Sarmiento que, sin su invaluable apoyo desde mis estudios de maestr´ıa, todo esto no hubiera sido posible. También quiero agradecer de manera especial al Dr. J. Miguel Rocha y al Sr. Guillermo Luna por todo la ayuda brindada durante el periodo de mediciones en el laboratorio. A mis amigos en el INAOE: Alberto Jesús Gutiérrez (el Betito), Cecilia Tecuatl, Carlos Hernández, César Calleja (Dr. Negro), Daniel Decle, Edgar Col´ın, Eric Silva, Ivick Guerra, Juan Manuel Merlo, Juan Pablo Treviño (Pablito), Julio Hernández (Dr. U Lie), Luis Antonio Carrillo Mart´ınez (Dr. Tigre), Luis Fernando Pérez (el loco), Marisol Basañez, Oscar González, Ricardo Mart´ınez y Sergio Román (Dr. Search)... por todos esos buenos momentos en el INAOE, muchas gracias. A mis amigos en la UPNA: Aintzane Lujambio, Coro Garc´ıa, Ferm´ın Esparza, Javier Vela, Jesús Aguado, Jose Mar´ıa Algueta, Juan JoséCerrolaza, Mikel Ariz,

ix x

Mikel Ugarte y Victoria Ponz... por haber hecho de mi estancia en Pamplona un año inolvidable, eskerrik asko. A mis padres, Agust´ın Moro y Susana Fr´ıas, por todo, por apoyarme y dejarme hacer lo que siempre he querido. ¡MUCHAS GRACIAS! Finalmente al Consejo Nacional de Ciencia y Tecnolog´ıa (CONACyT), por el apoyo brindado para la realización de este trabajo, a través de la Beca para Estudios de Doctorado con número de registro 227989.

David Moro-Fr´ıas (XE1REW) Contents

Abstract i

Resumen v

Agradecimientos ix

1 Introduction 1 1.1 AutomaticGainControlCircuits ...... 2 1.2 AGCApplications ...... 6 1.3 Objectives...... 8 1.4 ThesisOrganization...... 8

2 Exponential Pre-distortion Circuits 11 2.1 Winner-Take-All ...... 12 2.1.1 ProposedWTAI ...... 15 2.1.2 ProposedWTAII...... 18 2.2 PWLExponentialApproximation ...... 24 2.2.1 Exponential Circuit based on Current Mirrors ...... 28 2.2.2 ProposedExponentialCircuit ...... 32 2.2.3 ExperimentalResults...... 36 2.2.4 Conclusions ...... 37

3 AGC Building Blocks 39 3.1 VariableGainAmpliﬁer ...... 39 3.1.1 VGAI...... 41

xi xii CONTENTS

3.1.2 VGAII ...... 44 3.2 LogarithmicAmpliﬁer ...... 51 3.2.1 ProposedPWLLogarithmiccircuit ...... 52 3.3 Detectors ...... 61 3.4 Conclusions ...... 67

4 Automatic Gain Control 69 4.1 AGCLoopAnalysis...... 69 4.2 MatlabSimulationResults ...... 73 4.3 ProposedAGCcircuit ...... 75 4.3.1 AGCExperimentalresults ...... 76 4.4 Conclusions ...... 80

5 Conclusions and Future work 83 5.1 Conclusions ...... 83 5.2 Futurework...... 84

A Circuit implementation of PWL functions 87

B Setup 93 B.1 CurrentsourcesandV-I/I-VConverters...... 93 B.1.1 Currentsources ...... 93 B.1.2 Converters...... 94 B.2 AGCblocksmeasurementsetup ...... 96

List of Figures 105

Bibliography 111 Chapter 1

Introduction

Back in the early days of electronics, the very first Amplitude Modulated (AM) radio receivers required manual adjustment of the volume control in order to reproduce signals of different intensities with the same audible intensity from the speakers. Although there were at the time some devices which automatically regulated the amplification of the signal, they employed moving mechanical parts [1]. In order to find a fully electronic solution, Harold A. Wheeler (which also was an amateur radio operator, with 3QK callsign) designed in 1925 the “Diode Automatic Volume Control (AVC) and Peak Detector”, better known now as Automatic Gain Control (AGC) circuit, which had a fundamental impact on the design of every radio receiver since that time [2]. Wheeler’s invention maintained a constant sound level from a radio receiver while tuning to various broadcasting signals of differing strengths. AM radio receivers incorporating this AVC circuit came into use about 1930, and it has been included in every set since then [3]. Nowadays AGCs are employed in many systems where the input signal amplitude can vary in a wide dynamic range, becoming an important block in electronics design. This thesis is focused on the design and implementation of an AGC circuit based on a PWL method to design the internal loop blocks, such as an exponential and logarithmic circuits. In this first chapter is presented an introduction to the AGC circuits, their characteristics and the actual state of art of these circuits. Then, the common AGC applications and finally the objectives

1 2 CHAPTER 1. INTRODUCTION of the thesis are presented.

1.1 Automatic Gain Control Circuits

The main function of an AGC is to maintain a relatively constant output signal regardless of the input signal variations, so that the following circuits require less input dynamic range [4]. When the input signal amplitude variations are slower than the amplitude changes due to the modulating information, then the AGC can provide a well-defined average level output signal. The time required by the AGC to adjust its gain after input signal changes (settling time) must be constant independent of that change and of the Variable Gain Amplifier gain level. If so, the bandwidth of the AGC is maximized and acquisition times are reduced, ensuring the system stability under all operating conditions [4]. Otherwise settling time is not defined and, as a consequence, the speed response of the AGC is limited by the highest settling time. Therefore, in order to optimize the AGC behavior, the settling time parameter should have a known value independent of the input signal [5]. As an example, if the input is an AM signal, the AGC must not respond to the modulation amplitude changes or it will distort the modulated signal. This distortion is avoided by restricting the AGC bandwidth and, as a consequence, the AGC will respond only to the fading effect which is slower than the lowest frequency of the modulation signal.

Figure 1.1: Characteristic AGC behavior. 1.1. AUTOMATIC GAIN CONTROL CIRCUITS 3

The characteristic behavior of an AGC is shown in Fig. 1.1, where Vin and Vout refer to the input and output signal amplitude, respectively. For low input signals, the AGC does not work and the output signal is linearly related to the input signal. When the input is higher than V 1 and lower than V 2, the AGC keeps its output signal level relatively constant. For signals higher than V 2 the AGC is inoperative again, avoiding in this way stability problems [5].

Figure 1.2: AGC basic block diagram

A block diagram with the basic elements of an AGC system is shown in Fig. 1.2. The input signal is amplified by the Variable Gain Amplifier (VGA), whose gain depends on a control signal Vc . A given output signal parameter, such as carrier amplitude, side-band power or modulation index, is detected and then compared with a reference signal, Vref . The difference between these two signals is filtered and used as the gain control for the VGA. In a general case, input, output and control signals can be either voltages or currents. The VGA gain can be controlled either by a continuous or by a discrete signal. Generally, if the control signal is continuous over time, the amplifier is named VGA. On the other hand, if the gain is digitally controlled, the amplifier is usually called Programmable Gain Amplifier (PGA). Thus, AGC circuits can be divided into analog or digital, depending on the way their loop gain is controlled. Digital AGCs are implemented in many RF systems, such as WLAN receivers [6], and in biomedical applications [7], using a digital signal processor (DSP) to implement much of the AGC function, because of its flexibility design. This type of AGCs digitally controls the VGA gain, where the digital control signal is generally derived from a DSP or by mixed circuit DSP, 4 CHAPTER 1. INTRODUCTION using a PGA or a continuous VGA with a digital to analog converter (DAC) for setting the AGC loop gain. Although PGAs simplify the gain control interface by removing the digital- to-analog converter needed for VGAs in digital AGC loops, the low fixed number of bits used for gain programming limits the gain-step resolution, reducing their performance. Furthermore, analog AGC loops reduce power consumption avoiding the computational burden of the DSP by making a software AGC unnecessary [8]. The analog approach can also reduce the circuit complexity by eliminating digital- to-analog converters for the gain control, thus avoiding the need for calibrated gain states [6]. The AGC described in Fig. 1.2 is a negative feedback system, where the control signal represents the error between the output amplitude and the reference signal. As the input amplitude varies, the control signal varies in order to reduce the error. In fact, the control signal can be obtained in two ways:

• Feedback AGC: As mentioned, the VGA output signal amplitude is detected, compared with a reference level, ﬁltered and then fedback to the VGA.

• Feedforward AGC: The VGA input signal is measured, ﬁltered and then fed to the ampliﬁer. In order to compensate the delay in the control path, a delay of the same value of the path signal is introduced [9]. The basic block diagram of a feedforward AGC is shown in Fig 1.3.

Figure 1.3: Feedforward AGC block diagram.

The feedback AGC loop is the most popular due to its high linearity and the narrower dynamic range needed in the detector. On the other hand, feedforward 1.1. AUTOMATIC GAIN CONTROL CIRCUITS 5 loops needs wider bandwidth and faster settling time, but requires a loop with high linearity and a wide detector dynamic range. Moreover, this kind of AGC is used in high frequency devices [9]. Additionally, AGC circuits can be classified as single or dual loops. There are some specific applications, such as hearing aids (bionic ears) [8] or optical communications systems [10], were fast and slow settling times are required. As expected, loop complexity and power consumption increase because of the different bandwidth double loop response. The most important characteristic parameters of an AGC are [4], [11]:

• Settling Time: Required time to adjust the AGC loop gain in response to an amplitude change in the input signal.

• Attack Time: Period needed by the AGC to respond to an abrupt increment of the input amplitude. It is measured from the moment the input changes until the output amplitude reaches its ﬁnal value with a given tolerance (see Fig. 1.4).

• Release Time: Required time to respond to an abrupt decrement of the input. It is measured from the moment the input changes until the output signal reaches its ﬁnal value with a given tolerance (see Fig. 1.4).

• Compression Ratio: It speciﬁes the gain reduction of the loop caused by an abrupt increase level change in the input signal. It is the ratio between the input and output level change in dB [12].

Input level change (dB) C.R. = (1.1) Output level change (dB) 6 CHAPTER 1. INTRODUCTION

Figure 1.4: Release and Attack time: a) Input AGC signal and b) Output AGC signal

1.2 AGC Applications

AGC circuits are not only used into radio receivers, also are applied from low frequency devices, like audio applications such as hearing aid devices, to high frequency systems like wireless networks. Next will be mentioned some AGC applications systems where AGC loops play an important role. Nowadays the need for hearing aids devices arises exponentially due to the dramatic number of individuals who suffer from some degree of hearing loss [13]. In these systems, an AGC loop is used to adjust the microphone output signal within a desired range, compressing the dynamic range of the input signal in order to protect the user from high transients [14], [15]. This type of circuits need low harmonic distortion components, low power consumption and a narrow bandwidth suitable for audio applications [16]. Also, AGC circuits are critical blocks in communications systems. In applications such as WLAN (Wireless Local Area Network), AGC loops are used to adjust the power transferred to the input of the ADC (Analog-to-Digital Con- verter) in the receiver system. In such systems, analog AGC loops are used to 1.2. AGC APPLICATIONS 7 reduce power consumption, allowing the DSP to be in stand-by mode most of the time [17]. This type of AGCs require narrow bandwidths with high settling time [6]. On the other hand, applications like EPON (Ethernet Passive Optical Net- work) or Software Radio systems require also high settling times but with wide bandwidths responses [18, 19]. In applications like global positioning systems, as GNSS (Global Navigation Satellite Systems) or GPS (Global Position System), low noise AGCs are required. The power of the received signal varies within a large range, and the total gain of the receiver should be adjusted automatically according to it. If the received signal is weak, it should be amplified to a certain strength for an ADC to convert it to a digital signal [20]. Another high frequency application are optic discs, where the amplitude modulation caused by low frequency noise from the servo-engine is suppressed [21]. In oscillators circuits, parasitic effects or mismatch can produce pole displace- ments that causes an amplitude vanishment or distortion increase. In order to restore oscillation amplitude, AGC loops are required [22]. For example, in sinusoidal RC oscillators, an AGC loop is used to stabilize the output sinusoidal signal by balancing the positive and negative feedback paths inside the oscillator circuit [23]. In the case of PLL (Phase-Locked Loops) circuits, their operation is sensitive to the input signal level and, consequently, it is necessary to fix the level at some optimal bias value. This can be done by using an AGC loop preceding the PLL circuit [24]. In medical acquisition systems, the signals from human-body sensors are weak with a spectrum from DC to tens of kHz. The gain of the analog front-end can be selected according to the nature of the signal (for example Electroencephalography or Electrocardiography signals), using an AGC with a digitally-controlled VGA as amplifier [7]. In frequency readout-type resonant sensors, the input is measured indirectly through a resonant frequency variation. These resonant sensors need a self- sustained oscillation loop to maintain the oscillation amplitude and resonant frequency. Active amplitude control is therefore necessary to achieve constant oscil- 8 CHAPTER 1. INTRODUCTION lation amplitude, so AGC loops are used for a time domain amplitude regulation, which is a primary design factor in this type of sensors [25]. Moreover, by using an AGC to monitor the oscillation amplitude, the resonator is not driven into nonlinearity [26]. Also in MEMS (Microelectromechanical system) sensors, such as gyroscopes or angular rate sensors, a stable oscillation of the sensing elements is needed, being it necessary to use an AGC to achieve a constant oscillation amplitude [27], [28].

1.3 Objectives

The main objective of this thesis is to ﬁnd a novel solution to implement a robust and eﬃcient AGC loop in CMOS technology for signal processing in low frequency applications ( < 10 MHz ) by:

• Proposal of a wide-range exponential pre-distortion circuit (up to 40dB of variation range), valid for deep submicron CMOS processes.

• Based on the proposed exponential pre-distortion block, design of a wide gain range (up to 40dB) linear-in-dB VGA.

• Proposal of AGC building blocks (peak detector and logarithmic ampliﬁer) allowing for modular construction of the control loop.

• Based on the proposed building blocks, implementation of an AGC loop with almost constant settling time.

1.4 Thesis Organization

The thesis is organized in ﬁve chapters. In Chapter 1 a general overview of the AGC circuits is shown: basic blocks, types of loops and a brief description of AGC application systems are described. Finally the objectives of the thesis are mentioned. Chapter 2 is dedicated to the design of piece-wise linear (PWL) exponential pre-distortion circuits. First, the proposed PWL design method is described. 1.4. THESIS ORGANIZATION 9

Then two pre-distortion circuits are designed, one based on only current mirrors whereas the second is a current mirror and a winner-take-all (WTA) based pre- distortion circuit proposal. Also two WTA proposed circuits are described, which improves WTA time response for abrupt input signal changes. Experimental results are shown in order to validate the designs developed in this chapter. In Chapter 3 the main building blocks of an AGC loop are described. Two exponential variable gain amplifiers (VGA), based on the PWL exponential pre- distortion circuits described in Chapter 2, are designed. One based on the Gilbert cell and the second based on a I-V converter. Also the proposed PWL construction method is expanded to implement a logarithmic circuit based on current mirrors and a loser-take-all (LTA). Then a full wave rectifier, based on a WTA, with a low-pass filter implemented by an external capacitor is designed in order to obtain a peak detector. Inside this peak detector, the proposed PWL logarithmic circuit is included. Experimental results of the VGA based on the I-V converter and the logarithmic circuit are presented. Finally, in Chapter 4 an AGC circuit is implemented, using the circuits proposed in Chapters 2 and 3. First, an ideal AGC loop is simulated in Matlab, in order to gain insight on the AGC behavior. Then experimental results are shown to validate the objectives proposed in the present chapter. 10 CHAPTER 1. INTRODUCTION Chapter 2

Exponential Pre-distortion Circuits

Exponential pre-distortion circuits are essential building blocks in automatic gain control (AGC) circuits. They are used as part of the control loop to ensure an almost constant time response. Exponential circuits are relatively easy to design using BJT transistors, due to their inherent exponential voltage-current behavior; however, although bipolar transistors are available in standard CMOS technology, they are not optimized, leading to poor performance and limited exponential range. CMOS transistors in weak inversion also have an exponential characteristic but suﬀer from reduced bandwidth, large noise contribution and mismatch issues. As an alternative, exponential pre-distortion circuits are implemented by using approximations involving quadratic and linear terms that can be more easily implemented in CMOS technology. Most of such approximations are based on Taylor series [29] or a division of these series [18], [30]. However, these approximation techniques strongly rely on the square-law characteristic of MOS transistors. In submicron CMOS processes, pseudo-quadratic law is no longer valid, thus requiring more complex structures in order to implement the exponential approximations. In order to avoid this drawback, the use of a novel piecewise-linear (PWL) circuit to implement the exponential function is proposed in this chapter. The range of validity of the PWL approximation can be extended by adding seg-

11 12 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS ments to the implementation, which is straightforward due to the modularity of the circuit. PWL implementations found in the literature rely on differential-pair [31], [32] or current-conveyor [33] topologies and diodes. Another way to implement PWL circuits is by using current mirrors as current rectifiers [34], [35]. The main disadvantages of these approaches is that the error of each PWL segment accumulates and, as a consequence, the PWL function shows very poor accuracy. In this chapter a novel PWL exponential circuit based on current mirrors and a Winner-Take-All (WTA) circuit is proposed. It avoids the error accumulation by separately generating each PWL segment in the function. Current mirrors are used to implement each segment of the PWL exponential function and a WTA is employed to decide which segment will be active according to the input signal of the pre-distortion circuit. Next the general Winner-Take-All (WTA) circuit operation will be explained and two different WTA circuits will be proposed. Then, the general PWL exponential procedure design will be described and two different manners of designing a PWL exponential pre-distortion circuits will be shown, one based only on current mirrors [34] and a new proposal based on current mirrors and a WTA circuits.

2.1 Winner-Take-All

WTA circuits are one of the most important building blocks in neural networks, fuzzy systems and nonlinear filters. The main function of a WTA is to select the highest input signal among multiple inputs. Many WTA configurations can be found in literature, such as voltage-mode configurations based on differential pair structures [36] or on inhibitory and local excitatory feedback loop circuits [37], [38]. The first topology has a complex structure with high power consumption and the two last structures can present stability problems due to positive feedback. There are also many current-mode topologies, as tree-structured configurations based on 2-input WTA blocks connected in parallel [39], WTAs based on current comparators and MOS switches [40] or with circuits that need a reset signal in order to be able to operate [41]. These current-mode topologies also suffer from 2.1. WINNER-TAKE-ALL 13 their complexity and therefore high area and power consumptions. In [42] a very compact and low power consumption current-mode WTA was introduced by Lazzaro et al (Fig. 2.1). Since then, many modifications have been realized to this circuit.

Figure 2.1: Lazzaro WTA

To understand the operation principle, the Lazzaro WTA circuit is choosen due to its simplicity. Consider ﬁrst the case in which all the current inputs are equal: Iin 1 = Iin 2 = Iin 3 = I. In this case Mi 2 ( i = 1 , 2 or 3) transistors sink IC /3 each one. When the input condition changes to Iin 1 = I + ∆ I and Iin 2 = Iin 3 = I, M11 sinks an extra current equal to ∆ I, incrementing the voltage at node V 1 and therefore incrementing the voltage at the common node VC . Now M21 and

M31 must also sink I + ∆ I but Iin 2 and Iin 3 are just I, so the drain voltages of these transistors decrease in order to compensate for the increase in VC . For large values of ∆ I, M21 and M31 enter the triode region, thus lowering V 2 and V 3 to voltages near 0 V . M22 and M32 are then cut oﬀ and, as a consequence,

IC ﬂows only through the winner cell, that is through M12. In order to get a copy of the winning current, Mout is connected to node VC . In this way, the gate to source voltage of Mout is set to the same gate to source voltage as the Mi 1 transistors and drains a current equal to the winning one. In [43], Sekerkiran et al. increased the open loop gain of each cell by adding one transistor, in order to improve resolution, as shown in Fig. 2.2. As mentioned before, Sekerkiran WTA includes a transistor which increments 14 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

Figure 2.2: Sekerkiran WTA

the open loop gain of each WTA cell. This additional transistor ( M13 , M23 and

Mi3 in Fig. 2.2) is connected in a cascode mode with the input transistors of the original WTA (Lazzaro WTA), increasing the resistance at nodes V 1 to V 3, the open loop gain in each cell and, as a consequence, improving resolution [43]. In Fig. 2.3 an individual cell of Lazzaro (Fig. 2.3a) and Sekerkiran (Fig. 2.3b) WTAs in an open loop conﬁguration are shown.

Figure 2.3: WTA Open Loop cells: a) Lazzaro and b) Sekerkiran

The input resistance of each WTA cell is equal to 1 /g mi 1 approximately, for both Lazzaro and Sekerkiran WTAs. In an open loop conﬁguration, the output open loop resistance for Lazzaro cell is equal to the output transistor Mi 1 resistance, r0i1, and for Sekerkiran cell it is equal to gmi 3r01 r03 . The open loop gain ( Av OL ) is given by eqs. (2.1) and (2.2) for Lazzaro and Sekerkiran cells, respectively. 2.1. WINNER-TAKE-ALL 15

Av OL ≅ gmi 1r0i1 (2.1)

Av OL ≅ gmi 1gmi 3r0i1r0i3 (2.2)

Thus, Sekerkiran open loop gain is increased by a gmi 3r0i3 factor. Although open loop gain and, as a consequence, resolution is increased in Sekerkiran WTA, the voltage required at the input nodes for both WTAs is equal to 2 V gs in order to correctly bias each WTA cell. This requirement causes a slow time response for abrupt input changes due to the high swing voltage on input nodes. In order to ﬁnd a solution to this issue, in the next sections two WTA circuits are proposed, based on the same operation principle as Lazzaro WTA.

2.1.1 Proposed WTA I

The ﬁrst WTA proposal is shown in Fig. 2.4 [44]. It consists of n identical cells (n = 3), each with three transistors: Mi 1, Mi 2 and Mi 3 and a DC bias current

IBi (i = 1 ,...,n ). The cells are connected together at the low-impedance common node VC to a DC sink current source named IC . In order to understand the operation principle, consider ﬁrst the case in which all the current inputs are equal: Iin 1 = Iin 2 = Iin 3 = I. In this case Mi 2 transistors sink IB each one, whereas Mi 3 transistors sink the same current ( IC − 3IB )/3. When the input condition changes to Iin 1 = I + ∆ I and Iin 2 = Iin 3 = I, M11 sinks an extra current equal to ∆ I, incrementing the voltage at node V 1 and therefore incrementing the voltage at the common node VC . Now M21 and M31 must also sink I + ∆ I but Iin 2 and Iin 3 are just I, so the drain voltages of these transistors decrease in order to compensate for the increase in VC . For large values of ∆ I, M21 and M31 enter the triode region, thus lowering V 2 and V 3 to voltages near 0 V . M22 and M32 are then cut oﬀ and, as a consequence, so are

M23 and M33. Now IC ﬂows only through the winner cell, so a current IC − IB ﬂows through M13. 16 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

In order to get a copy of the winning current, Mout is connected to node VC . In this way, the gate to source voltage of Mout is set to the same gate to source voltage as the Mi 1 transistors and drains a current equal to the winning one.

Figure 2.4: Proposed WTA I

In Lazzaros implementation [42], the resistance seen at node VC is approximately:

1 RV c ≅ (2.3) gmi 1gmi 2r0i2

where r0,i 2 is the drain-source resistance of transistor Mi 2 while gmi 1 and gmi 2 are the transconductances of transistors Mi 1 and Mi 2, respectively. In this ﬁrst proposal, the additional transistor Mi 3 reduces the resistance seen at node VC through negative feedback. In this way, time response is improved without impacting the cell gain. Note that transistors Mi 2 and Mi 3 form a super source follower [45].

In contrast to Lazzaros circuit, the impedance seen at VC of the ﬁrs proposal is now: 1 RV c ≅ (2.4) gmi 1gmi 2gmi 3r0i1r0i2

Thus, the resistance has been reduced by a factor of gmi 3ro i1. This reduction in output resistance, or resistance at node VC , also occurs in Sekerkiran WTA. The proposed WTA was designed in a 0 .13 µm CMOS process with 2 .5V supply voltage. The width transistors were 1 .33 µm and 2 .66 µm for WMi 1,Mi 2 and WMi 3, respectively. Lengths for all transistors were equal to 0 .4µm . IBi and IC were 2.1. WINNER-TAKE-ALL 17 equal to 10 µA and 50 µA , respectively. Current sources were substituted with simple current mirrors. Fig. 2.5 shows the response of the proposed circuit for sinusoidal input currents

10 µA pp at frequencies of 1 MHz (Iin 1), 2 MHz (Iin 2) and 5 MHz (Iin 3). It is seen that the output current follows the envelope of the input currents, as expected.

Figure 2.5: Simulated input and output current waveforms

As the output resistance is the same in Sekerkiran and the WTA I circuits, there is no really output resistance improvement. Moreover, the 2 V gs input voltage requirement is still needed in this WTA proposal. In order to improve the WTA response to abrupt input signal changes, another topology is proposed in the next section. 18 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

2.1.2 Proposed WTA II

The main disadvantage of Lazzaro, Serkerkiran and WTA I topologies is their high swing voltage input nodes and, as a consequence, a slow response to abrupt input current changes. Moreover, Sekerkiran implementation needs an external voltage to bias the additional transistor. The second WTA proposal consists of n = 3 identical cells, a bias current supply, IB1, and an output transistor, Mout , as shown in Fig. 2.6. If all the current inputs are equal, transistors Mi2 (i = 1 , 2, 3) sink the same bias current IB2, whereas Mi3 (i = 1 , 2, 3) sink the same current IB1/n .

If IIN 1 then increases ( IIN 1 = I + ∆ I and IIN 2 = IIN 3 = I), M11 sinks an extra current equal to ∆ I, thus increasing the voltage at node VA1. M12 and M13 act as voltage followers, so the voltage at node VC is set to VC = VA1 + Vsg,M 12 − Vgs,M 13 . Now M21 and M31 should also sink the same current I + ∆ I, but input currents

IIN 2 and IIN 3 are lower. Thus, in order to compensate for the increase in VC , the drain voltages of M21 and M31 decrease, keeping these transistors in triode region. The voltages VB1 and VB2 also decrease and, as a consequence, M23 and

M33 are turned oﬀ. Now all the bias current IB1 ﬂows through the winner cell, which sets the voltage level at VC . Finally, in order to get a copy of the winning input current, Mout is connected to node VC .

Figure 2.6: Proposed WTA II

Input ( Rin ) and output ( RV c ) resistances, open loop gain ( AV ) and open loop resistance ( ROUT,OL ) of individual cells in the WTA II are shown in Table 2.1, along with the symbolic resistance values of Lazzaro, Sekerkiran and WTA I. 2.1. WINNER-TAKE-ALL 19

Table 2.1: WTA symbolic resistance values WTA Parameter Lazzaro [42] Sekerkiran [43] WTA I WTA II

RIN 1/g m1 1/g m1 1/g m1 1/g m1 1 1 1 2 0 1 1 2 01 RV c 1/g mi gmi r i gmi 1gmi 2gmi 3r0i1r0i3 gmi 1gmi 2gmi 3r0i1r0i2 1/g mi gmi r AV gmi 1r0i1 gmi 1gmi 3r0i1r0i3 gmi 1r0i1 gmi 1r0i1

ROUT,OL r0i1 gmi 3r0i1r0i3 r0i1 r0i1

The input voltage required to activate the winning cell in the WTA II can be as low as Vdsat , in contrast to the required 2 Vgs in the other three topologies, resulting in a faster response to abrupt input changes, as will be shown next.

Experimental Results

A 3-input version of the WTA II was designed and fabricated in 0 .13 µm technology. The circuit operates with a 2 .5V single supply voltage, occupies 47 µm x 41 µm and consumes 261 µW . The current sources in Fig. 2.6 were implemented with wide swing current mirrors, where IB1 and IB2 are equal to 20 µA and 10 µA , respectively. The WTAs proposed in [42] and [43] were also fabricated in the same chip for comparison. The resolution of a WTA circuit is defined as the minimum difference between two voltage values that can be resolved by the WTA structure [46]. It depends on two limitations: random resolution limitation, which is determined by device mismatch, and systematic resolution limitation, which depends on the finite open- loop gain of the WTA cells. The higher the gain of the WTAs, the better the resolution [43]. In order to determine resolution, the input currents for the first and third cell were Iin 1 = 10 µA and Iin 3 = 0 µA . The input current for the second cell, Iin 2, was incremented from 0 to 20 µA . When the value of Iin 2 is lower than 10 µA , the

first cell wins, setting a voltage proportional to the value of Iin 1 at node VC and, as a consequence, draining all the tail current of the WTA. When Iin 2 is greater than Iin 1, the second cell wins, so the voltage at node VC is proportional to Iin 2. Ideally, when Iin 2 becomes greater than Iin 1, the first cell instantly turns off. 20 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

However, during transition both the first and second cells are active. As the value of Iin 2 gets closer to Iin 1, the second cell gradually turns on, drawing a fraction of IC . As Iin 2 increases, the second cell draws more and more current until Iin 2 becomes greater than Iin 1 by a certain quantity and the first cell turns off. So, the value of Iin 1 at which the first cell turns off indicates the resolution of the whole WTA [46]. The resolution was measured at the 20% of V 1 final value (when Iin 2 = 20 µA ).

The input currents and internal voltage ( VB1, VB2 and VB3) swings are shown in Fig. 2.7a and Fig. 2.7b, respectively. As it can be seen, although Sekerkiran WTA has the best resolution, WTA II has a lower internal voltage swing. In Table 2.2 the resolutions measurements for Lazzaro, Sekerkiran and proposed WTA II circuits are shown, as well as the simulation result obtained for WTA I.

Figure 2.7: Resolution response: a) Input currents and b) Internal voltage swing

To test the time response, a square-wave current IIN 1 which varied from 0 to

25 µA and a constant current IIN 2 = 12 .5µA were used, as shown in Fig. 2.8(a).

The third input, IIN 3, was set to 0 A. The voltage swings at the input nodes VA1 and VA2 due to input current changes are shown in Fig. 2.8(b), whereas the time response of the output current is shown in Fig. 2.8(c).

Time response at the inputs is characterized by tin 1(tin 2), which is the elapsed time from the moment IIN 1 changes from low to high level until VA1(VA2) settles to 1% of its ﬁnal value, and tin 3(tin 4), which is the elapsed time from the moment

IIN 1 changes from high to low level until VA2(VA1) settles to 1% of its ﬁnal value. 2.1. WINNER-TAKE-ALL 21

Table 2.2: Measured Resolu- tion responses

WTA Resolution ( µA ) Lazzaro [42] 2.35 Sekerkiran [43] 0.92 WTA I * 1.55 WTA II 1.85

*Simulation result

Figure 2.8: Time response to abrupt input current changes:a) Input currents, b) Input voltage swing and c) Output currents.

Time response at the output is characterized by the rise time, tr,out , and the fall time, tf,out , both measured from the moment IIN 1 changes until the output current

Iout settles to 1% of its ﬁnal value. Table 2.3 summarizes all time responses for the proposed WTA, as well as for Lazzaro’s and Sekerkiran’s implementations. As can be seen, the lower voltage swings at the input nodes of the proposed topology result in a more than 25% faster time response. 22 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

Table 2.3: Time Responses

Time responses ( µs ) WTA tin 1 tin 2 tin 3 tin 4 tr,out tf,out Lazzaro [42] 15.7 21.5 15.5 21.0 20.5 24.5 Sekerkiran [43] 14.3 18.7 18.2 24.8 18.3 26.6 WTA II 12.7 16.3 12.7 16.2 17.9 16.4

Fig. 2.9 shows the experimental input and output current waveforms. A 20 µA amplitude 1 kHz sinusoidal wave, a 7 .5µA DC current and a 20 µA amplitude 3kHz sawtooth current were used as input signals. It is shown that the output current tracks the highest input signal and, as expected, the proposed topology shows faster response when input currents abruptly change.

Figure 2.9: Experimental input and output current waveforms

The parasitic package capacitance of the chip limits the frequency response of the integrated WTAs. For this reason, and to better show the full potential of the WTA II, simulation results in response to input signals of 1 MHz , 2 MHz and

5MHz with an amplitude equal to 10 µA p are shown in Fig. 2.10. As it can be seen, at higher frequencies the WTA II response further improves with respect to other implementations. In Table 2.4 the main characteristics of the WTAs are summarized and com- 2.1. WINNER-TAKE-ALL 23

Figure 2.10: Output simulated response for input waveforms of 1 MHz , 2 MHz and 5 MHz pared. As already mentioned, the lower input voltage required to activate the winning cell in the proposed topology results in faster time response. Further- more, this also reduces the output current error, as maximum error occurs during transitions. All results shown in the table were measured except for the bandwidth (BW), due to the large parasitic capacitances of packaging and experimental setup.

Table 2.4: WTA Parameter Comparison

Parameter Lazzaro [42] Sekerkiran [43] Proposed WTA II

VDD 2.5 2.5 2.5 Time response ( µs ) 24.5 26.6 17.9 Maximum Error ( µA ) 7.85 7.65 4.80 BW @ 1pF (MHz) 544 538 540 Area ( µmxµm ) 32 x 12 40 x 12 47 x 41 Power/cell ( µW ) 63.6 63.5 87.0

The proposed WTA II layout is shown in Fig. 2.11, with an area consumption of 53 µm x 42 µm . Transistors microphotograph are not presented because of the passivation layer at the top of the chip, so layout images are presented. 24 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

Figure 2.11: Proposed WTA II layout

2.2 PWL Exponential Approximation

As mentioned before, exponential approximations implemented with CMOS transistors are employed. These exponential approximations in CMOS technology are mainly based on the truncated Taylor series, implementing the linear and quadratic terms of:

a a2 an a a2 eax = 1 + x + x2 + ... + xn ≈ 1 + x + x2 (2.5) 1! 2! n! 1! 2! As an alternative, pseudo-exponential approximations [18], [30] based on eq. (2.5) can be implemented to increase the input range. These expressions are given by:

1 + ax/ 2 eax ≈ (2.6) 1 − ax/ 2

k + (1 + ax/b )2 eax ≈ (2.7) k + (1 − ax/b )2 However, all these approximations have a limited range of validity. In contrast, a PWL approximation is not limited to a speciﬁc range; instead, it can be extended at a constant error by increasing the number of segments. In Fig. 2.12, the approximations based on eqs. (2.5), (2.6), (2.7) and PWL are shown for 2.2. PWL EXPONENTIAL APPROXIMATION 25 comparison. The valid linear range of the approximations are shown in Table 2.5. For the case of the PWL approximation, equidistant points on the x axis were selected using eight segments.

Figure 2.12: Exponential approximations compared to ex

Table 2.5: Valid Range of Approximations

Exponential Approximation Linear output range @ ±1dB error 2nd Order Taylor, Ec. (2.5) 14.43dB Pseudo-Exponential, Ec. (2.6) 20.16dB Pseudo-Exponential (k=0.82 and b=2), Ec. (2.7) 28.86dB PWL 69.5dB (@ 1dB error)

In the PWL approximation of a nonlinear function, a major issue is the selection of breakpoints to guarantee good ﬁtting. The best choice in the case of an exponential function is to divide the total range with equidistant breakpoints, leading to a set of equal-length segments. Under those conditions, the approximation error in a dB-scale is the same for all the segments, as will be shown next. Let g(x) be the function to be implemented:

g(x) = eax (2.8) 26 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

where a is a constant. And let y(x) be its linear approximation between the breakpoints at X1 and X2, as is shown in Fig. 2.13:

Figure 2.13: Linear approximation y(x) of function g(x) between ( X1, Y 1) and

(X2, Y 2)

y(x) = m (x − X0) (2.9) with

eax 2 − eax 1 m = (2.10) x2 − x1

ax 2 ax 1 e x1 − e x2 X0 = (2.11) eax 2 − eax 1 In a dB-scale the approximation error is deﬁned by:

ǫdB = 20 log [y(x)] − 20 log [g(x)] (2.12)

And therefore given by:

ax 1 ax 2 ax 2 ax 1 ǫdB = 20 log (e x2 − e x1 + e x − e x)

− 20 log (x2 − x1) − 20 axlog (e) (2.13)

The maximum approximation error is then: ea∆ − 1 a∆ ǫ = 20 log − 20 log (e) 1 − (2.14) dB,M a∆ ea∆ − 1 2.2. PWL EXPONENTIAL APPROXIMATION 27

where ∆ = x2 − x1 is the length of the segment. Note that, for a given exponential function, the error in dB only depends on the length of the approximation segment. Thus, if all breakpoints of the approximation are equidistant, the maximum error is the same for all segments. This is illustrated in Fig. 2.14, where a 40dB-range PWL exponential was implemented with 5 segments, leading to a maximum 0 .9dB error. As the breakpoints are equidistant, the length of each segment is given by:

totalrange ∆ = (2.15) n where n is the number of segments.

Thus, for a target error and a given range, the number of segments can be found from Ec. (2.14). As expected, accuracy may be improved at the cost of complexity by increasing the number of segments. This fact can be shown in Table 2.6, where the error in dB of a PWL exponential is shown for diﬀerent ranges and number of segments n. Therefore, unlike commonly used exponential approximations, the PWL implementation is not limited to a certain range of operation.

Figure 2.14: a) 40dB 5-segment PWL exponential with equidistant breakpoints (BP) and b) error of the PWL approximation 28 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

Table 2.6: Total Error for Diﬀerent dB-Ranges and Number of Segments (n)

❍ ❍❍Range ❍❍ 20dB 30dB 40dB 50dB n ❍❍ 2 1.53 3.02 5.36 8.23 3 0.69 1.30 2.47 3.86 4 0.39 0.78 1.41 2.22 5 0.25 0.50 0.90 1.43 6 0.17 0.35 0.63 1.00 7 0.13 0.25 0.47 0.74 8 0.09 0.20 0.35 0.57

2.2.1 Exponential Circuit based on Current Mirrors

In this section a PWL exponential circuit based on the synthesis method presented in [34] is presented. As an example, a 7-segment PWL exponential function was designed. It consists of seven current mirrors ( CM 1 to CM 7) connected in parallel, as shown in Fig. 2.15, to obtain an exponential current IP W L from a linear input current IIN . This input current is copied to each one current mirror CMi (i = 1 ,..., 7) with a multiple-output simple current mirror formed by Mp and M1 to M7. The structure of current mirrors CMi is shown in Fig. 2.16.

Figure 2.15: Exponential circuit based on current mirrors

The transfer function of CMi current mirrors is shown in Fig. 2.17, which in fact is a three segment PWL function, with slope m and break-points I1BK and

I2BK given by: 2.2. PWL EXPONENTIAL APPROXIMATION 29

Figure 2.16: Current mirror (CM) structure

Figure 2.17: PWL block response

m = WM2/W M1 (2.16)

I1BK = Ib CM (WMb /W Ma ) (2.17)

I2BK = I1BK (Ib CM /(1 + m)) (2.18)

where WM1, WM2, WMa and WMb are the widths of transistor M1, M2, Ma and Mb , respectively; Ib CM is the bias current. Although in this design simple current mirrors were chosen not to increment circuit complexity, another type of current mirror can be employed, as wide-swing current mirrors, in order to improve precision. The ﬁrst breakpoint of each CMi determines the beginning of each of the seven segments which make up the exponential PWL function. The slope of each 30 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS segment in the exponential function is the sum of the slopes of all current mirrors whose ﬁrst breakpoint is lower and whose second breakpoint is greater than the start point of the considered segment. Thus, the output currents of each CMi current mirror are added to generate the exponential PWL output current IP W L .

In this way, an exponential PWL output current IP W L is obtained from a linear input current IIN . This PWL exponential implementations was simulated in 0 .35 µm CMOS technology, with a VDD equal to 3 V . Transistor widths, which were obtained from eqs. (2.16), (2.17) and (2.18), are shown ni Table 2.7. The channel lengths of all transistors have the same value L = 1 .2µm to reduce channel-modulation eﬀects.

Table 2.7: Transistor widths

Transistor widths ( µm ) CMi M1 M2 Mb M3, M 4 Ma, Mc 1 104 11 10.5 2 52 2 104 9.5 25 2 52 3 104 15 40 2 52 4 52 16 53.5 32 52 5 52 20 68 32 52 6 26 20 81 32 52 7 26 38 95 32 52

In Fig. 2.18 the PWL exponential current and the individual CMi responses are shown. The variation range of IIN is from 0 to 100 µA , providing an output current variation IP W L from 2 to 80 µA . Ideal exponential and simulated PWL exponential response are shown in Fig. 2.19a, whereas total error is shown in Fig. 2.19b. The linear range is greater than 30dB with a total error lower than ± 2dB. Despite the fact that the PWL exponential circuit was designed with simple current mirrors, the obtained linear range is greater than approximations shown in Table 2.5. The accuracy of the exponential PWL function could be improved by adding more segments to the implementation, at the expense of circuit complexity. In 2.2. PWL EXPONENTIAL APPROXIMATION 31

Figure 2.18: Total PWL Exponential output current and individual CMi currents

Figure 2.19: Simulated a) linear-in-dB ideal and PWL output current and b) total error this case, the function was chosen to be made up of seven segments as a good trade-oﬀ between accuracy and complexity. The main disadvantage of this implementation is that the error of each PWL segment accumulates and, as a consequence, the PWL function shows poor accuracy. In next section a novel PWL exponential circuit based on current mirrors and a Winner-Take-All (WTA) circuit is proposed, which avoids the error accumulation by separately generating each PWL segment in the function. 32 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

2.2.2 Proposed Exponential Circuit

The proposed PWL circuit is based on the use of current mirrors and a WTA circuit, as shown in Fig. 2.20. It works as follows: The input current Iin is copied n times, being n the number of segments to be generated, by means of a multiple- output current mirror ( CM in in Fig. 2.14). Each output is used to generate a segment of the approximation, with its required slope and offset. To this end, a current mirror CM i (i = 1 ,...,n ) is used to add an offset current ( X0 =Ioffset) to Iin and to change the current slope by adjusting the current mirror aspect ratio m. Subsequently, the outputs of the current mirrors CM i are connected to the inputs of the WTA, whose output is equal to the highest input current, thus selecting the proper segment of the approximation. As a result, an approximated exponential function is generated at the output.

Fig. 2.21 shows an implementation of CM i (transistors M1 to M10), and the input current mirror CM in with only one output (transistors MCM In 11 to

MCM In n2 ). Offset current Ioffset is added through transistors M5 and M6 and the slope is set through the aspect ratio m = ( W/L )M9,M 10 /(W/L )M7,M 8. In order to implement the PWL function generator, a PMOS version of the proposed WTA II topology was chosen due to its fast response. It is important to note that the proposed technique is not restricted to the use of a specific WTA. The WTA diagram within the exponential function circuit is shown in Fig. 2.22.

Figure 2.20: Proposed exponential circuit block diagram 2.2. PWL EXPONENTIAL APPROXIMATION 33

Figure 2.21: Current mirror to adjust oﬀset (Ioﬀset) and slope ( m) of a segment

Figure 2.22: WTA diagram within the exponential circuit

To show the functionality of the proposal, a 150 µA output range exponential circuit was designed, which corresponds to a 43 .5dB-range. In order to achieve an error lower than 1dB, a 6-segment PWL exponential function was designed. The breakpoints of the PWL approximation were obtained by dividing 34 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS in an equidistant manner the exponential function. Breakpoint values, shown in Table 2.8, are used to determine each segment slope, m, given by eq. (2.10), and oﬀset X0 given by Ec. (2.11). The slope and DC oﬀset values needed for the generation of each segment in the proposed implementation are also shown in Table 2.8.

Table 2.8: Breakpoints, Slopes and DC Oﬀsets

Breakpoints Segment m X0(µA ) (X1, Y 1) (X2, Y 2) 1 1.00, 1.22 4.98, 2.70 0.37 0.00 2 4.98, 2.70 8.96, 6.00 0.82 1.71 3 8.96, 6.00 12.94, 13.30 1.83 5.68 4 12.94, 13.30 16.92, 30.21 4.12 9.71 5 16.92, 30.21 20.90, 66.95 9.23 13.76 6 20.90, 66.95 24.88, 148.40 20.46 17.74

The circuit was designed in 0 .13 µm CMOS technology, with supply voltage V DD = 2 .5V , bias voltages V n = V p = 1 .2V and all transistor lengths of

0.4µm . Bias current IB1 and IB2, which were implemented with wide swing current mirrors, are equal to 20 µA and 10 µA , respectively. The widths of transistors setting the slope and DC oﬀset in each current mirror CM i are shown in Table 2.9. The widths of all other NMOS and PMOS transistors are 1 .33 µm and 4 .44 µm , respectively. The DC response of the proposed PWL exponential circuit is shown in Fig.

2.23. Fig. 2.23a shows the output current Io i of each CM 1 − CM 6 current mirror versus the input current Iin . Fig. 2.23b shows the output current Iout of the proposed PWL exponential circuit resulting from the selection of the highest current Io i. A 36 .52dB-range exponential function with maximum error of 2 .02dB was obtained (as shown in Fig. 2.24), as opposed to the 43 .5dB-range and 0 .75dB maximum error estimated from Ec.(2.14). The increase in error is due to the systematic gain error of the current mirrors, which causes slope, oﬀset and, as a consequence, segment deviations. In order 2.2. PWL EXPONENTIAL APPROXIMATION 35

Table 2.9: Transistor Dimensions

Segment WM9,M 10 (µm ) WM6,M 6(µm ) 1 0.5 − 2 1.10 0.45 3 2.44 0.75 4 5.49 1.29 5 12.30 1.83 6 27.27 2.36

Figure 2.23: DC response of the proposed PWL exponential circuit: (a) Individual

CM i output currents ( Io i) and (b) PWL Exponential output current Iout

to gain insight into how much the maximum error could be, the relative error between the ideal PWL exponential approximation and the simulation results were obtained, as shown in Table 2.10. The maximum relative error in slopes and oﬀsets is around 12% and the maximum segment relative error is around 15 .8%. 36 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

Figure 2.24: Simulated a) linear-in-dB output current and b) total error

Table 2.10: Relative Error

Segment ǫr,m (%) ǫr,X 0 (%) ǫr,Segment (dB ) 1 3.78 − 1 2 1.83 12.28 0.94 3 7.10 3.17 1.20 4 11.65 2.16 1.27 5 12.67 1.88 0.68 6 9.53 1.52 0.63

2.2.3 Experimental Results

The designed 6-segment PWL exponential function was fabricated in 0 .13 µm CMOS technology. The proposed structure provides a linear-in-dB output current within a 41 .97dB-range with a maximum error of 2 .55dB, as shown in Fig. 2.25. In Table 2.11 a comparison is shown between the proposed topology and previous implementations, which are based on the quadratic-law of long-channel MOS transistors in strong inversion and saturation to generate pseudo-exponential ap- 2.2. PWL EXPONENTIAL APPROXIMATION 37 proximations. The proposed topology reaches the highest dB-range in a 0 .13 µm CMOS process, with an error and area comparable to the other topologies. The implementation in [47] shows wide range and low error. However, note that in deep submicron CMOS processes the quadratic law is no longer valid due to second order eﬀects and, as a consequence, the dB-range of the approximation is reduced. In the case of the proposed circuit, the error can be reduced or the range increased, at a cost of power consumption, by incrementing the number of cells. The proposed circuit layout is shown in Fig. 2.26.

Figure 2.25: Experimental a) linear-in-dB output current and b) total error

Also, PWL exponentials circuits based on Lazzaro and Sekerkiran WTAs were implemented in the same chip were the PWL exponential based on the proposed WTA II was fabricated. Results are shown in Appendix A.

2.2.4 Conclusions

Exponential implementations based on Taylor series approximations depend on CMOS square-law behavior. However, as consequence of technology scaling, the square-law characteristic of CMOS transistors is no longer valid. As a solution, 38 CHAPTER 2. EXPONENTIAL PRE-DISTORTION CIRCUITS

Table 2.11: Performance Comparison of Exponential Circuits

[47] [48] [49] [50] Proposed CMOS process ( µm ) 0.5 0.18 0.5 0.5 0.13

VDD (V) ±1.5 1.2 ±1.5 ±1.5 2.5 Range (dB) 37 38 15 20 41.97 Error (dB) ±0.5 ±1 ±0.5 ±0.5 2.55 Area ( µm x µm ) 85 x 10 170 x 90 − − 203 x 70 Power ( µW ) 200 180 400 220 652

Figure 2.26: Proposed PWL exponential pre-distortion circuit layout in this chapter a PWL exponential approximation was proposed. It is based on a piecewise-linear method which allows for a technology-independent approach, as it does not rely on the ideally quadratic characteristic of MOS transistors in strong inversion and saturation. Instead, the proposed structure is based on simple circuits such as current mirrors and a Winner-Take-All. The modularity of the circuit allows for careful consideration of trade-oﬀ between accuracy, approximation range and number of segments at the design stage. A 6-segment prototype was fabricated in 0 .13 µm CMOS technology. Experimental results show a very wide linear-in-dB range of 41.97dB with 2.55dB error. Chapter 3

AGC Building Blocks

An AGC loop is based on different circuits, such as an exponential variable gain amplifier (VGA), a signal detector and a logarithmic pre-distortion circuit. In this chapter, two VGAs are presented, one of them based on the Gilbert cell and the other one based on a I-V converter. They both were designed to fully exploit the wide variation range of the exponential circuit, which is used as a component of the VGAs to set an exponential gain control signal. A PWL logarithmic pre-distortion circuit is also proposed, based on current mirrors and a Loser-Take-All (LTA) circuit. This logarithmic circuit is included in order to have a constant settling time loop even for abrupt input level changes. Finally a peak detector is presented, based on a WTA as a full wave rectifier and a first order low-pass filter. The proposed PWL logarithmic circuit was included within the detector block in order to obtain a linearized AGC loop later.

3.1 Variable Gain Ampliﬁer

Variable Gain Ampliﬁers (VGAs) are essential blocks in many signal processing circuits and a major component of Automatic Gain Control (AGC) loops. In order to make the settling time of the AGC constant and independent of the input signal level, the VGA must have an exponential gain variation [5]. The gain of a VGA can be controlled by a continuous or by a discrete signal. Generally, if the VGA control signal is continuous over time, the ampliﬁer

39 40 CHAPTER 3. AGC BUILDING BLOCKS is named VGA. On the other hand, if the gain is digitally controlled, then the amplifier is called Programmable Gain Amplifier (PGA). This digital control signal is generally derived from a Digital Signal Processor (DSP) or by a mixed circuit out of the DSP [51]. The VGAs described in this section are controlled by a continuous signal, because of the PGA low fixed number of bits used for gain programming that limits the gain-step resolution and, as a consequence, reduces the performance of the AGC [7]. In implementations reported in literature, the VGA gain is controlled by the following methods:

• By a variable source degeneration resistance [29].

• Varying the bias current [52].

• By digital programable attenuators [53, 54].

The VGAs in which the transconductance is modified by varying the bias current are based on the Gilbert cell, showing good linearity and fast response [52]. However, if a wide gain variation is required, a linearity degradation occurs and the input noise increases above the minimum gain of the amplifier [55]. Another type of VGA is based on non-linear V-I and I-V converters, a differential pair and diode-connected load transistors that increases the amplifier gain

[52]. Due to its structure, the input signal can not be greater than Vgs − VT . The gain of this VGA depends on the input and output currents and the transistor dimensions [55]. The degeneration resistance VGA, based on a differential pair, shows good linearity, low noise figure and a reduced power consumption [29]. The gain depends on the source resistance, so for great amplification factors, large resistors are needed, limiting the bandwidth of the amplifier. This can be improved by reducing the source resistance, but transistors are needed at the input [55]. An- other option is to include gain boosting circuits to increase the input amplifier transconductance, reducing the bandwidth and generating stability problems [52]. Next, two VGAs are proposed which make use of the PWL pre-distortion circuit presented in Chapter 2 to obtain a very wide gain variation range with 3.1. VARIABLE GAIN AMPLIFIER 41 exponential characteristics.

3.1.1 VGA I

The ﬁrst VGA, which will be called VGA I, is based on a Gilbert cell [56], shown in Fig. 3.1.

Figure 3.1: Gilbert cell

This circuit has a diﬀerential input and output, were X and Y refers to a DC level while x and y refers to a time variant signal. The diﬀerential output is given by:

I0 = I01 − I02 (3.1)

where:

I01 = ID1 + ID4 (3.2) and

I02 = ID2 + ID3 (3.3)

Being ID1, ID2, ID3, ID4 the respective transistor drain currents. Transistors M1 to M4 are in saturation region, so by substituting saturation CMOS transistor equation in Ec. (3.1), the diﬀerential output current is:

1 I = k (V gs − V )2 + ( V gs − V )2 − (V gs − V )2 − (V gs − V )2 (3.4) 0 2 1 th 4 th 2 th 3 th From Fig. 3.1, voltages V gs 1 to V gs 4 are: 42 CHAPTER 3. AGC BUILDING BLOCKS

V gs 1 = x + y

V gs 2 = −x + y

V gs 3 = x − y

V gs 4 = −x − y

By substituting these equalities in eq. (3.4), the multiplier response of the Gilbert cell is obtained:

I0 = 4 kxy (3.5)

where k = µnCox (W/L ).

Because of Gilbert cell is a fully diﬀerential circuit, a common mode voltage control is needed. In this case, a Common-Mode Feedforward (CMFF) circuit was implemented because it allows for greater output swing than a Common-Mode Feedback circuit [57]. The VGA I [58] structure is shown in Fig. 3.2.

Figure 3.2: VGA I structure

Due to the fact that the PWL block has a single output and the multiplier control is differential, a current mirror ( M22 and M24) and a current follower (M22, M23 and M25) are used to obtain two control currents with opposite directions: IP W L + and IP W L −. These currents are added to or subtracted from half the bias current flowing through M7. In this way, the differential input 3.1. VARIABLE GAIN AMPLIFIER 43 current ( IP W L + - IP W L −) is multiplied by the differential input voltage VIN in an easy and compact way. The control current Iin therefore controls the exponential

PWL current IP W L , which in turn is multiplied by the input voltage VIN , resulting in a VGA with a linear-in-dB gain variation. The CMFF circuit copies the output currents that flow through M9 and M10 by means of M26 and M27. These currents are added at node A. Thus, a current proportional to the output common mode current and, hence, proportional to the common mode output voltage is obtained. In order to guarantee a precise current summation, an error amplifier was included ( M15- M19) to reduce the non-zero output resistance effect at node A, and to keep the summing node A voltage at the common mode voltage value ( Vcm ). The generated current is subtracted from the amplifier output currents, performing a feedforward cancellation of the output common mode voltage and setting the DC output voltage to be close to the Vcm value. To avoid instability issues in the CMFF loop, a compensation capacitor Cc was connected. This capacitor has no effect on the pole associated to the first stage output [57].

Simulation Results

The VGA was simulated in 0 .35 µm technology, with a supply voltage VDD = 3 V , bias current Ib = 100 µA and a common-mode voltage Vcm = 1 .5V . At each output node a 1pF load capacitor was connected. It can be seen in Fig. 3.3 that the gain varies linearly in dBs, with a gain variation range of 33dB. The gain variation for an increment/decrement of 10 µA in IC is 3.6 ±0.4 dB. The bandwidth of the VGA is 800kHz, which makes it suitable for low frequency applications, such as sensor signal conditioning. The VGA I parameters are shown in Table I in next section. 44 CHAPTER 3. AGC BUILDING BLOCKS

Figure 3.3: Gain vs. IC

3.1.2 VGA II

In [59] a current-mode VGA based on a V-I converter and two second generation current conveyors (CCII) is proposed. The block diagram of this VGA II is shown in Fig. 3.4.

Figure 3.4: VGA block diagram

The I-V converter block (Fig. 3.5) is a diﬀerential transconductance ampliﬁer circuit which consists of four transistors bias in the triode region, working as a voltage controlled linear resistors.

Input signals are composed by a common mode ( VCM ) and a diﬀerential voltage component ( V d/ 2). Therefore, input voltages are deﬁned as: 3.1. VARIABLE GAIN AMPLIFIER 45

Figure 3.5: Complete V-I Converter implemented with triode transistors

Vin + = VCM + Vd/2

Vin − = VCM − Vd/2

Thus, the transconductance gm of the V-I converter is given by:

1 1 gm = IB − (3.6) VX2 − 2VCM − 2Vt + Vb VX1 − 2VCM − 2Vt + Vb

Each diﬀerential output of the V-I converter is connected to a CCII. The ideal behavior of a CCII is described by eq. (3.7), where iy = 0, vx = vy and iz = ±ix. A CCII is based on a voltage follower between Y and X terminals and a current mirror between X and Z terminals, where ideally X-terminal has zero input impedance while Y and Z terminals have inﬁnite input and output impedance, respectively [60].

iy 0 0 0 vy       vx = 1 0 0 ix (3.7)        iz   0 ±1 0   vz        46 CHAPTER 3. AGC BUILDING BLOCKS

Fig. 3.6 shows a very compact CCII based on the wide-swing current mirror [61].

Figure 3.6: Second Generation Current Conveyor

Although this is a very simple CCII, the voltage at X-terminal is not the same as the Y-terminal voltage because it is shifted by a Vsg (VX = VY +Vsg 1). Moreover, the current ﬂowing out of the Z-terminal is equal to the current ﬂowing into the

X-terminal plus the CCII bias current ( iZ = iX + iCCII ). These drawbacks do not affect the VGA behavior because the Vb voltage is fixed and the iCCII current can be subtracted from the differential output current. Thus, by connecting the V-I converter and the CCIIs, the VGA proposed in [59] is formed, as is shown in Fig. 3.7. The PWL exponential pre-distortion circuit proposed in Chapter 2 is connected to the VGA in order to vary exponentially the amplifier gain. So, if the input current IB linearly varies over time, IEXP is a PWL exponential current. Thus, the gain of the cell shows an exponential dependence on the input current IB. The exponential VGA circuit was designed in 0 .13 µm CMOS technology, with supply voltage V DD = 2 .5V , bias voltages V n = V p = 1 .2V and Vb = 1 V . The PWL exponential pre-distortion circuit was implemented with Lazzaro’s WTA.

The bias current iCCII , which was implemented by a high swing current mirror, is equal to 150 µA . The width of M1 to M4 transistors is 38 µm . The widths of all NMOS and PMOS transistores are 7 .6µm and 25 .3µm , respectively. In order 3.1. VARIABLE GAIN AMPLIFIER 47

Figure 3.7: Exponential VGA diagram to reduce short channel eﬀects, the length for all transistors is equal to 0 .4µm . The simulated transconductance of the exponential VGA is shown in Fig. 3.8.

Input current IB was varied from 5 µA to 22 .5µA in seven steps of 2 .5µA each one. This currents is converted to its exponential equivalent by the PWL exponential pre-distortion circuit, so the current biasing the VGA is in fact a control current that exponentially varies the ampliﬁer gain.

Figure 3.8: Simulated exponential VGA transconductance 48 CHAPTER 3. AGC BUILDING BLOCKS

The VGA transconductance varies from 8 .4µA/V to 291 .3µA/V for the IB variation mentioned before, as shown in Fig. 3.8. The linear in dB transconductance variation for the same IB range is shown in Fig. 3.9, with a linear variation range of 29 .92 dBµ .

Figure 3.9: Linear in dB simulated transconductance variation

The Total Harmonic Distortion (THD) was simulated at diﬀerent gain settings, for an output current equal to 20 µA at 100kHz. Results are shown in Table 3.1.

Table 3.1: THD at 100kHz for diﬀerent IB values and an output current IO = 20 µA

Vin (mV ) IB (µA ) Gain (dB) THD ( dB ) 350 15 55.76 -42.09 232 17.5 60.25 -42.27 129 20 65.18 -51.09 65.7 22.5 69.20 -69.36 3.1. VARIABLE GAIN AMPLIFIER 49

Experimental Results

The VGA was designed and fabricated in 0 .13 µm CMOS technology, with a V DD = 2 .5V . Bias signals were set to V n = V p = 1 .2V , V y = 1 V and

ICCII = 25 µA . The measured transconductance is shown in Fig. 3.10, were the transconductance varies from 5 .7µA/V to 353 µA/V , for an IB variation from 5µA to 22 .5µA . In Fig. 3.11 the measured exponential VGA variation in a linear in dB scale is shown, where total transconductance variation is equal to 31 .84 dB .

Figure 3.10: Measured transconductance

Figure 3.11: Linear in dB measured transconductance variation

The VGA layout is shown in Fig. 3.12, with an area of 180 µm x 155 µm . The power consumption is equal to 3 .1mW . 50 CHAPTER 3. AGC BUILDING BLOCKS

Figure 3.12: Exponential VGA layout

In Table 3.2 the VGA I and VGA II parameters are summarized together with other previously reported VGAs. VGA II shows the highest gain variation with a supply voltage and power consumption comparable to the other implementations. With the exception of VGA I and II, all VGAs on Table 3.2 have high bandwidth values, but due that the AGC of this thesis is focused on low frequency applications, large bandwidths are not needed.

Table 3.2: VGA Parameter Comparison

Parameter VGA I* VGA II [62] [63]* [64] [65] CMOS Technology (nm) 350 130 180 90 250 500 Supply Voltage (V) 3 2.5 0.8 1.2 3.3 ±1.5 Gain variation (dB) 33 41.94 17 17 40 28 Bandwidth (MHz) 0.8 0.45-1.8 21-195 265-285 6-108 5 THD (dB) −54 −41 −50 — −68 — Power consumption (mW) 5.1 3.1 0.2 0.3 74.6 5

*Simulation results 3.2. LOGARITHMIC AMPLIFIER 51 3.2 Logarithmic Ampliﬁer

Logarithmic amplifiers, or logarithmic pre-distortion circuits, perform a more complex operation than that of classical linear amplifiers. The essential purpose of a logarithmic amplifier is not to amplify, but to compress a signal of wide dynamic range to its decibel equivalent. Therefore, its basic function is the conversion of a signal from one domain of representation to another via a nonlinear transform- ation [66].

A logarithmic amplifier is included inside the AGC loop in order to have a relative constant settling time even for abrupt input signal changes. If the logarithmic amplifier is omitted, the objective of constant settling time can still be met under certain small-signal approximations [4], but the loop time constant will depend on the reference AGC signal, which is an input variable. In constrant, if the logarithmic amplifier is included, the loop time constant is independent of any input variable [4].

Logarithmic circuits can be classified as true (baseband) or demodulating logarithmic amplifiers. The first type provides the logarithm of the input signal without demodulating it and the second type provides the logarithm of the envelope input signal [67].

Also Logarithmic amplifiers can be divided according to their design architecture as a single-stage or PWL. The design of the modern logarithmic amplifiers is on the basis of the successive detection architecture that implements a PWL logarithmic function. True PWL approximation logarithmic amplifiers are in turn divided into two classes: Series Linear-Limit and Parallel-Summation Logarithmic Amplifiers [67]. The PWL approximation technique reported in literature uses a cascade of nonlinear dual gain stages that approximates the logarithmic curve as a PWL function [67], which gives complex designs. In this thesis, based on the same idea of the PWL Exponential circuit, a PWL Logarithmic amplifier is proposed, achieving a simpler Logarithmic circuit and obtaining a modularity based design for all the AGC loop, as will be shown in Chapter 4. 52 CHAPTER 3. AGC BUILDING BLOCKS

3.2.1 Proposed PWL Logarithmic circuit

The logarithmic circuit was designed following the same idea of the PWL exponential function, implementing a determined logarithmic function by a piece-wise linear approximation, were also the best choice is to divide the whole range with equidistant breakpoints in a logarithmic scale, leading to a set of equal dB-length segments. Due to the fact that a logarithmic function is a monotonically increasing mathematical function, a Loser-Take-All (LTA) circuit is needed to implement it, in contrast to the use of WTAs to implement the exponential function.

Loser-Take-All Circuit

In [68] Patel and DeWeerth presented a very simple current-mode LTA circuit based on only two transistors per cell. Its operation is very similar to the WTA circuits described in Chaper 2, based on local feedback in each cell. In fact, it is based on the Lazzaro’s WTA topology. In a Lazzaro’s WTA, input and output transistors in each cell are the same type, either NMOS or PMOS. In Patel’s LTA the input and output devices are complementary MOS transistors, allowing for the detection of the lowest input value. In order to explain the basic operation of the circuit presented in [68], a three input LTA is shown in Fig. 3.13. First, when I = Iin 1 = Iin 2 = Iin 3, the IC current ﬂows through M12, M22 and M32, divided equally between these three transistors. When Iin 1 decreases by a I − ∆I factor, the voltage at node V1 grows up, increasing the Vgs of transistor M12 and therefore increasing the voltage at the common node VC . Now M21 and M31 try to source I − ∆I but the current through these transistors is I, so the voltage at V2 and V3 nodes decreases and

M22 and M32 are pushed into cut-oﬀ region. As a consequence all IC current ﬂows through M12, which is the loser cell. As in the WTA cicuits, in order to get a copy of the loser current, Mout transistor is connected to VC node. This 3-input LTA was designed and simulated in 0 .13 µA technology, with a

2.5V single supply voltage. The ideal current source IC , equal to 25 µA , was implemented with a wide swing current mirror. The width of the LTA transistors 3.2. LOGARITHMIC AMPLIFIER 53

Figure 3.13: 3-input Patel’s LTA are 8 µm and 2 .4µm for PMOS and NMOS transistors, respectively. The length for all transistors is 0 .4µm . Time response was simulated, where inputs signals were two 12 µA p sinusoidal currents of 1 kHz and 5 kHz for Iin 2 and Iin 3, respectively.

Iin 1 was a constant current of 15 µA . The simulation results are shown in Fig.

3.14, where the output current Iout follows the lowest input value.

Figure 3.14: Simulated input and output current waveforms

Proposed PWL Logarithmic circuit design

The proposed PWL logarithmic circuit is based on the use of current mirrors and a LTA circuit. As in the exponential PWL approximation, for a PWL logarithmic 54 CHAPTER 3. AGC BUILDING BLOCKS approximation, the best choice is to divide the total range with equidistant breakpoints in order to have a set of equal-length segments and as consequence, the error in dB-scale will be the same for all the segments. The logarithmic function to be implemented is:

g(x) = ln (ax ) (3.8)

where a is a constant. Now the linear approximation y(x) between the breakpoints at x1 and x2 is shown in Fig. 3.15.

Figure 3.15: Linear approximation y(x) of function g(x) between ( X1, Y 1) and

(X2, Y 2)

y(x) = b + mx (3.9)

with ln (ax ) − ln (ax ) m = 2 1 (3.10) x2 − x1

x2ln (ax 1) − x1ln (ax 2) X0 = (3.11) ln (ax 1) − ln (ax 2)

The approximation error, ǫdB = g(x) − y(x), is given by:

x(ln (ax 1) − ln (ax 2)) x2ln (ax 1) − x1ln (ax 2) ǫdB = ln (ax ) − + (3.12) x1 − x2 x1 − x2 Thus, the maximum approximation error is given by:

e∆ − 1 ∆ + 1 − e∆ ǫ = ln − (3.13) dB a∆ 1 − e∆ 3.2. LOGARITHMIC AMPLIFIER 55

where ∆ = ln (x2) − ln (x1).

The breakpoints of the PWL logarithmic approximation were obtained by dividing in an equidistant manner an ideal linear-in-dB logarithmic function, as shown in Fig. 3.16. In Fig. 3.16a is shown the ideal and PWL logarithmic functions in a linear-in-dB scale and in Fig. 3.16b is shown the ideal error between these two functions, where the maximum ideal error is about 0 .18. Thus, breakpoints are then used to determine the slope ( m) and oﬀset ( Y0) of each segment, which are calculated from Ecs. (3.10) and (3.11), respectively.

Figure 3.16: a) BPs in a six-segment PWL Logarithmic and b) Error of PWL approximation

The input current Iin is copied n times ( n= number of segments) by a current mirror of multiple outputs, CM in in Fig. 3.17. At each of these CM in outputs a current mirror CM i (i = 1 ,...,n ) is connected to adjust the current mirror aspect ratio in order to change the current slope through the current mirror aspect ratio m and to add an oﬀset current to Iin , but now over −X-axis ( X0 = −Ioﬀset), thus generating each segment of the logarithmic function. After this, the outputs of the current mirrors CM i are connected to the inputs of the LTA, whose output is equal to the lowest input current, thus selecting the proper segment of the approximation. As a result, a PWL logarithmic function approximation is generated at the output.

Fig. 3.18 shows an implementation of CM i (transistors M1 to M5), and 56 CHAPTER 3. AGC BUILDING BLOCKS

the input current mirror CM in with only one output (transistors MCM In 11 to

MCM In n2 ). Oﬀset current (Ioﬀset) is added through transistors M1 and M2 and the slope is set through the aspect ratio m = ( W/L )M5,M 6/(W/L )M3,M 4. Finally, the LTA circuit described before is included into the logarithmic function circuit as shown in Fig. 3.19.

Figure 3.17: Proposed logarithmic circuit block diagram

Figure 3.18: Current mirror to adjust oﬀset (Ioﬀset) and slope ( m) of a segment

In order to prove the idea described before, a PWL logarithmic circuit was simulated in 0 .13 µm technology. Power supply voltage was 2 .5V , bias voltages 3.2. LOGARITHMIC AMPLIFIER 57

Figure 3.19: LTA diagram within the logarithmic circuit

V n and V p were equal to 1 .2V . The ideal current source IC in the LTA is equal to 10 µA , which also was implemented with a wide swing current mirror. Breakpoints, slopes and offsets values needed for the generation of each segment in the proposed implementation are shown in Table 3.3. The widths of transistors setting the slope and DC offset in each current mirror CM i are shown in Table 3.4. The widths of transistors in MCMin are 3 .8µm , for MB 1 and MB 2 are 3 .16 µm and for M3 and M4 are 2 .26 µm . The widths of the LTA transistors are 8 µm and 2 .4µm for PMOS and NMOS, respectively. The length for all transistors is 0 .4µm . Again, as the PWL exponential implementation, the proposed technique is not restricted to the use of a specific LTA.

Table 3.3: Breakpoints, Slopes and DC Oﬀsets

Breakpoints Segment m −X0(µA ) (X1(dB ), Y 1) (X2(dB ), Y 2) 1 0.00, 5.00 4.66, 7.68 3.77 0.326 2 4.66, 7.68 9.32, 10.35 2.20 1.78 3 9.32, 10.35 13.98, 13.04 1.29 5.07 4 13.98, 13.04 18.64, 15.73 0.76 12.17 5 18.64, 15.73 23.30, 18.41 0.44 27.16 6 23.30, 18.41 27.96, 21.10 0.26 56.15 58 CHAPTER 3. AGC BUILDING BLOCKS

Table 3.4: Transistor Dimensions

Segment WM5,M 6(µm ) WM1,M 2(µm ) 1 8.52 − 2 4.96 0.56 3 2.94 1.60 4 1.72 3.85 5 1.00 8.54 6 0.60 17.74

Fig. 3.20 shows the simulated responses of the PWL Logarithmic circuit. In Fig. 3.20a the ideal and simulated PWL Logarithmic response is shown in a linear-in-dB scale. In Fig. 3.20b the error of the PWL implementation is shown, with a maximum value of 2 .65 dB .

Figure 3.20: a) Ideal and simulated PWL logarithmic function and b) Error of PWL approximation 3.2. LOGARITHMIC AMPLIFIER 59

Experimental Results

The Logarithmic circuit was fabricated in 0 .13 µm technology, with a power supply voltage of 2 .5V , bias voltages V n and V p equal to 1 .2V and a DC polarization current source ( IB pwl for CM i and IC for the LTA) equal to 10 µA . In Fig. 3.21 is shown the measured logarithmic response of the designed circuit, which shows a maximum error of 1 .59 dB for a logarithmic function equal to y = 10 + 2 ln (Iin ). The layout is shown in Fig. 3.22 were the occupied area is 133 µm x 58 µm . The power consumption was 525 µW . In Table 3.5 the PWL logarithmic ampliﬁer parameters are summarized and its performance is compared with other implementations found in literature.

Figure 3.21: a) Ideal and measured PWL logarithmic function and b) Error of PWL approximation

Table 3.5: Logarithmic Ampliﬁers Parameter Comparison

Parameter Proposed [69] [70] [71] [72] CMOS Technology ( µm ) 0.13 0.18 0.35 0.18 0.13 Supply Voltage (V) 2.5 1.8 3.3 2.5 1.2 Input variation (dB) 27.95 29 32 20 20 Power consumption (mW) 0.525 16 3.4 10.8 0.18 60 CHAPTER 3. AGC BUILDING BLOCKS

Figure 3.22: Logarithmic circuit layout 3.3. DETECTORS 61 3.3 Detectors

One of the purposes of an AGC loop is to maintain its output amplitude relative constant despite input signal changes. In order to achieve this, the gain of the VGA is modiﬁed by a control signal, which is equal to the substraction of a constant reference signal with another signal that is proportional to some AGC output signal parameter, such as peak amplitude, side band power, modulation index, etc. So, the detector circuit in an AGC is the responsible to obtain this last signal from the VGA output. The detector response plays an important role in the dynamic loop response during abrupt input changes [73]. In order to obtain an appropriate AGC response, the estimation time of the input signal amplitude should be lower than the constant time of the loop ﬁlter. Next, the four types of detectors are described: Envelope, RMS, Quadratic and Logarithmic.

• Envelope: Generally the signal amplitude is estimated using an envelope or peak detector, in order to detect the VGA output peak value, which represents the ratio of the amplitude signal and the peak power average of a sinusoidal signal. The most common implementations are based on a differential amplifier, a current mirror and a capacitor as integrator. Also there are peak detectors based on the sample and hold technique [15]. Other implementations are based on differential positive peak detectors [9], where the rectifier circuit (diode) is implemented by a current mirror and a transconductor or by two half wave rectifiers based on MOS transistors.

• RMS: Measures the eﬀective value of periodic or aleatory signals and its output is independent of the wave form of the input signal [73], [74]. The RMS detectors are based on Joule heating [75] which have a good precision and a wide bandwidth, but need complex and expensive chip packages. Also there are RMS detectors designed with diodes based on the quadratic law [75], used in communication systems as an option to measure power at a low cost. However, compensation techniques are required, showing limited dynamic range and stability problems. As an alternative the use of translinear 62 CHAPTER 3. AGC BUILDING BLOCKS

cells is employed [75].

• Square: This type of detectors have an instant output proportional to the square value of the input signal; in other words, its output is proportional to the input power [73]. Its design is based on the square relation between drain current and gate voltage in a MOS transistor [76]. As in the envelope detectors, their output can not be negative and, as a consequence, the loop has a similar tendency to a limited slew rate in abrupt decrements of the input signal. This eﬀect is greater in abrupt increments in the input signal [73].

• Logarithmic: The Logarithmic ampliﬁer produces an output signal proportional to the logarithm of the input signal. Due to the fact that the logarithmic behavior is complementary to that of the linear-in-dB VGA, the AGC loop dynamic is equal to a linear system. Thus, the AGC loop response to abrupt input changes will not be slew-rate limited [73].

Logarithmic and squarer detectors show faster response to decrements and increments of the input signal, respectively. On the other hand, envelope and RMS detectors have an intermediate response. Even so, these four detectors have similar responses to small input signal changes [73]. Due to the fact that PWL Exponential and Logarithmic circuits were designed based on WTA/LTA structures, a simple form to design a signal detector is to use a WTA as full wave rectifier [77] connected to the PWL logarithmic circuit described previously and finally to a first order low-pass filter (LPF), as shown in Fig. 3.23

Figure 3.23: Block diagram of the Peak Detector 3.3. DETECTORS 63

The VGA is a differential transconductance amplifier, so it output currents are connected to a two-input WTA. This way, the WTA detects the positive cycles of the VGA outputs, acting as a full wave rectifier, as shown in Fig. 3.24.

Figure 3.24: Block diagram of the full wave rectiﬁer

Full wave rectiﬁer transistor diagram is shown in Fig. 3.25, which is a two- input Lazzaro WTA. The simulation response is shown in Fig. 3.26 for two input sinusoidal currents with 180 ◦ phase between them, with an amplitude equal to

100 µA p and a frequency of 1 kHz . The bias current IB is equal to 150 µA . The output current is equal to the positive cycles of the input signals. The power consumption is equal to 1 .56 mW .

Figure 3.25: Peak Detector diagram

A first order low pass filter, which is described in [78], is connected at the logarithmic output. As is shown in Fig. 3.27, this filter is based in a wide-swing current mirror structure and a Capacitor CAGC , which is the AGC capacitor.

Simulated AC response gives a cut-oﬀ frequency of 38 .4kHz for a CAGC = 1 nF , as shown in Fig. 3.28. 64 CHAPTER 3. AGC BUILDING BLOCKS

Figure 3.26: Simulation response of the WTA Peak Detector

The full detector was integrated within the ﬁnal AGC loop presented in the next chapter, so no experimental results of this circuit itself are available. In Fig. 3.29 the detector time response is shown, where two parameters were obtained, attack and settling time. Attack-time is the time required by the circuit to respond to a positive input envelope stepwise change. Speed is required in order to obtain a peak detector which can accurately track an increment in the input signal amplitude [51]. Release-time is the time required to respond to a negative input envelope stepwise, which depends on the capacitor size itself [51]. The simulated attack and release times with a CAGC equal to 1nF were 16 .17 µs and 28 .8µs , respectively. The total power consumption is approximately 960 µW . The detector layout is shown in Fig. 3.30 with an area consumption of 200 µm x 86 µm . 3.3. DETECTORS 65

Figure 3.27: Detector ﬁlter

Figure 3.28: Detector ﬁlter frequency response 66 CHAPTER 3. AGC BUILDING BLOCKS

Figure 3.29: Detector time response

Figure 3.30: Detector layout 3.4. CONCLUSIONS 67 3.4 Conclusions

In this chapter the main of the AGC building blocks were described. This circuits were designed and then fabricated in 0 .13 µm CMOS technology of ST Microelec- tronics. The two exponential variable gain amplifiers (VGAs) presented in this chapter shows wide gain variation range and a power consumption comparable with other implementations. Experimental results shows that the VGA II presents the widest gain variation (41.94dB) with a power consumption equal to 3.1mW. The proposed logarithmic pre-distortion circuit was described and designed based on current mirrors and a LTA circuit. Experimental results shows an input variation range of 27.95dB which is comparable to other published logarithmic circuits and a low power consumption of 525 µW . A WTA was used as a full wave rectifier and, with a low-pass filter, a peak detector was designed. This detector includes the PWL logarithmic circuit previously designed in order to accomplish with a linearized AGC loop. The time response of the detector is 28 .8µs with a total power consumption of 960 µW . 68 CHAPTER 3. AGC BUILDING BLOCKS Chapter 4

Automatic Gain Control

Automatic Gain Control (AGC) circuits are used in systems where the amplitude of the input signal varies on a wide dynamic so that the following circuits require less dynamic range [4]. In this Chapter an AGC loop is analyzed mathematically, using simulation results with Matlab, as a linear-in-dB system. Once the loop is simulated, a novel CMOS design at transistor level using the building blocks presented in former Chapters is proposed. Such a CMOS design was implemented on silicon using a technology of 0 .13 µm of ST Microelectronics. Measurement results are provided in order to demonstrate the design validity. Finally it is demonstrated that using PWL exponential and logarithmic pre-distortion circuits into the loop, the AGC circuit works properly for constant time responses.

4.1 AGC Loop Analysis

An AGC is a non-linear system, originally with an input signal dependent settling time. If a logarithmic function is added to the AGC loop, as shown in Fig. 4.1, this loop can be characterized as a linear-in-dB system [4]. It is quite difficult to find a solution for the non-linear equation described in [5], but an alternative model that describes the system behavior [4] is presented as follows: The VGA gain is equal to G(VC ), which is controlled by V c . The peak detector and the filter form a feedback circuit that monitors the peak amplitude

(AOUT ) of the output signal VOUT and adjusts the VGA gain until the measured

69 70 CHAPTER 4. AUTOMATIC GAIN CONTROL

Figure 4.1: AGC block diagram

peak amplitude V p equals the reference voltage Vref . The AGC output is the input signal multiplied by the gain:

VOUT (t) = G(VC )VIN (t) (4.1)

As the feedback loop only responds to peak amplitudes, the output signal amplitude VOUT is equal to:

AOUT = G(VC )AIN (4.2)

where AIN is the peak amplitude of VIN . The equivalent representation of the AGC is shown in Fig. 4.2, where the feedback loop only works for signal amplitudes and, as a consequences the input and output signals are represented only on amplitude terms: AIN (t) and AOUT (t).

The Peak Detector on Fig. 4.1 linearly extracts the peak amplitude of VOUT (t) faster than all loop operation, so V p = AOUT . Thus, the Peak Detector is not explicit shown in Fig. 4.2. Also the ﬁlter block in Fig. 4.1 is shown as an integrator in Fig. 4.2, where H(s) = Gm/sC AGC . The term kv1exp (y) is duplicated inside and outside the dotted block such that x(t) and y(t) represent the input and output amplitudes of the AGC, expressed in dB with a proportionality constant. The model on Fig. 4.2 is a linear-in-dB AGC model, using exponential and logarithmic blocks which simpliﬁes the mathematical analysis. Based on this

ﬁgure and, due to the fact that the VGA multiplies the input amplitude AIN by 4.1. AGC LOOP ANALYSIS 71

Figure 4.2: Generalized AGC model

G(V c ), and equivalent representation is:

AIN AOUT = kv1exp ln (G(VC )) + ln (4.3) kv1

where kv1 is a constant with the same units of AIN and AOUT .

In order to have a constant settling time, the blocks inside the dotted box must be a linear system. As x(t) represents the input signal amplitude, AIN (t), in dB, and y(t) is the output amplitude signal, AOUT (t), in dB, the linear response from x(t) to y(t) means that the AGC amplitude response from the input to the output is linear-in-dB. From Fig. 4.2, the y(t) output is:

y(t) = x(t) + ln (G(VC )) (4.4)

The control signal V c is equal to:

t Gm z y(t) V c (t) = kv1e − kv2ln e dt (4.5) Z CAGC 0 72 CHAPTER 4. AUTOMATIC GAIN CONTROL

Derivating eq. (4.4) using the chain rule and substituting it in Eqs. (4.4) and (4.5):

dy dx 1 dG dV = + C (4.6) dt dt G(VC ) dV C dt

t dy dx 1 dG d Gm z y(t) = + kv1e − kv2ln e dt (4.7) dt dt G(VC ) dV C dt Z CAGC 0

dy dx 1 dG G = + m k ez − k ln ey(t) (4.8) dt dt G(V ) dV C v1 v2 C C AGC Equation (4.8) describes a non-linear system so, in order to get a linear system, the second coeﬃcient of this equation must be constant:

1 dG Gm kX = (4.9) G(VC ) dV C CAGC Therefore:

dy dx = + k k ez − k ln ey(t) (4.10) dt dt X v1 v2 dy dx + k k y(t) = + k V (4.11) dt X v2 dt X ref z where Vref was substituted by kv1e from Fig. 4.2. Ec. (4.11) describes a ﬁrst order linear system with a high pass response from input x(t) to output y(t). From eq. (4.11), the system time constant τ is:

1 τ = kX kv2

1 τ = 1 dG Gm (4.12) G(V c ) dV c C kv2 The classical criteria for a constant AGC settling time assumes that Gm and C are constant, so: 1 dG kG1 = (4.13) G(VC ) dV C 4.2. MATLAB SIMULATION RESULTS 73

The system time constant is therefore given by: C τ = AGC (4.14) GmkG1kv2 Reordering eq. (4.13) and integrating both sides of the equation, the exponential gain characteristic of a VGA is obtained, given:

dG = kG1 G(VC ) (4.15) Z dV C Z

kG1VC G(V c ) = kG2e (4.16)

Thus, the simplest way to achieve constant settling time is by designing a VGA with an exponential gain variation with respect to Vc [4]. Although the analysis presented before includes a logarithmic amplifier in order to have a linear-in-dB AGC, some implementations do not include such amplifier. In those cases a constant settling time can still be achieved under certain small signal approximations [4]. The AGC presented in this chapter uses a logarithmic PWL amplifier in order to have a linear-in-dB loop without small signal conditions.

4.2 Matlab Simulation Results

It has been demonstrated so far that exponential and logarithmic pre-distortion circuits are needed to obtain constant settling time AGC loop. In order to gain more insight into that analysis, simulations were performed in Simulink to obtain release and attack times for an AGC loop with and without exponential and logarithmic ampliﬁers (e.g. linear-in-dB and linear AGC loops). Remember from Chapter 1 that release time (or attack time) is the time it takes an AGC to respond to an abrupt decrement (or increment) of the input signal. Both times are measured from the moment the input signal changes until the output signal reaches its ﬁnal value withing a given tolerance range [11]. Fig. 4.3 shows the responses of a linear (Fig. 4.3a) and a linear-in-dB (Fig 4.3b) AGC to an abrupt input decrement. The input signal was varied from 120 to 7 .5 in four steps of 6dB each 120nsec. Also, the response of a linear and a linear-in-dB AGCs 74 CHAPTER 4. AUTOMATIC GAIN CONTROL to an abrupt input increment is shown in Fig. 4.4a and Fig. 4.4b, respectively. The input signal was varied from 7.5 to 120 in 6dB-steps each 120ns.

Figure 4.3: Time response to an abrupt input decrement of: a) Linear and b) Linear-in-dB AGC

In Table 4.1 release and attack times of both linear and linear-in-dB AGCs are shown. These time responses were obtained in each increment or decrement input step at 1% of the ﬁnal value. As the input signal is divided in four steps of

120nsec each one, release and attack times were measured four times (from ST 1 to ST 4). As it can be seen, release and attack times are almost constant and independent of the input signal value for a linear-in-dB AGC. On the other hand, time responses of a linear AGC strongly depends on the input signal level. It is therefore shown that the AGC loop must include exponential and logarithmic circuits to obtain almost constant settling times. 4.3. PROPOSED AGC CIRCUIT 75

Figure 4.4: Time response to an abrupt input increment of: a) Linear and b) Linear-in-dB AGC

Table 4.1: Ideal release and attack times of linear and linear-in-dB AGCs

Release Time ( ns ) Attack Time ( ns ) Time linear linear-in-dB linear linear-in-dB

ST 1 10.8 38.3 47.5 35.0 ST 2 20.9 36.0 22.6 30.1 ST 3 41.1 38.6 12.6 32.5 ST 4 76.3 43.8 5.0 22.6

4.3 Proposed AGC circuit

Once the AGC loop was ideally analyzed, a real AGC was designed and implemented based on the circuits proposed in Chapter 2 and 3. In Fig. 4.5 a block diagram is shown which describes how these circuits were connected together in order to obtain the total AGC system. Because peak detector, logarithmic, LPF and exponential circuits are current- mode designs, the AGC is a current-mode loop. Although the VGA input is a 76 CHAPTER 4. AUTOMATIC GAIN CONTROL differential voltage signal, the control signal of the AGC amplifier is in current- mode. In fact, the VGA is a variable gain transconductance amplifier, so as its outputs are currents, a copy of the differential output current is taken for the loop control signal.

Figure 4.5: Block diagram of the proposed AGC loop

4.3.1 AGC Experimental results

The AGC was designed and implemented also in 0 .13 µm CMOS technology. Power supply voltage is 2 .5V , bias voltages are V n = V p = 1 .2V for all circuits and V b = 1 V for the VGA. As the input voltage signal is diﬀerential, the common- mode voltage V cm is equal to 1 .25 V . Reference current IREF and External AGC

Capacitor CAGC were equal to 25 µA and 1 nF , respectively. The diﬀerential AGC outputs were connected to a couple of 10 kΩ load resistances in order to convert the AGC output current into voltage and compare it with the input voltage. The main function of an AGC is to maintain a relative constant output signal independent of the input variations. So, in order to know if the implemented AGC loop is working, input and output voltages are compared in Fig. 4.6. Input voltage 4.3. PROPOSED AGC CIRCUIT 77 was increased linearly from 50 mV to 2 V and the AGC output voltage starts increasing almost linearly with no AGC action. When the input level reaches 450 mV approximately, AGC action begins and, for input voltages higher than this value, the AGC system attempts to maintain output voltage almost constant.

Figure 4.6: Input and output AGC voltage

The implemented AGC was also tested with an input voltage with diﬀerent amplitudes during certain periods of time. Release time was tested with an input voltage that decreased from 1 V to 0 .355 V , in three 3dB steps of 20 µs each one. The input and output voltages of the AGC are shown in Fig. 4.7a and Fig. 4.7b, respectively. Attack time was tested with an input voltage that increased from 0.355 V to 1 V divided also in three 3dB steps of 20 µs each one. Fig. 4.8a and Fig. 4.8b shows the input and output voltages, respectively. As it can be seen for both cases, the time response of the AGC loop tends to be constant, as shown in Table 4.2 for both simulated and measured time responses, taken at 1% of the ﬁnal value of each step.

From eq. (4.14), with kG1 = 1 .5 and kG2 = 1 [4] and from VGA transconductance measured values presented in Chapter 3, the AGC time response should be around 3 .3µs , which is conﬁrmed also in Table 4.2, where time responses are greater than this value because is not included in eq. (4.14) the nonlinear dynamic of CMOS implementations such as saturations and second order eﬀects. The AGC loop was also tested for abrupt input changes. Input voltage signal was a single step signal which varied 6dB, between 0 .5V and 1 V . Release and 78 CHAPTER 4. AUTOMATIC GAIN CONTROL

Figure 4.7: Time response of the proposed AGC as input decreases in 3dB-steps: a) Input Voltage, b) Output Voltage

Figure 4.8: Time response of the proposed AGC as input increases in 3dB-steps: a) Input Voltage, b) Output Voltage 4.3. PROPOSED AGC CIRCUIT 79

Table 4.2: AGC Release and Attack time responses

Release Time ( µs ) Attack Time ( µs ) Time Simulated Measured Simulated Measured

ST 1 2.77 4.50 4.05 5.36 ST 2 3.50 5.98 4.00 5.80 ST 3 3.80 7.25 2.71 3.27

attack times were equal to 6 .09 µs and 5 .07 µs , respectively, with a compression factor equal to 17. Once again, the time response remains relatively constant for abrupt decrements and increments of the input signal.

Figure 4.9: Time response for an abrupt input change of the proposed AGC: a) Input Voltage, b) Output Voltage

The layout of the AGC is shown in Fig. 4.10, where the power and area consumption is equal to 12 mW and 196 µm x 210 µm , respectively. Layout images instead of transistors microphotograph are presented because the chip has the passivation layer at the top of the die. In Table 4.3 an AGC parameter comparation is shown. 80 CHAPTER 4. AUTOMATIC GAIN CONTROL

Figure 4.10: AGC measured layout

Table 4.3: AGCs Parameter Comparation

Parameter Proposed [6] [79] [80] [81] CMOS Technology ( µm ) 0.13 0.18 0.18 0.35 0.35 Supply Voltage (V) 2.5 2 1.8 1.8 to 5.5 3

Vout ( mV p) 500 250 — — — Loop Bandwidth 38.4kHz — 100kHz 20 to 50kHz — VGA Bandwidth (MHz) 0.45-1.8 0.8 to 18 — — 100 AGC Gain (dB) 41.94 40 28.5 — — Settling Time ( µs ) 6.09 4.8 1.6 2100 — Compression Factor 17 — — 8.12 — Power consumption (mW) 12 11.2 43.2 — 24 Area ( mm 2) 0.196x0.21 0.75x0.75 0.82x0.56 — 0.25

4.4 Conclusions

An AGC loop with a current-mode control loop was presented, implemented with PWL exponential and logarithmic pre-distortion circuits which were designed in previous chapters, demonstrating its application in a current-mode control loop. According to mathematical analysis and ideal AGC loop simulations, the implemented AGC circuit presents almost constant time responses for input abrupt 4.4. CONCLUSIONS 81 changes. Thus, it is demonstrated that PWL pre-distortion circuits are suitable to be used in complex systems such as an AGC loop. The designed AGC presents a settling time of 6 .09 µs for a 6dB input step with a compression factor equal to 3.55 and a power consumption of 12mW. 82 CHAPTER 4. AUTOMATIC GAIN CONTROL Chapter 5

Conclusions and Future work

In this Chapter the results and conclusions obtained during this thesis work are summarized. Also some ideas derived of the results obtained from this thesis are discused as a future work.

5.1 Conclusions

In this thesis, a technology-independent solution to implement an exponential approximation based on a PWL design method was proposed, which is not limited to a certain validity range, in contrast to pseudo-exponential approximations. The PWL exponential proposal was validated with experimental results from a 6-segment prototype, which show a wide range of 41.97dB with 2.55dB maximum error. Moreover, the error can be reduced by increasing the number of segments of the approximation, at a cost of power consumption. So, a trade-oﬀ between variation range, error and power consumption must be taken into account. The proposed PWL exponential approximation is based on current mirrors and a WTA circuit. Classical WTA implementations show a wide input voltage swing and, as a consequence, a slow response to abrupt input signal changes. As a solution, a novel WTA circuit topology, based on Lazzaro’s WTA, is presented, which is 27% faster than this last classical topology. As it was mentioned before, in order to obtain an AGC with a constant time response, the gain variation of the VGA must be exponential. Thus, the proposed

83 84 CHAPTER 5. CONCLUSIONS AND FUTURE WORK

PWL exponential circuit was used to vary the gain of a linear VGA, obtaining an exponential VGA (simply called VGA in this thesis). Two VGA circuits were designed: one based on a Gilbert cell (VGA I) and another pre-based on a I- V converter circuit (VGA II). Because the VGA II showed a wide gain variation range of almost 42 dB, it was selected as a proper choice to be implemented within the AGC circuit. Additionally to the exponential circuit, a logarithmic amplifier is included inside the AGC loop in order to obtain a constant time response not only for small but also for abrupt input signal changes. The proposed PWL logarithmic amplifier function is based on current mirrors but, instead of using a WTA as in the exponential circuit, a LTA circuit is required because of the logarithm concave shape. Experimental results show an input variation range of almost 28dB with an error lower than 1.6dB. Although the proposed PWL design method was focused on the design of exponential and logarithmic approximations, the method can be extended to implement any concave or convex monotonically increasing mathematical functions. Following the design based on WTA/LTA circuits, a simple peak detector was designed based on a 2-input WTA as a full wave rectifier, which provides the absolute value of its input signal. The full wave rectifier output is connected to the PWL logarithmic amplifier described before and to a low-pass filter with a cut-off frequency of 38.4kHz. Finally, an AGC loop based on the circuits presented before was designed. Experimental results show an almost constant settling time of 6 µs and a compression ratio of 17.14, with power consumption of 12mW. These results prove that the proposed PWL circuits and the AGC loop are suitable to be implemented in submicron technologies.

5.2 Future work

• The proposed PWL design method can be used to implement monotonically increasing or decreasing convex or concave mathematical functions. This can be extended to implement arbitrary mathematical functions based on the 5.2. FUTURE WORK 85

PWL method.

• Apply the proposed PWL method to the design of an AGC for high frequency applications.

• Explore diﬀerent possibilities to design a low-voltage WTA with high resolution and time response, based on circuits using low voltage techniques such as ﬂoating gate or bulk driven transistors. 86 CHAPTER 5. CONCLUSIONS AND FUTURE WORK Appendix A

Circuit implementation of PWL functions

The PWL method presented in this thesis is not only limited to implement monotonically increasing functions. Instead, monotonically decreasing PWL functions can be implemented by using the same basic circuits, that is, current mirrors together with a WTA or a LTA circuit. Increasing and decreasing functions can be classiﬁed as convex or concave functions. In a convex curve g = f(x), each point of the function is located above the tangent and the second derivative f ′′ (x) is greater than zero. On the other hand, in a concave curve g = f(x) each function point is under the tangent with the second derivative f ′′ (x) lower than zero [82]. In Fig. A.1 are shown two examples of a convex (A.1a) and a concave (A.1b) curve.

Figure A.1: a) Convex and b) Concave functions

87 88 APPENDIX A. CIRCUIT IMPLEMENTATION OF PWL FUNCTIONS

Next will be mentioned how can be implemented increasing or decreasing convex and concave PWL functions. First will be described convex and then concave increasing PWL function implementation followed by convex and concave decreasing PWL implementation, using current mirrors and a WTA or LTA, depending on the type of function.

Convex increasing PWL function

In Fig. A.2a a 3-segment PWL convex increasing PWL function is shown. Because of the convex increasing characteristic of the function, only the highest value of the function for each value on X must be selected, so a WTA must be chosen. Thus, if these three segments (dotted lines) are the input of a 3-input WTA, a PWL convex increasing function will be obtained (solid line). In Fig. A.2b only one segment is shown, which is the linear approximation of g(x) between breakpoints X1 and X2, and is described by eq. (A.1). This segment has an oﬀset X0 and a slope m.

Figure A.2: a) 3-segment PWL exponential function and b) linear approximation y(x) of function g(x)

y = m(X − X0) (A.1)

This segment can be implemented by any of the current mirrors shown in Fig.

A.3. Ioﬀset current determines the X0 value whereas the slope m is given by the width relation between transistors M1 and M2. Iout is given by eq. (A.2). 89

Iout = m(Iin − Ioﬀset) (A.2)

Figure A.3: Circuits for implementing each segment of a PWL exponential: a) NMOS and b) PMOS version

Concave increasing PWL function

In order to implement this function with the PWL method described in this thesis, a LTA must be employed due to the fact that this is a concave function, so the lowest values of each linear segment must be chosen. A 3-segment concave increasing approximation is shown in Fig. A.4a, were dotted lines represents each segment and solid line represents the PWL approximation. Fig. A.4b shows only one segment of the approximation, with a negative oﬀset −X0. This segment, which is described by eq. (A.3), is the linear approximation of g(x) between breakpoints X1 and X2.

Figure A.4: a) 3-segment PWL logarithmic function and b) linear approximation y(x) of function g(x) 90 APPENDIX A. CIRCUIT IMPLEMENTATION OF PWL FUNCTIONS

y = m(X + |X0|) (A.3)

The current mirror conﬁguration for implementing each segment of the PWL logarithmic approximation is shown in Fig. A.5a and Fig. A.5b, for NMOS and PMOS implementation, respectively. The output current is given by eq. (A.4).

Iout = m(Iin+Ioﬀset) (A.4)

Figure A.5: Circuits for implementing each segment of a PWL logarithmic: a) NMOS and b) PMOS version

Convex decreasing PWL function

A convex decreasing PWL approximation function is shown in Fig. A.6a, implemented with three linear segments and a WTA circuit, because only the highest values of the segment set implement the approximation. The linear approximation of g(x) between breakpoints X1 and X2 is shown in Fig. A.6b and described by eq. (A.5).

y = m(X0 − X) (A.5)

The current mirrors that implement each segment of a convex decreasing PWL function are shown in Fig. A.7. The output current is given by eq. (A.6).

Iout = m(Ioﬀset − Iin) (A.6) 91

Figure A.6: a) 3-segment convex decreasing function and b) linear approximation y(x) of function g(x)

Figure A.7: Circuits for implementing each segment of a convex decreasing function: a) NMOS and b) PMOS version

Concave decreasing PWL function

A 3-segment concave decreasing PWL function is shown in Fig. A.8a and a linear approximation between breakpoints X1 and X2 is shown in Fig. A.8b. This linear approximation is also described by eq. (A.5). Opposite to the convex decreasing PWL function, now this concave function is implemented with a LTA circuit. Each segment is implemented also with the same current mirrors shown in Fig. A.7. 92 APPENDIX A. CIRCUIT IMPLEMENTATION OF PWL FUNCTIONS

Figure A.8: a) 3-segment concave decreasing function and b) linear approximation y(x) of function g(x) Appendix B

Setup

In this appendix the bias current sources, the Voltage to Current (V-I) and the Current to Voltage (I-V) converters used to measure the designed circuits in this thesis are described. Then the setup equipment used in the laboratory and the way each circuit of the thesis was connected to be tested are shown.

B.1 Current sources and V-I / I-V Converters

B.1.1 Current sources

Due to the fact that in the laboratory there are no current sources, this type of bias device was implemented using the three terminal adjustable current source LM 334. This three terminal integrated circuit permits to implement a regulated source or shrink current device. In Fig. B.1 and Fig. B.2 the LM 334 conﬁguration as a source or shrink current source, respectively, are shown. The value of Rs determines the current value:

V DD I = (B.1) B Rs

93 94 APPENDIX B. SETUP

Figure B.1: Source current

Figure B.2: Shrink current

B.1.2 Converters

All the circuits inside the AGC loop (WTAs, Exponential and Logarithmic circuits) work in current mode. In order to test each of these circuits independently, V-I and I-V converters were necessary to implement externally to the chips. These converters are based on a single operational ampliﬁer, and for this thesis the µA 741 OpAmp was used.

V-I converter

The V-I converters were used as input test blocks. This type of converter is shown in Fig. B.3 and B.4. The diﬀerence between these two conﬁgurations is B.1. CURRENT SOURCES AND V-I / I-V CONVERTERS 95 the converter output current direction. Thus, the output current is given by:

V in I = ± (B.2) X R

Figure B.3: Positive V-I converter

Figure B.4: Negative V-I converter

I-V converter

The I-V converters were used as output test blocks, in order to be able to visualize the output current in time domain in an oscilloscope as a voltage signal. The electric diagram is shown in Fig. B.5. The output voltage is given by:

V out = IoutR (B.3) 96 APPENDIX B. SETUP

Figure B.5: I-V converter

B.2 AGC blocks measurement setup

The individual AGC blocks and the AGC loop were implemented in two different chips. In Chip 1 the WTAs and Exponential circuits, described in Chapter 2, were fabricated. The Logarithmic amplifier, the VGA II (described in Chapter 3) and the AGC loop (described in Chapter 4) were fabricated in Chip 2. Thus, the laboratory equipment used to test and measure the different designed blocks in this thesis are listed as follows:

• Oscilloscope: Agilent 54624A.

• Triple Output DC Power Supply: Two HP (E3630A and E3631A) and two Agilent (E3630A and E3631A).

• Arbitrary Wave Generator: ArbStudio 1104.

• Arbitrary Wave Generator: Agilent 33120A.

• Multimeter: Agilent 34401A.

• Network Spectrum Analyzer: HP 4195A. B.2. AGC BLOCKS MEASUREMENT SETUP 97

Figure B.6: Test Setup 98 APPENDIX B. SETUP

WTAs

Figure B.7: WTA connections

WTA bias voltages and currents values:

• V DD = 2 .5V

• V p = 1 .2V

• V n = 1 .2V

• V g = 2 V

• IB = 25 µA B.2. AGC BLOCKS MEASUREMENT SETUP 99

Proposed PWL Exponential

Figure B.8: Proposed Exponential connections

Figure B.9: Exponential test board

PWL Exponential bias voltages and currents values:

• V DD = 2 .5V

• V p = 1 .2V

• V n = 1 .2V

• IB = 20 µA 100 APPENDIX B. SETUP

Proposed PWL Logarithm

Figure B.10: Logarithmic ampliﬁer connections

Figure B.11: Logarithm test board

PWL Logarithmic ampliﬁer bias voltages and currents values: • V DD = 2 .5V

• V p = 1 .2V

• V n = 1 .2V

• IB = 10 µA B.2. AGC BLOCKS MEASUREMENT SETUP 101

VGA II

Figure B.12: VGA II connections

VGA II bias voltages and currents values:

• V DD = 2 .5V

• V p = 1 .2V

• V p 1 = 1 .4V

• V n = 1 .2V

• V y = 1 V

• IB = 25 µA

• V cm = 1 .25 V

External devices:

• Balun: WB2010

• RL± = 10 kΩ 102 APPENDIX B. SETUP

AGC

Figure B.13: AGC connections

Figure B.14: VGA II and AGC test board

AGC bias voltages and currents values:

• V DD = 2 .5V

• V p = 1 .2V

• V p 2 = 1 .4V B.2. AGC BLOCKS MEASUREMENT SETUP 103

• V n = 1 .2V

• V y = 1 V

• IB = 25 µA

• V cm = 1 .25 V

• IREF = 25 µA

External devices:

• CAGC = 1 nF

• Balun: WB2010

• RL± = 10 kΩ

Figure B.15: AGC setup 104 APPENDIX B. SETUP

Figure B.16: AGC setup closer view

Figure B.17: Die photograph List of Figures

1.1 CharacteristicAGCbehavior...... 2 1.2 AGCbasicblockdiagram ...... 3 1.3 FeedforwardAGCblockdiagram...... 4 1.4 Release and Attack time: a) Input AGC signal and b) Output AGC signal...... 6

2.1 LazzaroWTA...... 13 2.2 SekerkiranWTA ...... 14 2.3 WTAOpenLoopcells: a)Lazzaroandb)Sekerkiran ...... 14 2.4 ProposedWTAI ...... 16 2.5 Simulated input and output current waveforms ...... 17 2.6 ProposedWTAII...... 18 2.7 Resolution response: a) Input currents and b) Internal voltage swing 20 2.8 Time response to abrupt input current changes:a) Input currents, b)Inputvoltageswingandc)Outputcurrents...... 21 2.9 Experimental input and output current waveforms ...... 22 2.10 Output simulated response for input waveforms of 1 MHz , 2 MHz and 5 MHz ...... 23 2.11 ProposedWTAIIlayout ...... 24 2.12 Exponential approximations compared to ex ...... 25

2.13 Linear approximation y(x) of function g(x) between ( X1, Y 1) and

(X2, Y 2) ...... 26 2.14 a) 40dB 5-segment PWL exponential with equidistant breakpoints (BP)andb)errorofthePWLapproximation ...... 27

105 106 LIST OF FIGURES

2.15 Exponential circuit based on current mirrors ...... 28 2.16 Currentmirror(CM)structure ...... 29 2.17 PWLblockresponse ...... 29 2.18 Total PWL Exponential output current and individual CMi currents 31 2.19 Simulated a) linear-in-dB ideal and PWL output current and b) totalerror ...... 31 2.20 Proposed exponential circuit block diagram...... 32 2.21 Current mirror to adjust oﬀset (Ioﬀset) and slope ( m) of a segment 33 2.22 WTA diagram within the exponential circuit ...... 33 2.23 DC response of the proposed PWL exponential circuit: (a) Indi-

vidual CM i output currents ( Io i) and (b) PWL Exponential output

current Iout ...... 35 2.24 Simulated a) linear-in-dB output current and b) total error.... 36 2.25 Experimental a) linear-in-dB output current and b) totalerror . . 37 2.26 Proposed PWL exponential pre-distortion circuit layout...... 38

3.1 Gilbertcell ...... 41 3.2 VGAIstructure...... 42

3.3 Gain vs. IC ...... 44 3.4 VGAblockdiagram...... 44 3.5 Complete V-I Converter implemented with triode transistors . . . 45 3.6 SecondGenerationCurrentConveyor ...... 46 3.7 ExponentialVGAdiagram ...... 47 3.8 Simulated exponential VGA transconductance ...... 47 3.9 Linear in dB simulated transconductance variation ...... 48 3.10 Measuredtransconductance ...... 49 3.11 Linear in dB measured transconductance variation ...... 49 3.12 ExponentialVGAlayout ...... 50 3.13 3-inputPatel’sLTA...... 53 3.14 Simulated input and output current waveforms ...... 53

3.15 Linear approximation y(x) of function g(x) between ( X1, Y 1) and

(X2, Y 2) ...... 54 LIST OF FIGURES 107

3.16 a) BPs in a six-segment PWL Logarithmic and b) Error of PWL approximation...... 55 3.17 Proposed logarithmic circuit block diagram ...... 56 3.18 Current mirror to adjust offset (Ioffset) and slope ( m) of a segment 56 3.19 LTA diagram within the logarithmic circuit...... 57 3.20 a) Ideal and simulated PWL logarithmic function and b) Error of PWLapproximation ...... 58 3.21 a) Ideal and measured PWL logarithmic function and b) Error of PWLapproximation ...... 59 3.22 Logarithmiccircuitlayout ...... 60 3.23 BlockdiagramofthePeakDetector...... 62 3.24 Blockdiagramofthefullwaverectifier ...... 63 3.25 PeakDetectordiagram ...... 63 3.26 Simulation response of the WTA Peak Detector ...... 64 3.27Detectorfilter ...... 65 3.28 Detectorfilterfrequencyresponse ...... 65 3.29 Detectortimeresponse ...... 66 3.30Detectorlayout ...... 66

4.1 AGCblockdiagram...... 70 4.2 GeneralizedAGCmodel ...... 71 4.3 Time response to an abrupt input decrement of: a) Linear and b) Linear-in-dBAGC ...... 74 4.4 Time response to an abrupt input increment of: a) Linear and b) Linear-in-dBAGC ...... 75 4.5 BlockdiagramoftheproposedAGCloop...... 76 4.6 InputandoutputAGCvoltage ...... 77 4.7 Time response of the proposed AGC as input decreases in 3dB- steps: a)InputVoltage,b)OutputVoltage ...... 78 4.8 Time response of the proposed AGC as input increases in 3dB- steps: a)InputVoltage,b)OutputVoltage ...... 78 108 LIST OF FIGURES

4.9 Time response for an abrupt input change of the proposed AGC: a)InputVoltage,b)OutputVoltage ...... 79 4.10 AGCmeasuredlayout ...... 80

A.1 a)Convexandb)Concavefunctions ...... 87 A.2 a) 3-segment PWL exponential function and b) linear approxima- tiony(x)offunctiong(x)...... 88 A.3 Circuits for implementing each segment of a PWL exponential: a) NMOSandb)PMOSversion ...... 89 A.4 a) 3-segment PWL logarithmic function and b) linear approxima- tiony(x)offunctiong(x)...... 89 A.5 Circuits for implementing each segment of a PWL logarithmic: a) NMOSandb)PMOSversion ...... 90 A.6 a) 3-segment convex decreasing function and b) linear approxima- tiony(x)offunctiong(x)...... 91 A.7 Circuits for implementing each segment of a convex decreasing function: a)NMOSandb)PMOSversion...... 91 A.8 a) 3-segment concave decreasing function and b) linear approxim- ationy(x)offunctiong(x) ...... 92

B.1 Sourcecurrent...... 94 B.2 Shrinkcurrent...... 94 B.3 PositiveV-Iconverter...... 95 B.4 NegativeV-Iconverter ...... 95 B.5 I-Vconverter ...... 96 B.6 TestSetup...... 97 B.7 WTAconnections...... 98 B.8 ProposedExponentialconnections...... 99 B.9 Exponentialtestboard ...... 99 B.10Logarithmicampliﬁerconnections ...... 100 B.11Logarithmtestboard ...... 100 B.12VGAIIconnections...... 101 B.13AGCconnections ...... 102 LIST OF FIGURES 109

B.14VGAIIandAGCtestboard...... 102 B.15AGCsetup ...... 103 B.16AGCsetupcloserview ...... 104 B.17Diephotograph ...... 104 110 LIST OF FIGURES Bibliography

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