ChapterChapter 1010 SemiconductorSemiconductor MemoriesMemories

Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan OutlineOutline • Introduction • Random Access Memories • Content Addressable Memories • Flash Memories

National Central University EE6013 VLSI Design 2 OverviewOverview ofof MemoryMemory TypesTypes

Semiconductor Memories

Read/Write Memory or Random Access Memory (RAM) Read Only Memory (ROM)

Random Access Non-Random Access Memory (RAM) Memory (RAM) •Mask (Fuse) ROM •Programmable ROM (PROM) •Erasable PROM (EPROM) •Static RAM (SRAM) •FIFO/LIFO •Electrically EPROM (EEPROM) •Dynamic RAM (DRAM) •Shift Register •Flash Memory •Register File •Content Addressable •Ferroelectric RAM (FRAM) Memory (CAM) •Magnetic RAM (MRAM)

National Central University EE6013 VLSI Design 3 MemoryMemory ElementsElements –– Memory Architecture • Memory elements may be divided into the following categories − Random access memory − Serial access memory − Content addressable memory • Memory architecture 2m+k bits row decoder row decoder 2n-k words row decoder row decoder

column decoder k n-bit address column mux, m-bit data I/Os sense amp, write buffers National Central University EE6013 VLSI Design 4 11--DD MemoryMemory ArchitectureArchitecture

S0 S0 Word0 Word0 S1 S1 Word1 Word1

S2 S2 Word2 Word2 A0 S3 S3 A1 Decoder Ak-1

Sn-2 Storage Sn-2 Wordn-2 element Wordn-2

Sn-1 Sn-1 Wordn-1 Wordn-1

m-bit m-bit Input/Output Input/Output n select signals are reduced n select signals: S0-Sn-1 to k address signals: A0-Ak-1

National Central University EE6013 VLSI Design 5 22--DD MemoryMemory ArchitectureArchitecture

S0 Word0 Wordi-1 S1

A0

A1

Ak-1 Row Decoder

Sn-1 Wordni-1

A 0 Column Decoder Aj-1

Sense Amplifier Read/Write Circuit

m-bit Input/Output

National Central University EE6013 VLSI Design 6 33--DD MemoryMemory ArchitectureArchitecture Row Column Block

Input/Output

National Central University EE6013 VLSI Design 7 ConceptualConceptual 22--DD MemoryMemory OrganizationOrganization

Address Memory Cell Row Decoder

Column decoder Data I/Os

National Central University EE6013 VLSI Design 8 MemoryMemory ElementsElements –– RAM Generic RAM circuit

Bit line conditioning Clocks

RAM Cell

n-1:k

Sense Amp, Column Write k-1:0 Mux, Write Buffers Clocks

Address write data read data

National Central University EE6013 VLSI Design 9 RAMRAM –– SRAM Cells

6-T SRAM cell

word line

bit - bit 4-T SRAM cell

word line

bit - bit

National Central University EE6013 VLSI Design 10 RAMRAM –– DRAM Cells

4-T dynamic RAM (DRAM) cell

word line

bit - bit 3-T DRAM cell

Read Write

Write Read data data National Central University EE6013 VLSI Design 11 RAMRAM –– DRAM Cells

1-T DRAM cell

word line word line

Vdd or bit bit Vdd/2

Layout of 1-T DRAM (right) Vdd word line

bit

National Central University EE6013 VLSI Design 12 RAMRAM –– DRAM Retention Time

Write and hold operations in a DRAM cell

WL=1 WL=0

on + off + Cs Vs + Cs Vs Input Vdd - - -

Write Operation Hold

V s = V max = V DD − V tn

Q max = C s (V DD − V tn )

National Central University EE6013 VLSI Design 13 RAMRAM –– DRAM Retention Time

Charge leakage in a DRAM Cell

Vs(t) WL=0 Vmax

IL Minimum logic 1 V1 voltage off + C V (t) s - s t th dQ I = − ( s ) L dt dV I = − C ( s ) L s dt ∆ V I ≈ − C ( s ) L s ∆ t

C s t h = | ∆ t |≈ ( ) ∆ V s I L National Central University EE6013 VLSI Design 14 RAMRAM –– DRAM Refresh Operation

As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the hold time is 50 ×10 −15 t = ×1 = 0.5µs h 1×10 −9 Memory units must be able to hold data so long as the power is applied. To overcome the charge leakage problem, DRAM arrays employ a refresh operation where the data is periodically read from every cell, amplified, and rewritten.

The refresh cycle must be performed on every cell in the array with a minimum refresh frequency of about

1 f refresh ≈ 2t h

National Central University EE6013 VLSI Design 15 RAMRAM –– DRAM Read Operation

WL=1

IL on + C C V V bit + s - s f Vbit - Vf

Q s = C sV s

Q s = C sV f + C bit V f

C s V f = ( )V s C s + C bit

This shows that Vf

National Central University EE6013 VLSI Design 16 RAMRAM –– SRAM Read Operation

Vdd precharge

precharge precharge

bit, -bit word line word

data

-bit bit

data

National Central University EE6013 VLSI Design 17 RAMRAM –– SRAM Read Operation

Vdd-Vtn precharge

precharge precharge Vdd bit, -bit word line word

data

-bit bit

data

National Central University EE6013 VLSI Design 18 RAMRAM –– SRAM Read Operation

bit, -bit

word

data

-bit bit load

V2 sense + sense - pass

V1 sense common pulldown

National Central University EE6013 VLSI Design 19 RAMRAM –– Differential Amplifier

Vdd

Mp1 Mp2 I

ISS

f Id2 Id1 Id1 Id2 d d’ Mn1 Mn2 Id1 Id2

ISS 0 d – d’ se Mn

ISS=Id1+Id2

National Central University EE6013 VLSI Design 20 RAMRAM –– Write Operation

N 5 N6 write data word

write

N3 N4

word

bit, -bit -bit bit N N write 1 2 cell, -cell write data

National Central University EE6013 VLSI Design 21 RAMRAM –– Write Operation

-bit bit Pbit

5V -cell cell 0V -write Nbit

write

ND PD write-data

National Central University EE6013 VLSI Design 22 RAMRAM –– Row Decoder

word<3> word<0>

word<2> word<1>

word<1> word<2>

word<0> word<3>

a<1> a<0> a<1> a<0>

National Central University EE6013 VLSI Design 23 RAMRAM –– Row Decoder

word

a1

a0 a0 a1 a2 a3

Complementary AND gate Pseudo-nMOS gate

National Central University EE6013 VLSI Design 24 RAMRAM –– Row Decoder

Symbolic layout of row decoder

output Vss Vdd Vss

National Central University EE6013 VLSI Design 25 RAMRAM –– Row Decoder

Symbolic layout of row decoder

Vdd

output

Vss a3 -a3 a2 -a2 a1 -a1 a0

National Central University EE6013 VLSI Design 26 RAMRAM –– Row Decoder Predecode circuit word<7>

word<6>

word<5>

word<4>

word<3>

word<2>

word<1>

word<0>

a2 a1 a0 National Central University EE6013 VLSI Design 27 RAMRAM –– Row Decoder

Actual implementation

a0

a4 a3 a2 a1 word

-a0 clk

Pseudo-nMOS example

a0 word

a1 a2 en

National Central University EE6013 VLSI Design 28 RAMRAM –– Column Decoder

bit<7> bit<6> bit<5> bit<4> selected-data bit<3> bit<2> bit<1> bit<0>

to sense amps and write ckts -bit<7> -bit<6> -bit<5> -bit<4> -selected-data -bit<3> -bit<2> -bit<1> -bit<0>

a0-a0 a1 -a1 a2 -a2 National Central University EE6013 VLSI Design 29 RAMRAM –– Multi-port RAM

write read0 read1

-rbit1 -rbit0 -rwr_datarwr_data rbit0 rbit1

write read0 read1 -rbit1 -rwr_datarwr_data rbit0 National Central University EE6013 VLSI Design 30 RAMRAM –– Expandable Reg. File Cell

wr-b addr<3:0>

rd-a addr<3:0>

rd-b addr<3:0>

write-data read-data 0 read-data 1 write-data

write-enable(row) read0 read1 Write-enable (column) National Central University EE6013 VLSI Design 31 SpecificSpecific MemoryMemory –– FIFO

Two port RAM

Write-Data Read-Data Write-Address Read-Address

Write-Clock Read-Clock

Full Empty

FIFO read address control design

WP

0 0 1 1 Read rst 1 clk incrementer

National Central University EE6013 VLSI Design 32 SpecificSpecific MemoryMemory –– FIFO

FIFO address control design

0 -1 0 decrementer 1 0 1 1

rst 1 Read clk incrementer

Empty Read Write Full

National Central University EE6013 VLSI Design 33 SpecificSpecific MemoryMemory –– LIFO

LIFO (Stack)

Require: Single port RAM One address counter Empty/Full detector

Algorithm: Write: write current address Address=Address+1 Read: Address=Address-1 read current address Address Empty: Address=0 Full : Address=FFF…

National Central University EE6013 VLSI Design 34 SpecificSpecific MemoryMemory –– SIPO SIPO cell design

Read

Parallel-data

Sh-In Sh-Out

Clk -Clk

SIPO Read

Sh-In

Clk

National Central University EE6013 VLSI Design 35 SpecificSpecific MemoryMemory –– Tapped Delay Line

delay<5> delay<4> delay<3> delay<2> delay<1> delay<0>

0 0 0 0 0 0

din 1 1 1 1 1 1 dout

Clk 32-stage SR 16-stage SR 8-stage SR 4-stage SR 2-stage SR 1-stage SR

National Central University EE6013 VLSI Design 36 NonNon--volatilevolatile MemoryMemory –– ROM

4x4 NOR-type ROM

Vdd

WL0 GND WL1

WL2 GND

WL3

BL0 BL1 BL2 BL3

National Central University EE6013 VLSI Design 37 NonNon--volatilevolatile MemoryMemory –– ROM

4x4 NAND-type ROM

Vdd

BL0 BL1 BL2 BL3 WL0

WL1

WL2

WL3

National Central University EE6013 VLSI Design 38 SpecificSpecific MemoryMemory –– CAM • Content addressable memories (CAMs) play an important role in digital systems and applications − such as communication, networking, data compression, etc. • Each storage element of a CAM has the hardware capability to store and compare its contents with the data broadcasted by the control unit • CAM types − dynamic or static − binary or ternary • The binary static CAM is discussed

National Central University EE6013 VLSI Design 39 DifferenceDifference BetweenBetween RAMRAM andand CAMCAM

Address RAM Data R/W

Hit Data CAM Cmd Address

National Central University EE6013 VLSI Design 40 CAMCAM –– Applications

CAM architecture

CAM Memory Array Data Match NxM-bit words

Cache architecture

CAM RAM Match 0 Word 0 Match 1 Word 1 CAM Memory Array Match 2 Match 3 Word 2 Data In NxM-bit words Word 3 Match 4 Word 4 Match 5 Word 5 Data I/Os

National Central University EE6013 VLSI Design 41 CAMCAM –– Architecture

Comparand Register

Mask Register

Address Hit Input Memory Array Address Valid Bit

Responder Output Address Decoder

I/O Register

National Central University EE6013 VLSI Design 42 CAMCAM –– Basic Components • Comparand Register − It contains the data to be compared with the content of the memory array • Mask Register − It is used to mask off portions of the data word(s) which do not participate in the operations • Memory Array − It provides storage and search (compare) medium for data • Responder − It indicates success or failure of a compare operation

National Central University EE6013 VLSI Design 43 CAMCAM –– Binary Cell

CAM cell

-bit bit

WL

-d d

M2 M1 Match

M3

National Central University EE6013 VLSI Design 44 CAMCAM –– Word Structure

bit[0] bit[0] bit[w-1] bit[w-1]

W i 10 Vdd

P

M i

1010

comparison logic

National Central University EE6013 VLSI Design 45 CAMCAM –– Organization

CAM circuit Match Data In Read Data (Test)

Normal RAM Read/Write Circuitry

Hit

Match0

Match1

Match2

Match3 precharge

National Central University EE6013 VLSI Design 46 NonNon--volatilevolatile MemoryMemory –– Flash Memory • Flash memory − A nonvolatile, in-system-updateable, high-density memory technology that is per-bit programmable and per-block or per-chip erasable • In-system updateable − A memory whose contents can be easily modified by the system processor • Block size − The number of cells that are erased at the same time • Cycling − The process of programming and erasing a flash memory cell

National Central University EE6013 VLSI Design 47 FlashFlash MemoryMemory –– Definition • Erase − To change a flash memory cell value from 0 to 1 • Program − To change a flash memory cell value from 1 to 0 • Endurance − The capability of maintaining the stored information after erase/program/read cycling • Retention − The capability of keeping the stored information in time

National Central University EE6013 VLSI Design 48 BasicsBasics • How can a memory cell commute from one state to the others independently of external condition? − One solution is to have a transistor with a threshold voltage that can change repetitively from a high to a low state − The high state corresponding to the binary value “1” − The low state corresponding to the binary value “0” • Threshold voltage of a MOS transistor

− VT = K − Q'/ Cox − K is a constant depending on the gate and substrate material, doping, and gate oxide thickness − Q’ is the charge in the gate oxide

− Cox is the gate oxide capacitance

National Central University EE6013 VLSI Design 49 FloatingFloating GateGate TransistorTransistor • Floating gate (FG) transistor

Control Gate

CFC Floating Gate

CFS CFB CFD Source Drain

Substrate • Energy band diagram of an FG transistor

Substrate Floating Control Gate Gate

National Central University EE6013 VLSI Design 50 FlashFlash MemoryMemory –– Threshold Voltage

• When the voltages (VCG & VD) are applied to the control gate and the drain, the voltage at the floating gate (VFG) by capacitive coupling is expressed as Q C C − V = FG + FC V + FD V FG C C CG C D − total total total Ctotal = CFC + CFS + CFB + CFD • The minimum control gate voltage required to turn on the control gate is Ctotal QFG CFD − VT (CG) = VT (FG) − − VD CFC CFC CFC − where VT(FG) is the threshold voltage to turn on the floating gate transistor • The difference of threshold voltages between two memory data states (“0” and “1” ) can be expressed as ∆QFG − ∆VT (CG) = − CFC

National Central University EE6013 VLSI Design 51 FlashFlash MemoryMemory –– Structures • Two major flash memory structures − NOR & NAND • NOR structure − Simplest − Dual power supply − Large block size • NAND structure − Intermediate block size − High-speed and high density − For storage applications

National Central University EE6013 VLSI Design 52 FlashFlash MemoryMemory –– Structures

Bit line Basic Bit line Basic unit unit Select WL 1 gate (drain)

WL 2 WL 1 WL 2

WL 3 WL 3 WL 4

WL N WL N Select gate (source) Source line NOR structure NAND structure

National Central University EE6013 VLSI Design 53 FlashFlash MemoryMemory –– Program Operation • Program operation of the Intel’s ETOX flash cells (NOR structure) − Apply 6V between drain and source ∗ Generates hot electrons that are swept across the channel from source to drain − Apply 12 V between source and control gate ∗ The high voltage on the control gate overcomes the oxide energy barrier, and attracts the electrons across the thin oxide, where they accumulate on the floating gate − Called channel hot-electron injection (HEI) +12V Control Gate GND Floating Gate +6V

Source Drain

Substrate

National Central University EE6013 VLSI Design 54 FlashFlash MemoryMemory –– Erase Operation • Erase operation of the Intel’s ETOX flash cells (NOR structure) − Floating the drain, grounding the control gate, and applying 12V to the source − A high electric field pulls electrons off the floating gate − Called Fowler-Nordheim (FN) tunneling

GND Control Gate +12V Floating Gate

Source Drain

Substrate

National Central University EE6013 VLSI Design 55 FlashFlash MemoryMemory –– Erase Operation • Threshold voltage depends on oxide thickness • Flash memory cells in the array may have slightly different gate oxide thickness, and the erase mechanism is not self-limiting • After an erase pulse we may have “typical bits” and “fast erasing bits”

VT typical bit

fast erasing bit 0 log t National Central University EE6013 VLSI Design 56 FlashFlash MemoryMemory –– Read Operation • Read operation of the Intel’s ETOX flash cells (NOR structure) − Apply 5V on the control gate and drain, and source is grounded

− In an erased cell, the VC>VT ∗ The drain to source current is detected by the sense amplifier

− In a programmed cell, the VC

Source Drain

Substrate

National Central University EE6013 VLSI Design 57