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Next Generation SDN Switches Using Programming Protocol-Independent Packet Processors

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Next Generation SDN Switches Using Programming Protocol-Independent Packet Processors DEGREE PROJECT IN ELECTRICAL ENGINEERING, SECOND CYCLE, 30 CREDITS STOCKHOLM, SWEDEN 2018 Next Generation SDN Switches Using Programming Protocol- Independent Packet Processors TIJO VARGHESE THAZHONE KTH ROYAL INSTITUTE OF TECHNOLOGY SCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE KTH ROYAL INSTITUTE OF TECHNOLOGY MASTER THESIS REPORT Next Generation SDN Switches Using Programming Protocol-Independent Packet Processors Author: Company supervisor: Tijo Varghese Thazhone Magnus Svevar (Infinera) Examiner: Academic supervisor: Dr. Zhonghai Lu Yuan Yao A thesis submitted in fulfillment of the requirements for the degree of Master of Science in the School of Electrical Engineering and Computer Science Stockholm, Sweden November 30, 2018 iii Abstract Over recent years, Software Defined Networking has enabled operators to control the network and realize new networking topologies. With increasing network traf- fic and protocol formats that aim at managing the traffic efficiently, the capabilities offered by Software Defined Networking alone are currently limited by the under- lying fixed hardware infrastructure. The inflexibility involved in redesigning the hardware forces the bottom-up approach defined by switch vendors in describing the network and limits the capabilities offered to operators for further innovation. To meet the demands of ensuring a higher degree of flexibility to design, test and guarantee a faster time to market, the concept of Softly Defined Networks was in- troduced. The idea in addition to offering the conventional advantages of Software Defined Networking is based upon implementing a re-programmable data-plane. Field-Programmable Gate Arrays offered a higher degree of flexibility and capa- bility to handle such designs. Programming Protocol-independent Packet Proces- sors(P4) is a high-level language continuously evolving to define data-planes for various networking devices. The aim of P4 is for network operators to customize the underlying hardware with minimum constraints and ease, independent of the target. Therefore, the three major goals while defining such a language revolved around reconfigurability of hardware after being deployed, protocol independence to permit customization without constraints and target independence for users to be less concerned of the underlying hardware. Recent advances in P4 with the added support in terms of compatible targets and compilers have made P4 a viable oppor- tunity to realize a re-programmable hardware. This work contributes towards exploring the ease of incorporating the capabilities of P4 in realizing a flexible data-plane. To achieve the same and study its characteristics a supporting two lane hardware pipeline is proposed that is capable of accommo- dating P4 upon a Kintex 7 FPGA. Primarily, a custom P4 module is defined that is capable of performing L2 operations upon a double tagged Ethernet frame using an appropriate architecture model. Subsequently, to integrate the P4 description on hardware the proposed supporting pipeline is implemented at a line rate of 10Gbps using the essential building blocks that help in observing the desired processing. Using a test setup, the design shall be further tested for the expected data-plane ac- tivity based upon the populated match-action rules. In terms of resource utilization, the overall design consumes less than 15% of the available resources and incurs an average latency of 5.71us. In addition to the ease of customization compared to the conventional fixed data-plane descriptions, it is vital to analyze the cost inherited while adopting P4. The final design is therefore studied in terms of resource utiliza- tion and latency by increasing the complexity of the P4 definition with regard to the number of headers, tables and write operations(H-T-W) for the adopted compiler. In the case of eight headers, tables and write operations(8H-8T-8W), there is an aver- age latency of 8.01us and the P4 description alone demands 51536 LUTs, 77789 FFs and 118.5 BRAMs in terms of resource utilization. Finally, the article discusses the extent to which the proposed top-down approach is implemented and is capable of redefining the network as we know it. v Abstrakt Under de senaste åren har Software Defined Networking gjort det möjligt för op- eratörer att styra nätverket och implementera nya nätverkstopologier. Med ökande nätverkstrafik och nya protokoll som syftar till att hantera trafiken effektivt, är de möjligheter som erbjuds av Software Defined Networking för närvarande begränsat av den underliggande fixa hårdvaruarkitekturen. Den inflexibla hårdvaran tvingar fram det ”bottom-up-” tillvägagångssätt som definieras av switchleverantörer när det gäller att beskriva nätverket och begränsar de möjligheter som erbjuds operatör- erna för att styra och innovera i sina nät. För att möta kraven på att skapa en högre grad av flexibilitet för att designa, testa och garantera en snabbare tid till marknaden, introducerades begreppet Softly Defined Networks. Tanken, utöver att erbjuda de konventionella fördelarna med Software Defined Networking, bygger på att man implementerar ett omprogrammerbart dat- aplan. Field-Programmable Gate Arrays erbjuder en högre grad av flexibilitet och förmåga att hantera sådana konstruktioner. Programming Protocol-independent Packet Processors(P4) är ett språk på hög nivå som kontinuerligt utvecklas för att definiera dataplanet för olika nätverksenheter. Målet med P4 är att nätverksoper- atörerna lätt ska kunna anpassa den underliggande hårdvaran med minimala be- gränsningar oberoende av leverantör av hårdvara. De tre huvudmålen när man definierade ett sådant språk handlade om omkonfigurerbarhet av hårdvaran efter att ha blivit utplacerad, protokolloberoende för att möjliggöra anpassning utan begrän- sningar och leverantörsoberoende för att användarna skulle vara mindre oroade över den underliggande hårdvaran. Nya framsteg i P4 när det gäller stöd för kom- patibla hårdvaror och kompilatorer har gjort P4 till en tänkbar kandidat för att re- alisera en omprogrammerbar hårdvara. Detta arbete bidrar till att utforska hur enkelt det är att integrera P4:s förmåga att re- alisera ett flexibelt dataplan. För att uppnå detta och studera dess egenskaper föres- lås en hårdvaruimplementation av L2 i två pipelines av P4 på en Kintex 7 FPGA. I första hand definieras en anpassad P4-modul som kan utföra L2-operationer på en dubbeltaggad Ethernet-ram med hjälp av en lämplig arkitekturmodell. Därefter im- plementeras P4-beskrivningen av hårdvaran på den föreslagna arkitekturmodellen med en hastighet av 10 Gbps med hjälp av de byggblock som krävs för att kunna ob- servera beteendet. Med hjälp av en testupptällning testas konstruktionen för att se om den uppfyller den förväntade dataplanaktiviteten baserat på de uppsatta match- ningsreglerna. När det gäller resursutnyttjandet förbrukar designen mindre än 15% av de tillgängliga resurserna och uppnår en genomsnittlig latens på 5,71us. Föru- tom den enkla implementeringen, jämfört med en konventionell fix beskrivning av data-planet, är det viktigt att analysera kostnaden vid införandet av P4. Den slut- liga konstruktionen studeras därför med avseende på resursutnyttjande och latens genom att öka komplexiteten i P4-definitionen med avseende på antalet rubriker, tabeller och skrivoperationer (H-T-W) för den antagna kompilatorn. När det gäller åtta ”headers”, tabeller och skrivoperationer (8H-8T-8W), är det en genomsnittlig latens på 8.01us och P4-beskrivningen ensam kräver 51536 LUTs, 77789 FFs och 118,5 BRAMs vad gäller resursutnyttjande. Slutligen diskuterar artikeln hur den föres- lagna top-down-metoden är implementerad och hur den kan omdefiniera nätverket som vi känner till det. vii Acknowledgements ““Tell me and I forget, teach me and I may remember, involve me and I learn.”” -Benjamin Franklin The contents of this report would be incomplete without acknowledging the con- stant guidance and support I received throughout the thesis work. First and fore- most I am grateful to God for helping me with the patience and capability necessary to see the thesis through. The opportunity to work on this topic in collaboration with Infinera was an abso- lute pleasure. It would have been impossible to state the findings mentioned in this report without the guidance, support and resources granted by Infinera. The open work culture and supportive colleagues helped make new friends and enjoy my work. I would like to express my gratitude to my industrial supervisor Magnus Svevar for helping me with all the necessary resources and support to better under- stand the topic. Hannah Dysenius helped manage the project work and made sure there was progress in a systematic fashion. I am truly thankful to them both for their patience and understanding with regard to all the unmet deadlines. Kenth Erikson, Dr. Jue Shen and Stefanos Kyri with their years of experience and knowledge in the field offered valuable guidance during various stages of the project work. It was absolutely an honor to have been a part of Infinera and learn more about the topic. This thesis work was undertaken to fulfill the requirements for the degree of Mas- ter of Science at KTH Royal Institute of Technology, Stockholm with Dr. Zhonghai Lu as the examiner and Yuan Yao as the academic supervisor. I specially thank Dr. Zhonghai Lu for constantly reviewing the status of my thesis work and helping me refine this report. Finally, I would like to thank my family for their incessant love and encouragement that has helped me throughout my life. ix Contents Abstract iii Abstraktv
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