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Altivec Vector Processor, Part 2: Enhancements TM June 2012 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Next-generation QorIQ products built on e6500 Power Architecture® technology include an enhanced AltiVec vector processor. This session describes new instructions for extended support for misaligned vectors, support for handling head and tail vectors, and the long-awaited capability to move from general purpose to vector registers. Learn about the performance improvements resulting from enhancement to both AltiVec and the e6500 core. This session compliments AltiVec Vector Processor Introduction for Newcomers (Part 1), but those who are already familiar with SIMD and AltiVec processors can attend as a stand-alone session. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, TM 2 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. • Overview of AltiVec enhancements in e6500 core • More detail on each change • Some limitations • Unaligned loads and stores in-depth - memcpy Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, TM 3 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. • AltiVec e6500 core technology is essentially the same as AltiVec technology from the 74xx processors except the following: • Adds new instructions for computing absolute differences • vabsdub – absolute differences (byte) • vabsduh – absolute differences (halfword) • vabsduw – absolute differences (word) • Adds new instructions for moving data from GPRs to VRs • mvidsplt <64> and mviwsplt move data from 2 GPRs into a vector register • Adds new instructions for dealing with misaligned vectors more easily • lvtlx[l], lvtrx[l], stvflx[l], stvfrx[l] – load/store vector to/from left [LRU] • lvswx[l], stvswx[l] – load/store vector with left/right swap [LRU] • Adds new instructions for dealing with elements of vectors • lvexbx, stvebx – load/store vector element indexed byte • lvexhx, stvehx – load/store vector element indexed halfword • lvexwx, stvewx – load/store vector element indexed word • These allow loading/storing of arbitrary elements to arbitrary addresses Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, TM 4 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Feature Original Power ISA Description AltiVec AltiVec Definition Definition Little-endian Supported Not Supported Little-endian byte ordering is not supported on Power ISA AltiVec definition. Data stream Supported Not Supported dss, dssall, dst, dstt, dstst, and instructions dststt instructions are not supported on Power ISA AltiVec definition. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, TM 5 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Feature Original Power ISA Description AltiVec AltiVec Definition Definition IVORs Not Supported Supported IVORs added for AltiVec unavailable interrupt and AltiVec assist interrupt. Move from Not Supported Supported mvidsplt <64> and mviwsplt GPR to VR instructions move data from 2 GPRs into a vector register. Absolute Not Supported Supported Absolute difference instructions differences vabsdub, vabsduh, and vabsduw compute the unsigned absolute differences. These are useful for motion estimation in video processing. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, TM 6 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Feature Original Power ISA Description AltiVec AltiVec Definition Definition Extended Not Supported Supported Load vector to left and right (lvtlx[l], support lvtrx[l]), load vector with left-right swap (lvswx[l]), load vector for misaligned for swap merge (lvsm). Store vector vectors from left and right (stvflx[l], stvfrx[l]), store vector with left-right swap (stvswx[l]). Extended Not Supported Supported Load vector element indexed [byte, support half-word, word] indexed (lvexbx, lvexhx, lvexwx) loads specified for handling elements from an arbitrary address head zeroing the rest of the register. Store and tail of vector element indexed [byte, half- word, word] indexed (stvexbx, vectors stvexhx, stvexwx) stores specified elements to an arbitrary address. Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, TM 7 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Feature Original Power ISA Description AltiVec AltiVec Definition Definition External PID Not Supported Supported Load and store vector by external instructions for PID (lvepx[l], stvepx[l]) for moving data efficiently across address loading and spaces. storing VRs Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, TM 8 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. • dss (Data Stream Stop), dssall (stop ALL prefetch engines), dst (Data Stream Touch), dstt (Touch Transient), dstst (Data Stream Touch for STore), and dststt (Touch for Store Transient), instructions were present in the first definition of AltiVec technology for PowerPC processors. These instructions provided software initiated streaming prefetch controls. • In Power ISA these instructions are no longer defined, and streaming is performed by variants of the dcbt instruction or by hardware prefetchers. Cache stashing could be considered an alternative as well. • For Freescale
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