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CD40106B CMOS Hex Schmitt-Trigger Inverters Datasheet

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CD40106B CMOS Hex Schmitt-Trigger Inverters Datasheet Product Order Technical Tools & Support & Folder Now Documents Software Community CD40106B SCHS097F –NOVEMBER 1998–REVISED MARCH 2017 CD40106B CMOS Hex Schmitt-Trigger Inverters 1 Features 3 Description The CD40106B device consists of six Schmitt-Trigger 1• Schmitt-Trigger Inputs inputs. Each circuit functions as an inverter with • Hysteresis Voltage (Typical): Schmitt-Trigger input. The trigger switches at different – 0.9 V at VDD = 5 V points for positive- and negative-going signals. The – 2.3 V at VDD = 10 V difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as – 3.5 V at VDD = 15 V hysteresis voltage (VH). • Noise Immunity Greater Than 50% The CD40106B device is supplied in ceramic • No Limit On Input Rise and Fall Times packaging (J) as well as standard packaging (D, N, • Standardized, Symmetrical Output Characteristics NS, PW). All CD40106B devices are rated for –55°C • For Quiescent Current at 20 V to +125°C ambient temperature operation. • Maximum Input Current Of 1 µA at 18 V Over Full Device Information(1) Package Temperature Range: PART NUMBER PACKAGE BODY SIZE (NOM) – 100 nA at 18 V and 25°C CD40106BF CDIP (14) 6.92 mm x 19.94 mm • Low V and V Current During Slow Input DD SS CD40106BE PDIP (14) 6.30 mm x 19.31 mm Ramp CD40106BM SOIC (14) 3.90 mm x 8.65 mm • 5-V, 10-V, and 15-V Parametric Ratings CD40106BNSR SO (14) 5.30 mm x 10.20 mm 2 Applications CD40106BPWR TSSOP (14) 4.40 mm x 5.00 mm (1) For all available packages, see the orderable addendum at • Wave and Pulse Shapers the end of the data sheet. • High-Noise-Environment Systems • Monostable Multivibrators • Astable Multivibrators Logic Diagram A G 1 (3, 5, 9, 11, 13) 2 (4, 6, 8, 10, 12) VDD VSS Copyright © 2017, Texas Instruments Incorporated All inputs protected by the protection network shown to the right 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CD40106B SCHS097F –NOVEMBER 1998–REVISED MARCH 2017 www.ti.com Table of Contents 1 Features .................................................................. 1 8.3 Feature Description ................................................ 13 2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 13 3 Description ............................................................. 1 9 Application and Implementation ........................ 14 4 Revision History..................................................... 2 9.1 Application Information .......................................... 14 5 Pin Configuration and Functions ......................... 3 9.2 Typical Applications ................................................ 14 6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 16 6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 16 6.2 ESD Ratings ............................................................ 4 11.1 Layout Guidelines ................................................ 16 6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example .................................................... 16 6.4 Thermal Information.................................................. 4 12 Device and Documentation Support ................. 18 6.5 Electrical Characteristics: Static................................ 5 12.1 Receiving Notification of Documentation Updates 18 6.6 Electrical Characteristics: Dynamic........................... 8 12.2 Community Resources.......................................... 18 6.7 Typical Characteristics.............................................. 9 12.3 Trademarks ........................................................... 18 7 Parameter Measurement Information ................ 11 12.4 Electrostatic Discharge Caution............................ 18 8 Detailed Description ............................................ 13 12.5 Glossary ................................................................ 18 8.1 Overview ................................................................ 13 13 Mechanical, Packaging, and Orderable 8.2 Functional Block Diagram ....................................... 13 Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (September 2016) to Revision F Page • Changed incorrect pin descriptions to match package drawing ............................................................................................ 3 Changes from Revision D (August 2003) to Revision E Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Added Thermal Information table ........................................................................................................................................... 4 2 Submit Documentation Feedback Copyright © 1998–2017, Texas Instruments Incorporated Product Folder Links: CD40106B CD40106B www.ti.com SCHS097F –NOVEMBER 1998–REVISED MARCH 2017 5 Pin Configuration and Functions D, J, N, NS, PW Packages 14-Pin SOIC, CDIP, PDIP, SO, TSSOP Top View A 1 14 VDD G = A 2 13 F B 3 12 L = F H = B 4 11 E C 5 10 K = E I = C 6 9 D VSS 7 8 J = D Not to scale Pin Functions PIN I/O DESCRIPTION NO. NAME 1 A I Channel A input 2 G = A O Channel A inverted output 3 B I Channel B input 4 H = B O Channel B inverted output 5 C I Channel C input 6 I = C O Channel C inverted output 7 VSS — Ground 8 J = D O Channel D inverted output 9 D I Channel D input 10 K = E O Channel E inverted output 11 E I Channel E input 12 L = F O Channel F inverted output 13 F I Channel F input 14 VDD — Power supply Copyright © 1998–2017, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CD40106B CD40106B SCHS097F –NOVEMBER 1998–REVISED MARCH 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT (2) DC supply voltage, VDD –0.5 20 V Input voltage, all inputs –0.5 VDD + 0.5 V DC input current, any one input ±10 mA TA = –55°C to +100°C 500 Power dissipation, PD (3) mW TA = 100°C to 125°C 200 Device dissipation per output transistor 100 mW Maximum junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Voltages referenced to VSS terminal (3) Derate linearity at 12 mW/°C 6.2 ESD Ratings VALUE UNIT (1) Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 2000 V(ESD) V discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage 3 18 V Operating temperature, TA –55 125 °C 6.4 Thermal Information CD40106B THERMAL METRIC(1) D (SOIC) N (PDIP) NS (SO) PW (TSSOP) UNIT 14 PINS 14 PINS 14 PINS 14 PINS Junction-to-ambient R 86.1 51.3 83.5 114.1 °C/W θJA thermal resistance Junction-to-case (top) R 44.3 38.6 41.5 39.1 °C/W θJC(top) thermal resistance Junction-to-board R 40.6 31.2 42.2 56.9 °C/W θJB thermal resistance Junction-to-top ψ 11.6 23.4 13.1 3.1 °C/W JT characterization parameter Junction-to-board ψ 40.3 31.3 41.8 56.2 °C/W JB characterization parameter (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 4 Submit Documentation Feedback Copyright © 1998–2017, Texas Instruments Incorporated Product Folder Links: CD40106B CD40106B www.ti.com SCHS097F –NOVEMBER 1998–REVISED MARCH 2017 6.5 Electrical Characteristics: Static over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = –55°C 1 TA = –40°C 1 VIN = 0 or 5, VDD = 5 TA = 25°C 0.02 1 TA = 85°C 30 TA = 125°C 30 TA = –55°C 2 TA = –40°C 2 VIN = 0 or 10, VDD = 10 TA = 25°C 0.02 2 TA = 85°C 60 TA = 125°C 60 IDDmax Quiescent device current µA TA = –55°C 4 TA = –40°C 4 VIN = 0 or 15, VDD = 15 TA = 25°C 0.02 4 TA = 85°C 120 TA = 125°C 120 TA = –55°C 20 TA = –40°C 20 VIN = 0 or 20, VDD = 20 TA = 25°C 0.04 20 TA = 85°C 600 TA = 125°C 600 TA = –55°C 2.2 TA = –40°C 2.2 VDD = 5 TA = 25°C 2.2 2.9 TA = 85°C 2.2 TA = 125°C 2.2 TA = –55°C 4.6 TA = –40°C 4.6 Positive trigger threshold V min V = 10 T = 25°C 4.6 5.9 V P voltage DD A TA = 85°C 4.6 TA = 125°C 4.6 TA = –55°C 6.8 TA
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