designideas Edited by Bill Travis

DPP adds versatility to VFC Chuck Wojslaw, Catalyst Semiconductor, Sunnyvale, CA he basic VFC (voltage-to-frequen- cy converter) in Figure 1 R2 Tcomprises an integrator Figure 1 (IC1) and a Schmitt-trigger circuit (IC2). VIN The integrator converts the dc input volt- R1 C1 R3 R4 age,VIN, to a linear voltage ramp, and the Schmitt trigger sets the limits of the in- _ + tegrator’s output voltage. IC1 IC2 VOUT around both circuits provides the condi- + _ INTEGRATOR SCHMITT tion for oscillation. The DPP (digitally TRIGGER programmable potentiometer) in Figure 2 adds programmable limits to the Schmitt trigger and adds two powerful This schematic depicts a basic voltage-to-frequency converter. features to the VFC. First, the scale or conversion factor is programma- Figure 2 D R2<

Power circuit terminates DDR DRAMs Ron Young, Maxim Integrated Products, Sunnyvale, CA

DR (double-data-rate) SDRAMs put current as high as 6A. IC1 includes a an inverting amplifier. This amplifier find use in high-speed memory sys- step-down controller and two linear-reg- compares VDD/2 (created by R1 and R2) tems in workstations and servers. ulator controllers and operates with in- with V from IC and generates an er- D REF 1 The memory ICs operate with 1.8 or 2.5V put voltages of 4.5 to 28V. ror signal that connects via R3 to IC1’s FB supply voltages and require a reference IC1’s fixed-frequency, 200-kHz PWM pin, thereby forcing VOUT to track VDD/2. voltage equal to half the supply voltage controller maintains the output voltage A 10-mA load, R , is necessary to bias the ϭ 4 (VREF VDD/2). In addition, the logic out- by sourcing and sinking current. Maxi- inverting amplifier for accurate tracking. puts terminate with a to the ter- mum sink current equals the maximum VOUT can track VDD/2 for VDD in the range mination voltage, VTT, which equals and source current, though the sink current 1 to 4V. tracks V .V must source or sink cur- has no current limiting. When sinking REF TT ϭ Ϯ rent while maintaining VTT VREF current, the device returns some current 0.04V. The circuit of Figure 1 provides to the input supply. To implement the

the termination voltage for both 1.8 and tracking function, one of IC1’s extra lin- Is this the best Design Idea in this 2.5V memory systems and delivers out- ear-regulator controllers is configured as issue? Select at www.edn.com.

Figure 1 5V INPUT 1200 ␮F 4.7 ␮F CMPSH-3 10V 10V MV-AX

22 ␮F (ן10V (4 15 16 VP VL 14 9 BST ILIM ␮ 15k 2 0.1 F COMP 13 FDS6690A EC31 DH QS03L ␮ 4.7 1.5 H DO5022P 22 nF 1000 pF 12 LX 1.25V 6A EC31 11 FDS6690A DL QS03L IC + 1200 ␮F 1 4.7 MAX1864T 10 2.5V GND 5V OS-CON 3 OUT 1OOk R5 4 10k 1 FB POK POK

B2 5 R3 5V 10k R FB2 6 7 CMPT 1 ␮F + Ϫ 220 330 pF 3906 10V

1.24V B3 7 22.1k

8 R4 FB3 22 ␮F 100 22.1k 10V

R1 1k 2.5V 0.1 ␮F R2 1k

This circuit generates the termination voltage for DDR synchronous DRAMs.

100 edn | November 14, 2002 www.edn.com designideas Circuit protects bus from 5V swings Said Jackson, Equator Technologies Inc, Campbell, CA

C1 he circuit in Figure 1 auto- 0.01 ␮F matically detects voltage 5V Figure 1 5 3 Tand protects a bus, such VCC GND 2 4 #IC1 + PCI_SERRמ as a 3.3V-limited PCI bus, from 5V NC7SZ125 signal-level swings.You can also use 1 the circuit to determine bus-voltage 5V swings within one bus-cycle for set- 4 10 2 PR 5 12 PR 9 ting appropriate termination volt- DQ DQ IC2A IC2B 5V 3 6 11 8 ages of protection or termi- PCI_CLK CLK Q CLK Q CL CL nation resistors. Today’s deep- R1 1 74LVC74A 13 submicron VLSI-manufacturing PLACE CLOSE 3.3 74LVC74A TO PCI BUS 0603 PCI_RST# 1 5 R techniques sometimes require cir- PCI Q VCC 4 12V 1.5k AD10 R2 0603 R3 0603 2 C2 C LS1 GND IC ␮ + 3 0603 cuits to limit I/O voltages to 3.3V 3 0.1 F 10 ␮F P9948-ND 1 2k 2k 3 4 PANSONIC 0805 0805 מIN+ IN signal swings. Connecting such cir- PCI_AD[31..0] 1% 1% EFB-CB37C11 2 METAL METAL cuits to a bus with 5V level-swing MAX999 C TOP VIEW 5V BUS B Q1 cards could damage the circuitry. 1.88VϮ5% WARNING 5V BUZZER The circuit in Figure 1 can accu- R6 E FMMT4123CT-ND R5 C4 15k 0.1 ␮F 9k SOT-23 rately and—within one bus cycle— 1% METAL 1% METAL 0805 JP1 0603 0603 detect a level swing larger than 3.3V 1 ENABLE on any bus and, upon a fault situa- 2 PROTECTION tion, generate a reset signal and an HEADER2 alarm output to notify the user and This circuit provides both an audible alarm and an error flag when an overvoltage condition exists. the system of this fault. Some of the novel circuit features include a highly ac- The circuit generates a signal that can PCI_AD10. Every PCI device asserts this curate synchronous-detection capability reset the system, or it can generate a sys- signal at least once during PCI enumer- to avoid false alarms arising from large tem-error signal. Because the alarm-reg- ation, but you can monitor other signals

signal overshoots, high impedance and ister memory, IC2B, serves as an asyn- if necessary. This method guarantees low capacitive loading of the bus, auto- chronous register, you can switch the recognition of a 5V PCI device shortly af- matic system shutdown during fault con- alarm off only by removing power from ter the BIOS starts enumerating the PCI

ditions, and a single-cycle response time. the system or by asserting the reset signal. bus during system boot. IC2A then latch- This circuit successfully operates in To avoid false triggering by signal over- es the ’s, IC3, Q-output Pin 1 products using the high-performance shoot and undershoot, a flip-flop-based during the rising edge of the PCI clock.

3.3V MAP-CA processor family from register, IC2A, samples the comparator This action asserts flip-flop IC2B, which Equator Technologies (www.equator. output only during the rising edges of the in turn enables buzzer LS1 and generates com), but you can use it in other high- bus clock. This method allows for a gen- an open-collector, low-active, system-er-

speed 3.3V or even lower voltage systems. erous 33-nsec period at 33 MHz for the ror signal through IC1.You could use this Equator’s latest generation chips are 5V- bus signal to settle down before being error signal to automatically remedy the tolerant, but you can adjust the circuit to sampled. Lowpass filtering by sensor re- fault condition by disabling the offend-

protect other 1.8 and 2.5V chips. The cir- sistors R2,R3 and the 3- to 5-pF parasitic ing circuit on the bus. The sense and ref- cuit uses IC3, an ultrahigh-speed Maxim capacitance on Pin 3 of IC3 limit the max- erence resistors R2,R3,R5, and R6 should (www.maxim-ic.com) MAX999 com- imum clock speed of this circuit. The be metal-film 1% types. The 5V reference

parator with 4.5-nsec propagation delay, traces connecting to Pin 3 of IC3,R2, and voltage connected to R5 determines the TPD, to constantly compare a signal line, R3 thus must be as short as possible and accuracy of the trip voltage, and today’s PCI_AD10 in case of a PCI bus, to a ref- may limit the bus speed to approximate- power regulators have sufficient accura- erence level of 3.8V. This reference volt- ly 40 to 50 MHz. Symmetrically lower- cy so that you can use a 5V system-pow-

age is an optimal compromise between ing the resistance of R2 and R3 increases er line as the reference voltage, obviating 5V signals clamped by 3.3V protection the maximum bus speed to a theoretical the need for a special 5V-reference gen-

diodes and the normal-operation 3.3V 7-nsec cycle time (greater than 140 MHz) erator. Removing jumper JP1 disables the signals. Once the voltage exceeds this ref- at the expense of a higher signal-loading circuit. erence level for an entire bus clock peri- current on the bus. od, the system turns on an alarm buzzer In the case of monitoring a PCI bus, Is this the best Design Idea in this

connected to Q1. Pin 3 of comparator IC3 monitors signal issue? Select at www.edn.com. 102 edn | November 14, 2002 www.edn.com designideas

Use a 555 timer as a switch-mode power supply Aaron Lager, Masterwork , Rohnert Park, CA ost switch-mode power supplies continuous-trigger source. The input IC ,R,R, and V form the feedback cir- ϩ 3 1 2 1 rely on a PWM (pulse-width- must be (1.5VOUT Margin), so for 5V cuit to set the output voltage. The output- modulated) output that is con- output you need 9V minimum input. If voltage equation is V ϭV (R /R ϩ1). M OUT 1 1 2 trolled via voltage feedback. A 555-timer you use CMOS chips and small timing The TL431 is a popular part for setting a

IC can inexpensively perform PWM. The capacitors C1 and C2, you can keep the voltage reference and can easily create the circuit in Figure 1 shows how to turn a operating current low. Thus, you can use 1.25V shown for V1.You can supply 5V at 555 PWM circuit into an switch-mode a simple zener- regulator for the 1.5A with an input of 9 to 40V. At volt- power supply with only one simple equa- 555 and increase the input voltage to ages higher than 12V, you can add a 10V

tion. The design uses two 555s. IC1,in more than 30V.The input-voltage limit is zener-diode supply for the chips. The astable mode, triggers IC2 in PWM mode. a function of how much power the zen- zener supply only slightly reduces the ef- IC1 is set to oscillate at approximately 60 er supply can handle while delivering 5 to ficiency. With 12V input, 5V, 1.5A out- kHz at a high duty cycle. The output is 10 mA to the 555s. put efficiency is approximately 70%, and ␮ low for only approximately 2.5 sec to Q1 has low RDS(ON) and low VGS and can it drops to 65% with a 40V input and a trigger the PWM circuit and then goes handle more than 40V. D1 clamps any zener circuit. The ’s influence high for the rest of the period. The PWM voltage spikes, such as those that occur is more noticeable at lower current levels; circuit has a maximum pulse width of ap- when a large current flow ceases, causing at a 50-mA load the efficiency drops to proximately 85 ␮sec, and it becomes a large magnetic field to be left in the in- approximately 50%.

shorter, depending on the control voltage ductor.You should select D1 according to from the feedback circuit.You can reduce the output voltage you need. For 5V out- Is this the best Design Idea in this the chip count by using a 556 or another put, use a 5.6V zener diode, for example. issue? Select at www.edn.com.

POWER ASTABLE TRIGGER PWM

8 10k VCC 0.1 ␮F 48 4.7k 2 TRIGGER RESET + VCC 7 UNREGULATED 100 4 RESET 3 DISCHARGE SUPPLY IC1 OUTPUT Ϫ 2 6 5 CONTROL 555 TRIGGER THRESHOLD IC 83 2 5 C1 6 THRESHOLD 555 CONTROL 0.01 ␮F 7 3 Figure 1 DISCHARGE OUTPUT GND GND C2 1 ␮ 1 0.001 ␮F 0.01 F

0 POWER

3 Q 7 1 1 2 ZVN4210G/ZTX 3 + V V+ 1 OUT IC 3 6 REGULATED LF411/NS OUT L SUPPLY 1 2 Ϫ VϪ 68 ␮H R1 10k 5 + 1 + V1 1N5817 100 ␮F D 4 1 RLOAD 1.25 1N4734 R2 _ 3.33k FEEDBACK VOUTϭ1.25(1ϩR1/R2). 0 0

Here’s one more use for the ubiquitous 555 timer: a switch-mode power supply.

104 edn | November 14, 2002 www.edn.com

edn021031di3088 Heather designideas VCO uses programmable logic Susanne Nell, Breitenfurt, Austria

VCO (voltage-controlled oscilla- tor) is an analog circuit, so 5V 5V Ayou cannot find it in the li- Figure 1 braries for the design of digital pro- R1 R3 R4 R2 STEERING 6.8k 27k 27k 6.8k J2 grammable chips. When you need such VOLTAGE OUTPUT a circuit for synchronization or clock 1 1 2 multiplication, you need to find a circuit ICST 2 D1 Q 1N4148 3 that works with the standard digital func- D2 Q tions, such as AND and NAND. Several 1N4148 possibilities exist for building variable- F F frequency oscillators. For example, you 1 4 IC1A IC1B can change the frequency using a varac- 74HC02 74HC02 tor diode. Unfortunately, these diodes 2 356 have a small change of frequency per volt. C1 C2 So, the standard Pierce oscillator with 1 nF 1 nF one and capacitors is not useful for these applications. Another idea is to use a Schmitt-trigger inverter and to vary This unique VCO, implemented with discrete logic, has a wide tuning range. the charging resistor. This method can

work, but the hysteresis of the IC usual- NOT NOT ly has a wide tolerance, so the selected in- 1 2 2 1 verter chip has a large influence Figure 2 on the frequency. For these reasons, this design modifies 1 1 1 4 a two-NOR-gate RC oscillator (Figure 1) NOR2 TRISTATE to function as a VCO. For almost all pure- NOR2 TRISTATE BUFFER BUFFER CMOS circuits, the switching point be- 2 2 3 5 6 2 tween high and low states is approxi-

mately VCC/2. This point does not depend PAD5 PAD6 PAD2 on the device. Using this circuit, you can BIDIRECTIONAL OUTPUT BIDIRECTIONAL

obtain a wide frequency-tuning range. 1 Q The output is a with a 50% 1 2 Q duty cycle. At power-on, both capacitors ICST 2 R4 R 1k 4 C1 C2 OUTPUT C and C are uncharged, and IC has a 1k 1 2 1A STEERING 1 nF 1 nF low output. Thus, the output of IC1B is VOLTAGE VST high, and C2 charges with the time con- stant R2C2. The additional charging cur- This VCO uses an EPLD and has high , expressed in kilohertz per volt. rent from ICST and R4 also influences this charging time. When the voltage on C2 reaches VCC/2, IC1B to a low state. VCO’s gain. The circuit uses an Altera grammable-logic devices with CMOS in- Now, the output of IC1A switches high, (www.altera.com) EPLD (erasable pro- puts. You can also use steering voltages and C1 charges with time constant R1C1, grammable-logic device), the EPM3032. much higher then the supply voltage of influenced by ICST and R3. The low sig- Tristate buffers replace the diodes in Fig- the programmable chip, because the volt- nal at the output of IC1B forward-biases ure 1, and the charging resistors connect age on the input of the chip never goes D2 and quickly discharges C2. directly to the steering voltage. This con- higher then VCC/2. This fact makes the This circuit produces a 50% duty cy- figuration produces the highest possible circuit suitable as a voltage-to-frequency ϭ ϭ ϭ cle if C1 C2,R1 R2, and R3 R4. The val- VCO gain: approximately 700 kHz/V for converter with a high input-voltage ues of R4 and R3 and the steering voltage, the component values shown. You can range. VST, determine the VCO’s gain in kilo- switch off the VCO by using a steering hertz per volt. The circuit in Figure 2 voltage lower then VCC/2. You can imple- Is this the best Design Idea in this yields the highest possible value for the ment this circuit using almost all pro- issue? Select at www.edn.com.

106 edn | November 14, 2002 www.edn.com designideas Controlling slew times tames EMI in offline supplies David Canny, Linear Technology Corp, Milpitas, CA

MI from offline switching power that typically suppress this . The ab- pin. Q2,Q3 and their associated circuitry supplies typically causes all sorts of sence of these capacitors allows medical provide undervoltage lockout with hys- Eproblems for power-supply design- devices to easily comply with the more teresis. During start-up, the SHDN pin ers. You may need a large EMI filter to stringent low-leakage-current health- stays low until C5 charges to 12V via R1. meet FCC emission requirements. care specifications of UL544, UL2601, The LT1738 then turns on and subse- Switchers for high efficiency produce and CSA22.2. quently obtains most of its operating

high-frequency switching noise that can Figure 1 shows a 30W (12V output at power from T1’s auxiliary winding. The propagate through the rest of the system 2.5A) offline power supply. IC1,an feedback goes directly to the LT1738’s VC and cause problems. Board layout is crit- LT1738 low-noise switching regulator in pin rather than to the FB pin because the ical, requiring considerable experimen- a flyback topology, drives Q1 and contin- optocoupler provides the feedback gain tation, even for experienced designers. uously controls the current slew using the that the LT1738’s internal feedback am-

The low-noise circuit in Figure 1 signif- resistor at the RCSL pin. The IC controls plifier typically provides. C6 and L1 at- icantly reduces the complexity of these is- the voltage slew using the resistor at the tenuate the low-frequency harmonics of

sues by continuous, closed-loop control RVSL pin and the capacitance at the CAP the LT1738 switching frequency. of the voltage and current slew rates. pin. IC2, an LT1431 programmable ref- You can see the benefits of the circuit High-frequency noise suppression is par- erence, and the optocoupler close the iso- by measuring its ac-line-conducted EMI ticularly important for medical devices lated loop back to the LT1738. The circuit and then comparing these measured re- because they don’t require the ac-line-to- achieves current limit by sensing the cur- sults with those for basically the same cir- earth ground capacitors (“Y” capacitors) rent through a 68-m⍀ resistor at the CS cuit with the LT1738 replaced with a

DANGER: HIGH VOLTAGE P6KE200A L1 C1 + X1 100 ␮F 400V 510 200 pF 1M C BR 90 TO 6 1 2W T 200V 0.1 ␮F 1 1 11 10 264V 250V AC 220 pF AC 1M "X2" D1 K A A1 VOUT 12V X3 37 MUR160 A2 2.5A C C4 10 612 C2 + 3 + + 100k ␮ 330 ␮F R1 330 ␮F 330 F Figure 1 2W 25V 25V BA521 25V 5 8 ϪVOUT 17 19 10 + C5 470 pF 510k ␮ V NC NFB 56 F IN 15 pF 35V 600V 7.5V 14 SHDN IN755A 5 V5 15 pF IC 6 1 2 LT1738 SYNC CAP Q 1 ␮ V 510k MTP2N60E 0.1 F 1k OUT 7 1 C GATE 51k T 1.5 nF 8 4 1k 165k RT CS ISO1 19.6k 16 0.068 Q2 18 CNY17-3 1k RVSL NC 0.5W 38.3k 3.9k 15 20 3 1 3 2 1% 2N2222 R CSL PGND 6 0.22 ␮F 3.9k V+ COMP 8 9 12 5 REF FB VC IC2 4 2 COLL R SS GND GCL LT1431 TOP 2N2222 7 RMIO 10k Q3 13 11 3 ␮ G-F G-S 1% 51k 10 nF 0.1 F 4 65

NOTES: UNLESS OTHERWISE NOTED, D1: MBR20300CT. ALL RESISTORS: 1206,5%. L1: HM18-10001. BR1: GENERAL INSTRUMENTS WO6G. T1: PREMIER MAGNETICS POL-15033. C2, C3, AND C4: SANYO MV-GX.

A 30W offline power supply passes FCC Class B emission requirements without line-to-earth-ground capacitors.

108 edn | November 14, 2002 www.edn.com designideas

generic switcher. The only circuit-pa- rameter difference is that, unlike the LT1738, the generic switcher doesn’t ac- tively control the switching current and voltage slew rates. Figure 2 shows the fre- quency spectra for both circuits. You can see by the respective frequency spectra that the LT1738-based circuit generates emissions well within FCC Class B re- quirements, whereas the circuit with the generic part results in emissions that ex- (a) (b) ceeds FCC Class B allowable emissions by a significant margin. In these 50-MHz-wide spectral plots, areas under horizontal lines indicate acceptable Another benefit of the circuit Figure 2 FCC Class B emission requirements. The spectral plot for the LT1738-based circuit (a) in Figure 1 is that the output voltage shows emissions well within FCC Class B requirements, unlike the plot for the generic switcher (b). noise comprises the fundamental ripple with practically no high-frequency com- the output with little attenuation through in medical devices because the absence of ponents. You can attenuate this ripple the parasitic capacitance of the output fil- Y capacitors results in low leakage current voltage if desired to less than 300 ␮V us- ter’s inductor. The circuit in Figure 1 to earth ground in compliance with ing a 100-␮H, 100-␮F LC filter on the minimizes noise and EMI by controlling health-care specifications. output. The generic switcher, on the oth- the voltage and current slew rates of the er hand, produces more output noise be- external n-channel MOSFET.This circuit Is this the best Design Idea in this cause the high-frequency noise passes to is well-suited for offline power supplies issue? Select at www.edn.com.

110 edn | November 14, 2002 www.edn.com