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Designideas Edited by Bill Travis designideas Edited by Bill Travis DPP adds versatility to VFC Chuck Wojslaw, Catalyst Semiconductor, Sunnyvale, CA he basic VFC (voltage-to-frequen- cy converter) in Figure 1 R2 Tcomprises an integrator Figure 1 (IC1) and a Schmitt-trigger circuit (IC2). VIN The integrator converts the dc input volt- R1 C1 R3 R4 age,VIN, to a linear voltage ramp, and the Schmitt trigger sets the limits of the in- _ + tegrator’s output voltage. Feedback IC1 IC2 VOUT around both circuits provides the condi- + _ INTEGRATOR SCHMITT tion for oscillation. The DPP (digitally TRIGGER programmable potentiometer) in Figure 2 adds programmable limits to the Schmitt trigger and adds two powerful This schematic depicts a basic voltage-to-frequency converter. features to the VFC. First, the scale or conversion factor is programma- Figure 2 D R2<<R1 ble, and, second, for a fixed dc-in- 1 5V put voltage, the converter is a program- 1k, 1% 8 mable oscillator. The frequency, f , of the pR Ϫ 0 3 (1 p)R3 1 single-supply converter in Figure 2 is: VIN CAT5113 R 6 3 1 C1 10k 2 DIGITAL 20k, 1% 0.01 ␮F ()Ϫ ()Ϫ 5 7 CONTROLS ϭ 1 p VIN 2.5V 5V fo fBASE ; 5V p 5V 510 4 2 8 _ 7 2 + 0ϽpϽ0.5, and 2.5VϽV Ͻ5V, IC IN 1 6 IC2 7 LT1097 V1 LM211 V0UT 3 ϭ ␲ + 3 _ where fBASE 1/2 R1C1, and p is the rela- 4 tive position of the wiper from one end 4 (0) of the DPP to the other end (1). For 1 the100-tap Catalyst (www.catsemi.com) 2.5V DPP adds versatility edn021031dix30741 Using a digitally programmable potentiometer, you can vary the scale factor of this voltage-to-fre- to VFC................................................................99 Heather quency converter. Power circuit terminates DDR DRAMs..................................................100 5113 potentiometer, the range of the rate resistors and capacitors. The scale Circuit protects bus scale-factor term (1-p)/p is 1 to 99 with factor relates to the ratiometric temper- from 5V swings ............................................102 a resolution and accuracy of approxi- ature coefficient of the DPP and hence is Use a 555 timer as a mately 1%. For the values shown in Fig- minimally temperature-dependent. You switch-mode power supply........................104 ure 2, the practical range of frequencies can use the circuit as a programmable os- is 500 Hz to 25 kHz. Higher bandwidth, cillator when V is fixed and the poten- VCO uses programmable logic................106 IN rail-to-rail CMOS versions of IC1 and tiometer’s wiper setting changes the lim- Controlling slew times tames IC2, and a greater R1/R2 ratio can extend its of the Schmitt trigger. EMI in offline supplies ................................108 the accuracy and range of the circuit. The Publish your Design Idea in EDN. See the automated, accurate setting ofedn021031dix30742 the scale What’s Up section at www.edn.com. factor saves manufacturing test time andHeatherIs this the best Design Idea in this eliminates the need for expensive, accu- issue? Select at www.edn.com. www.edn.com November 14, 2002 | edn 99 designideas Power circuit terminates DDR DRAMs Ron Young, Maxim Integrated Products, Sunnyvale, CA DR (double-data-rate) SDRAMs put current as high as 6A. IC1 includes a an inverting amplifier. This amplifier find use in high-speed memory sys- step-down controller and two linear-reg- compares VDD/2 (created by R1 and R2) tems in workstations and servers. ulator controllers and operates with in- with V from IC and generates an er- D REF 1 The memory ICs operate with 1.8 or 2.5V put voltages of 4.5 to 28V. ror signal that connects via R3 to IC1’s FB supply voltages and require a reference IC1’s fixed-frequency, 200-kHz PWM pin, thereby forcing VOUT to track VDD/2. voltage equal to half the supply voltage controller maintains the output voltage A 10-mA load, R , is necessary to bias the ϭ 4 (VREF VDD/2). In addition, the logic out- by sourcing and sinking current. Maxi- inverting amplifier for accurate tracking. puts terminate with a resistor to the ter- mum sink current equals the maximum VOUT can track VDD/2 for VDD in the range mination voltage, VTT, which equals and source current, though the sink current 1 to 4V. tracks V .V must source or sink cur- has no current limiting. When sinking REF TT ϭ Ϯ rent while maintaining VTT VREF current, the device returns some current 0.04V. The circuit of Figure 1 provides to the input supply. To implement the the termination voltage for both 1.8 and tracking function, one of IC1’s extra lin- Is this the best Design Idea in this 2.5V memory systems and delivers out- ear-regulator controllers is configured as issue? Select at www.edn.com. Figure 1 5V INPUT 1200 ␮F 4.7 ␮F CMPSH-3 10V 10V MV-AX 22 ␮F (ן10V (4 15 16 VP VL 14 9 BST ILIM ␮ 15k 2 0.1 F COMP 13 FDS6690A EC31 DH QS03L ␮ 4.7 1.5 H DO5022P 22 nF 1000 pF 12 LX 1.25V 6A EC31 11 FDS6690A DL QS03L IC + 1200 ␮F 1 4.7 MAX1864T 10 2.5V GND 5V OS-CON 3 OUT 1OOk R5 4 10k 1 FB POK POK B2 5 R3 5V 10k R FB2 6 7 CMPT 1 ␮F + Ϫ 220 330 pF 3906 10V 1.24V B3 7 22.1k 8 R4 FB3 22 ␮F 100 22.1k 10V R1 1k 2.5V 0.1 ␮F R2 1k This circuit generates the termination voltage for DDR synchronous DRAMs. 100 edn | November 14, 2002 www.edn.com designideas Circuit protects bus from 5V swings Said Jackson, Equator Technologies Inc, Campbell, CA C1 he circuit in Figure 1 auto- 0.01 ␮F matically detects voltage 5V Figure 1 5 3 Tand protects a bus, such VCC GND 2 4 #IC1 + PCI_SERRמ as a 3.3V-limited PCI bus, from 5V NC7SZ125 signal-level swings.You can also use 1 the circuit to determine bus-voltage 5V swings within one bus-cycle for set- 4 10 2 PR 5 12 PR 9 ting appropriate termination volt- DQ DQ IC2A IC2B 5V 3 6 11 8 ages of protection diodes or termi- PCI_CLK CLK Q CLK Q CL CL nation resistors. Today’s deep- R1 1 74LVC74A 13 submicron VLSI-manufacturing PLACE CLOSE 3.3 74LVC74A TO PCI BUS 0603 PCI_RST# 1 5 R techniques sometimes require cir- PCI Q VCC 4 12V 1.5k AD10 R2 0603 R3 0603 2 C2 C LS1 GND IC ␮ + 3 0603 cuits to limit I/O voltages to 3.3V 3 0.1 F 10 ␮F P9948-ND 1 2k 2k 3 4 PANSONIC 0805 0805 מIN+ IN signal swings. Connecting such cir- PCI_AD[31..0] 1% 1% EFB-CB37C11 2 METAL METAL cuits to a bus with 5V level-swing MAX999 C TOP VIEW 5V BUS B Q1 cards could damage the circuitry. 1.88VϮ5% WARNING 5V BUZZER The circuit in Figure 1 can accu- R6 E FMMT4123CT-ND R5 C4 15k 0.1 ␮F 9k SOT-23 rately and—within one bus cycle— 1% METAL 1% METAL 0805 JP1 0603 0603 detect a level swing larger than 3.3V 1 ENABLE on any bus and, upon a fault situa- 2 PROTECTION tion, generate a reset signal and an HEADER2 alarm output to notify the user and This circuit provides both an audible alarm and an error flag when an overvoltage condition exists. the system of this fault. Some of the novel circuit features include a highly ac- The circuit generates a signal that can PCI_AD10. Every PCI device asserts this curate synchronous-detection capability reset the system, or it can generate a sys- signal at least once during PCI enumer- to avoid false alarms arising from large tem-error signal. Because the alarm-reg- ation, but you can monitor other signals signal overshoots, high impedance and ister memory, IC2B, serves as an asyn- if necessary. This method guarantees low capacitive loading of the bus, auto- chronous register, you can switch the recognition of a 5V PCI device shortly af- matic system shutdown during fault con- alarm off only by removing power from ter the BIOS starts enumerating the PCI ditions, and a single-cycle response time. the system or by asserting the reset signal. bus during system boot. IC2A then latch- This circuit successfully operates in To avoid false triggering by signal over- es the comparator’s, IC3, Q-output Pin 1 products using the high-performance shoot and undershoot, a flip-flop-based during the rising edge of the PCI clock. 3.3V MAP-CA processor family from register, IC2A, samples the comparator This action asserts flip-flop IC2B, which Equator Technologies (www.equator. output only during the rising edges of the in turn enables buzzer LS1 and generates com), but you can use it in other high- bus clock. This method allows for a gen- an open-collector, low-active, system-er- speed 3.3V or even lower voltage systems. erous 33-nsec period at 33 MHz for the ror signal through IC1.You could use this Equator’s latest generation chips are 5V- bus signal to settle down before being error signal to automatically remedy the tolerant, but you can adjust the circuit to sampled. Lowpass filtering by sensor re- fault condition by disabling the offend- protect other 1.8 and 2.5V chips. The cir- sistors R2,R3 and the 3- to 5-pF parasitic ing circuit on the bus.
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