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Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits

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Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits Journal of Low Power Electronics and Applications Article Accurate Analysis and Design of Integrated Single Input Schmitt Trigger Circuits Mohamed R. Elmezayen 1,2,* , Wei Hu 1, Amr M. Maghraby 2, Islam T. Abougindia 2 and Suat U. Ay 1 1 Department of Electrical and Computer Engineering, University of Idaho, Moscow, ID 83844, USA; [email protected] (W.H.); [email protected] (S.U.A.) 2 Electronic Engineering Department, Military Technical Collage, Cairo 11838, Egypt; [email protected] (A.M.M.); [email protected] (I.T.A.) * Correspondence: [email protected] Received: 8 June 2020; Accepted: 22 June 2020; Published: 29 June 2020 Abstract: Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 µm/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided. Keywords: schmitt trigger; artificial neural networks; hysteresis circuits 1. Introduction Artificial neural networks (ANNs) are the core of artificial intelligence (AI) in next generation systems that mimic the parallel processing capabilities of the human brain. One important characteristic of the distributed processing element of the brain, the neuron, is to deal with chaos through its hysteretic I/O response [1]. It is shown that this characteristic of a neuron makes ANNs stable [2] and converge more rapidly [3]. Additionally, the artificial neuron has to be small and consume minimal power to be able to be integrated into mass numbers [4]. The Schmitt trigger (ST) has been used in both analog and digital domains to improve the noise immunity of circuits, thanks to its programmable or hard-wired hysteresis characteristics [5–11]. This characteristic has been utilized in many CMOS circuit blocks including oscillators [12–15], input/output pads of integrated circuits [16,17], image sensors [18–24], triangular carrier-based PWM modulators [25], subthreshold SRAMs [26–29], CMOS transceivers [30–34], impedance-to-frequency converters [35], digital to analog converters (DACs) [36], neuron-based analog to digital converters (ADCs) [37–39], powerline communication systems [40], binary logic circuits (i.e., adders [41] and gates [42]), and sensors [43,44]. CMOS STs can be categorized based on their mode of operation (voltage or current), inputs (single or differential input), outputs (inverting or noninverting), and hysteresis controls (fixed or programmable). The simplest and most compact STs are the ones with fixed hysteresis, and single voltage input and J. Low Power Electron. Appl. 2020, 10, 21; doi:10.3390/jlpea10030021 www.mdpi.com/journal/jlpea J. Low Power Electron. Appl. 2020, 10, 21 2 of 20 programmable). The simplest and most compact STs are the ones with fixed hysteresis, and single voltage input and single voltage output types. Six well known single input/single output ST topologies are investigated in this paper: Dokic [5] (three types: N, P, and CMOS), Steyaert [6], Pedroni [7], and Al-Sarawi [8]. In this paper, we show how to derive the hysteresis voltages accurately forJ. Low these Power STs, Electron. and Appl. determine2020, 10, 21their design limitations and sensitivities to process variations. For2 ofthe 20 analysis and design of an ST circuit, three fundamental input-output (I/O) parameters are considered: high-to-low switching voltage (VHL), low-to-high switching voltage (VLH), and hysteresis voltage (ΔVH single voltage output types. Six well known single input/single output ST topologies are investigated = VHL − VLH), as shown in Figure 1. The hysteresis offset (VHO) in Figure 1 can be calculated as (VHO = in this paper: Dokic [5] (three types: N, P, and CMOS), Steyaert [6], Pedroni [7], and Al-Sarawi [8]. VLH + ∆VH/2). In thisDetailed paper, analysis we show and how the to hand derive calculation the hysteresis equations voltages of accuratelyeach topology for theseare presented STs, and determinein Section 2.their Each design topology limitations is extensively and sensitivities simulated to at process different variations. corners Forof the the selected analysis CMOS and design process. of an The ST simulationcircuit, three results fundamental are presented input-output in Section (I/O) 3, parameters as are the arecomparisons considered: between high-to-low hand switchingcalculations voltage and (V ), low-to-high switching voltage (V ), and hysteresis voltage (DV = V V ), as shown in theHL simulation results of each topology, LHin addition to the comparisonsH betweenHL − theLH six topologies. TheFigure conclusion1. The hysteresis is presented o ffset in (SectionVHO) in 4. Figure 1 can be calculated as ( VHO = VLH + DVH/2). FigureFigure 1. 1. I/OI/O characteristics characteristics of of a a voltage voltage mode, mode, inverting inverting ST ST circuit. circuit. Detailed analysis and the hand calculation equations of each topology are presented in Section2. 2. Analysis of Schmitt Trigger (ST) Circuits Each topology is extensively simulated at different corners of the selected CMOS process. The simulation resultsSix are well presented known insingle Section input3, as and are single the comparisons output ST betweentopologies hand and calculations their variants and are the analyzed simulation in thisresults section, of each providing topology, transistor in addition level to theand comparisons more accurate between and intuitive the six topologies. design equations. The conclusion They are is Dokicpresented [5] in(three Section types),4. Steyaert [6], Pedroni [7], and Al-Sarawi [8] STs. We used long-channel MOSFET models and high supply voltage process in this section. Equations (1) and (2) are the quadratic2. Analysis MOSFET of Schmitt transistor Trigger model (ST) Circuits equations that were used for the analysis in saturation (SAT) and linear/triodeSix well known (LIN) single regions, input and respectively single output [45]. ST The topologies threshold and voltage their variants equation are analyzedwas modified in this slightly,section, providinglinearizing transistor bulk-to-source level and voltage more dependency accurate and as intuitive Vthx = V designth0 + ψ∙V equations.SB. Here, ψ They is defined are Dokic as ψ [ 5=] n(three∙GAMMA types),∙PHI Steyaert, where [ 6GAMMA], Pedroni is [ 7the], and back-gate Al-Sarawi effect [8 ]parameter, STs. We used PHI long-channel is the surface MOSFET potential, models and n isand a fitting high parameter supply voltage (0.3 < n process < 0.5) which in this is section.determined Equations through (1)the andsimulation. (2) are the quadratic MOSFET transistor model equations = that( were− used) for the analysis≥ − in saturation () (SAT) and linear/triode(1) (LIN) regions, respectively [45]. The threshold voltage equation was modified slightly, linearizing =(2( − ) − ) for < − (2) bulk-to-source voltage dependency as V = V + V . Here, is defined () as = n GAMMA PHI, thx th0 · SB · · where GAMMA is the back-gate effect parameter, PHI is the surface potential, and n is a fitting parameter (0.3 < n < 0.5) which is determined through1 the simulation. = (3) 2 2 I = β(V VTH) for V V V (1) DS GS − DS ≥ GS − TH (Saturation) 2.1. Dokic Schmitt Trigger Circuits 2 I = β 2(V VTH)V V for V < V V (2) DS GS − DS − DS DS GS − TH (Linear) Dokic proposed three ST topologies in [5]: N-type, P-type, and CMOS-type. These topologies are where investigated and detailed, and more accurate design1 equationsW for VHL, VLH, and ΔVH are derived. β = KP (3) 2 L 2.1.1. N-Type ST by Dokic 2.1. Dokic Schmitt Trigger Circuits Figure 2a shows the N-type Dokic ST [5]. It is composed of four transistors and its hysteresis is shownDokic in Figure proposed 2b. threeDepending ST topologies on how in the [5]: input N-type, signal P-type, changes, and CMOS-type. two I/O characteristics These topologies can arebe investigated and detailed, and more accurate design equations for V , V , and DV are derived. observed. If the input goes from low (0) to high (VDD), the output changesHL LH from high Hto low at VHL. If 2.1.1. N-Type ST by Dokic Figure2a shows the N-type Dokic ST [ 5]. It is composed of four transistors and its hysteresis is shown in Figure2b. Depending on how the input signal changes, two I /O characteristics can be observed. If the input goes from low (0) to high (VDD), the output changes from high to low at VHL. J. Low Power Electron. Appl. 2020, 10, 21 3 of 20 J. Low Power Electron. Appl. 2020, 10, 21 3 of 20 If the input goes from high (V ) to low (0), the output changes from low (0) to high (V ) at V . the input goes from high (VDD) DDto low (0), the output changes from low (0) to high (VDD) atDD VLH. TheLH The V and V can be found when the input and output voltages are equal to each other at operating VHL andHL VLH canLH be found when the input and output voltages are equal to each other at operating pointspoints OP1 OP1 and and OP2, OP2, respectively, respectively, as as marked marked in in Figure Figure 22b.b.
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