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Using a Software-Defined Computer in Teaching the Basics of Computer Architecture and Operation

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Using a Software-Defined Computer in Teaching the Basics of Computer Architecture and Operation Using a software-defined computer in teaching the basics of computer architecture and operation Julia Kosowskaa, Grzegorz Mazur*a aInstitute of Computer Science, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warszawa, Poland ABSTRACT The paper describes the concept and implementation of SDC_One software-defined computer designed for experimental and didactic purposes. Equipped with extensive hardware monitoring mechanisms, the device enables the students to monitor the computer’s operation on bus transfer cycle or instruction cycle basis, providing the practical illustration of basic aspects of computer’s operation. In the paper, we describe the hardware monitoring capabilities of SDC_One and some scenarios of using it in teaching the basics of computer architecture and microprocessor operation. Keywords: software-defined computer, real-time embedded system, microprocessor, bus protocol, instruction cycle, instruction execution 1. INTRODUCTION Our software-defined computer, named SDC_One, was developed as a proof-of-concept and didactic device. It is a complete computer based on a real classic microprocessor chip and implementing all the remaining components of a computer with a contemporary microcontroller, emulating the functionality of processor’s surrounding in firmware. We have treated the SDC_One as an advanced exercise in real-time embedded microcomputer system design, thus we implemented the computer’s logic using a microcontroller rather than an FPGA. The goal was to design a fully functional computer with extensive hardware monitoring capabilities, similar to and exceeding those found in typical microprocessor development systems built in the late 1970s and early 1980s but implemented using a contemporary technology. We insisted on using an old, legacy microprocessor for one important reason: while contemporary microcontroller circuits have very powerful debugging mechanisms, enabling advanced monitoring of device state on instruction basis, it is generally not possible to have any insight into the process of execution of an instruction because of the hardware structures of these circuits and the lack of easily-observable external buses. The primary purpose of SDC_One is the demonstration of processor’s and computer’s operation. With the level of hardware monitoring implemented in SDC_One it is easy to practically demonstrate the phases of instruction execution, stack operations, addressing modes and other aspects of processor’s activity. While all of this may be described with textbooks and pictures or demonstrated using simulation software, we find it very important to show to the students the real operation of real hardware. 2. SDC_ONE HARDWARE SDC_One contains a legacy microprocessor and a contemporary microcontroller with 32-bit ARM Cortex-M core. Four versions of SDC_One have been built, based on four different target microprocessors: the Zilog Z80 CPU1, Motorola MC680082, Intel 80853/OKI 80C85AH4 and WDC65C02S5. All versions use the same base platform – ST Microelectronics STM32L476RGT microcontroller6. The microcontroller implements the functionality of all the integrated circuits found in a classic microcomputer. It generates all the control signals, including the system clock and it implements the memory and peripheral controllers for a target computer. Physically, SDC_One consists of a NUCLEO- L476RG development board made by ST Microelectronics and a small target processor board, containing the CPU, USB mini-B connector, an RGB LED and a few passive components as shown in Figure 1. Such physical design is inexpensive and easily-reproducible; it is possible to place the CPU on a breadboard and connect it to Nucleo board using jumper wires, so students willing to experiment with SDC_One may easily clone the device at their homes. * [email protected]; www.ii.pw.edu.pl Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017, edited by Ryszard S. Romaniuk, Maciej Linczuk, Proc. of SPIE Vol. 10445, 104451O © 2017 SPIE · CCC code: 0277-786X/17/$18 · doi: 10.1117/12.2280769 Proc. of SPIE Vol. 10445 104451O-1 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 08/08/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx se Figure 1. SDC_One with the Zilog Z80 CPU. SDC_One requires only single USB cable for communicating with the PC and supplying power. It is visible to the PC as a complex USB device with one mass storage device and two virtual serial ports used for terminal connection. One of the terminals controls the hardware monitor; the other is used as a target computer console. 3. KNOWN SIMILAR PROJECTS During the implementation of our design, two similar designs were published on the web. They are software-defined computers based on the WDC W65C02S processor with the Parallax Propeller microcontroller emulating some other parts of the computer designed by Jac Goudsmit. The Parallax Propeller is a multicore microcontroller with 8 cores called cogs and 2 KiB of RAM per core. Apart from that, it also has 32 KiB of shared ROM, 32 KiB of shared RAM called hub memory, and 32 I/O lines. Except for some hobby projects, it is not widely used. The first of the aforementioned designs, named Propeddle7, uses a separate SRAM chip connected directly to the target processor, as well as some glue logic chips, such as latches and buffers, to compensate for the low number of I/O lines available in the Propeller. The Propeller microcontroller generates clock and control signals for the 65C02, activates the SRAM chip at the proper times and emulates I/O devices for the target processor. The second design, named L-Star8, is a simplified version of the Propeddle, in which the SRAM and glue logic chips were removed leaving only the 65C02 with its address, data and R/-W lines connected directly to the Propeller. The target processor’s RAM is emulated using Propeller’s 32 KiB hub memory. Since that size of memory may be insufficient for some applications, an extended version called L-Star Plus contains an SRAM chip connected to the 65C02 and controlled by the Propeller much like in the Propeddle. There are 3 main advantages of SDC_One over these designs: • SDC_One is based on a popular, standard microcontroller, not a niche device. • It does not require external memories nor any glue logic. • It provides comprehensive facilities for monitoring and controlling the operation of the target processor. 4. SDC_ONE IMPLEMENTATION The implementation of SDC_One has been in itself an exercise in advanced embedded system design because of tight timing constraints required for the correct implementation of microprocessor’s bus protocol using a microcontroller to perform all the functions of memory, peripheral controllers and glue logic found in a typical microprocessor based computer from the era of 8- and 16-bit microprocessors. A classic processor is connected to the outside world by a bus, which, while physically being a single bunch of wires, is logically divided into three parts: address bus, data bus and control bus. The last part is used to control the process of transferring information on the other two buses. The signals forming the control bus differ depending on the CPU architecture, but they typically include some signals that inform about a data transfer request and its direction. The processors used in SDC_One also have a cycle extension request signal, that is, a CPU input signal originally used to enable interfacing the processor with slower input/output devices and memory chips. The signal is checked after Proc. of SPIE Vol. 10445 104451O-2 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 08/08/2017 Terms of Use: http://spiedigitallibrary.org/ss/termsofuse.aspx initializing a transfer cycle and if it is active, all the control signals remain unchanged. The signal is essential to our design as it allows the microcontroller emulating computer’s environment to make the transfer cycles arbitrary long and finalize them at its own convenience. That both gives the microcontroller ample time to perform more complex actions involved in emulating certain peripherals and enables operating the computer by stepping over individual machine cycles with the cycle being finalized by a monitor command, which is a major feature given the didactic nature of our design. Execution of a single machine cycle involves multiple actions of the CPU: • initiating the transfer by placing the transfer address on the address bus and activating certain control signals that signal data transfer request and identify the type of the cycle, • placing the data on the data bus in write cycles, • checking the state of the bus cycle extension request signal and possibly extending the cycle if requested by a peripheral module, • finalizing the transfer upon detecting inactive state of the cycle extension request signal which involves deactivating the control signals and either latching the data (in read cycles) or closing the data output buffers (in write cycles), The actions required of the microcontroller emulating the CPU’s environment are in direct correlation with the actions of the CPU and involve: • detecting the start of a new transfer cycle, • determining the type of the cycle, transfer address and direction, • performing the data transfer: o in write cycles: latching the data form the data bus, interpreting it and performing additional actions related to peripheral devices if necessary, o in read cycles: fetching the requested piece of data, placing
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