CMOS Schmitt Triggers B.L

CMOS Schmitt triggers B.L. Dokic, Ph.D.

Indexing terms: Metal-oxide-semiconductor structures, Integrated circuits, Circuit theory and design

Abstract: Two variants of CMOS Schmitt triggers, consisting of only four enhancement-type MOS transistors, are proposed in the paper. One consists of three NMOS transistors and one PMOS transistor, while the other consists of one NMOS and three PMOS transistors. A Schmitt trigger with three pairs of CMOS transistors is also described. The hysteresis voltage depends on supply voltage and transistor geometry.

1 Introduction are off, and with Vin = VDD, transistors Tp and Tn2 are also off; hence the consumption in both static states is negligi- A very simple circuit for a CMOS Schmitt trigger, consist- ble, for only leakage currents of the transistors are present. ing of four MOS transistors, has been proposed in Refer- ence 1. Three transistors are of enhancement type and one is of depletion type. For fabrication of the channel of the depletion device, with reference to conventional CMOS technology, a further ion-implantation stage is necessary. On the other hand, the depletion device is conducting in both static states, so consumption exists, as in MOS integrated circuits. Reference 2 describes a CMOS Schmitt trigger which uses a total of eight MOS transistors. New circuits, which are proposed in this paper, also use ou t four MOS transistors; three transistors are of the same type, p or n, and one of the opposite type, n or p. However, all transistors are of enhancement type, and can be imple- mented using conventional CMOS technology. Static consumption is negligible, as in standard CMOS circuits. The Schmitt trigger with three pairs of CMOS transistors will also be described. Referring to circuits with four devices, using the same transistor geometry, the transfer •VDD characteristic is improved and the hysteresis voltage increased. This circuit is the same as the input circuit of the CMOS Schmitt trigger MM54/74C14 [3], which has two additional stages. The second stage is a latch made of two inverters, while the third is an inverter. The latch also has an influence on the hysteresis voltage. So far as the author is aware, there is no detailed analysis of the circuit MM54/74C14 in the literature, except for a very short Fig. 1 Circuit with one PMOS and three NMOS transistors description in Reference 3. It must be pointed out that the bad design of some devices can bring into question the 2.2 Transfer characteristic analysis reliable operation of the circuit, especially when referring to Assume that the input voltage is increasing from zero to the transistors making up the inverter in the latch, whose the supply voltage VDD. Then, the transfer characteristic, output is connected to the output of the first stage. The with reference to the states of individual transistors, can be Schmitt trigger with only six transistors, without a latch as divided into the seven different regions shown in Fig. 2. in the 74C14, is proposed here. The analysis given in this The first region is for 0 ^ Vin ^ VTnl, where VTnl is the paper can also be applied to the circuit 74C14, if the threshold voltage of the transistor T . In this case, T and channel width/length ratio of the inverter transistor, whose nl n Tnl are off and Tp and Tn2 are on, where Tp is non- output is connected to the output of the first stage, is much saturated and T is saturated. The output voltage V = smaller than the same ratio for the other transistors. n2 out VDD and the source voltage of Tn and Tn2 is VSn = VSn2 = V V v> 2 wh Dsm = DD - Tn2 (see Fig- )> ere V'Tn2 is the threshold voltage of T , taking into account the influence of the 2 Schmitt trigger with three NMOS and one PMOS n2 transistor substrate/source voltage. In the second region, Tnl is on and saturated, while the state of the other transistors 2.1 Circuit remains unchanged. VDSnX is decreasing linearly. Through equalisation of the drain currents of T and T (see The Schmitt trigger, consisting of one PMOS and three nl n2 Appendix) in saturation, we obtain NMOS transistors, is shown in Fig. 1. The transfer characteristic has the shape of the hysteresis curve, because of the - V'Tn2 - in - VTnX) (1) effect of transistors Tnl and Tn2. Regenerative feedback is obtained using transistor Tn2 which, during the change of where state, works like a source follower. With input voltage equal to zero, transistors Tn and Tnl vDSnl vTn iWJLnl) Paper 3307G (E10), received 23rd May 1983 The author is with the Elektrotehnicki Fakultet, University 'Djuro Pucar Stari' of Banjaluka, V. Butozana 3, 78.000 Banjaluka, Yukoslavia the geometry ratio of transistors Tnl and Tn2.

IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 197 For VDSnl ^ Vin — VTnl, Tn2 is nonsaturated. Since the is threshold voltage of the transistor Tn is V'Tn > VTnl, due to (3) Pn + Pn and the threshold voltage is determined by eqn. 2, i.e. VTne = V\n. So, in region V of the transfer characteristic, with Tn and Tp in saturation, we obtain

VTp - (4)

Since in this region Vin = Vj, assuming that finl = fin and VTnl = VTn, we find from eqn. 4 that the high threshold is

f YDD ^T (VDD - VTn)

(5) The first term in eqn. 5 is the threshold voltage of the standard CMOS inverter without hysteresis, taking (fiJ2) instead of /?„. For V} < Vin < VDD + VTp (region VI), Tn2 is off, while the others are on, i.e. Tp is saturated and Tn and Tnl are nonsaturated. In region VII, where VDD + VTp < Vin ^ VDD, then Tp and Tn2 are off, Tn and Tnl are on and nonsaturated, and the output voltage Vout = 0. When the input voltage decreases, Tn2 is off until both Tn and Tp are saturated (point C on the transfer characteristic). When the transistor Tn2 starts to conduct, regenerative feedback takes place, and we obtain a much steeper transfer characteristic than with the standard inverter. Owing to Tn2 being off immediately before the regenerative process starts, the low threshold is determined in the same way as the threshold of the standard inverter Fig. 2 Characteristics of circuit in Fig. 1 with two serial NMOS transistors, and is equal to the first a Drain/source voltage of T as a function of input voltage nl term in eqn. 5, namely (i) VDD ~ V'rm

iw.i m m (iv) VDD + VTp Vnn + V, (v) VTml (vi) yTn (6) b Transfer characteristic the influence of the substrate/source voltage, this transistor Therefore, the hysteresis voltage is equal to the second is still off. It starts becoming on when the input voltage term in eqn. 5, that is V'in=V Although for VpSnl + VT DSnl T p ^DSni + V'rn (region III in Fig. 2b) Tnl is nonsaturated, and it can be taken that VDSnl is an approximately linear func- (7) tion of the input voltage, given by eqn. 1, so we have vH = (1 + V Kn VTnl DD (2) 1 +JK Regenerative feedback exists between points A and B, and C and D, on the transfer characteristic (Fig. 2b). taking into account that V'Tn = V'Tn2 when the individual thresholds of Tn and Tn2 are equal. Now all transistors are on, and Tn and Tn2 are saturated while Tp and Tnl are 3 Circuit with three PMOS transistors and one nonsaturated (region IV). In region V, which is reached NMOS transistor when Tp becomes saturated, the state at the output is sud- denly changed. Namely, the regenerative feedback loop is The circuit diagram of the Schmitt trigger with three closed across Tn2, so that the transfer characteristic in that PMOS transitors and one NMOS transistor is shown in part is nearly vertical (VinA = VinB), and the input voltage is Fig. 3. The transfer characteristic has a hysteresis form, equal to the high threshold V j of the Schmitt trigger. The because of Tpl and Tp2. When the input voltage is equal high threshold can be determined from the equation to zero, Tn and Tp2 are off and Tp and Tpl are on, while for obtained through equalisation of the drain currents of Vin = VDD, Tn and Tp2 are on and Tp and Tpl are off. For transistors Tp and Tn in saturation. As Tn2 is off at the end this circuit, the supply current in both static states is negli- of the regenerative process (point B), it will not influence gible. the current of transistor Tn. Transistors Tn and Tnl can be The source/drain voltage VSDp2 of Tp2, as a function of replaced by one equivalent NMOS transistor, whose fl [4] the input voltage, as well as the transfer characteristic, is

198 IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 shown in Fig. 4. For 0 ^ Vin < V j, Tp2 is off and has no threshold voltage of the standard inverter, taking (/?p/2) influence on the high threshold, so that Vj is equal to the instead of j?p, owing to the combination two serial PMOS transistors. If individual thresholds and values of /? for Tp and Tpl are equal, we obtain

(8)

When the input voltage decreases, the transfer characteristic can be divided into seven regions, similar to the case of the increase of input voltage for the circuit in Fig. 1. Only the characteristic regions will be analysed separately. For Vpsp2 +Vj Vppi VDD + VTpl, Tpl is on and saturated while Tp is off. As Tp2 is saturated, VSD2 increases linearly as Vin decreases, and is given by

Tp2 (9) where

VSD2 VD Tpl (Wpl/Lpl) , the geometry ratio of Tpl and Tp2. {Wp2ILpl)

With negligible error, eqn. 9 is valid up to Vin = VSD2 Fig. 3 Schmitt trigger with one NMOS and three PMOS transistors + V'TP> when Tp is turning on. We therefore find that Tp starts turning on at the input voltage given by Vii Vi V.iViii • II i i -•+»- 'DO V'L = (10)

For VT ^ Vin ^ V"n, all transistors are on and the state at the output is changed when Tn and Tp are saturated. In this case, the low threshold is determined in the same way as the high threshold was found for the circuit in Fig. 1. Q (0 PMOS transistors are replaced by an equivalent single transistor, for which the equivalent threshold voltage is

v (11) 1 - vn IIV I 1 il TO? and the constant /? is (/?p/2) when /?pl = fip. Through equalisation of drain currents of Tn and the equivalent 'in lVTPel PMOS transistor, we find that

'DD Vnn + V,Tp (i + M i + .FF

It is assumed that the individual thresholds of Tpl and Tp are equal, i.e. VTpl = VTp. The first term is found to be equal to the high threshold, so that the second term of eqn. J 11 is equal to the hysteresis voltage V + VT nn (13)

VT* V.. There is regenerative feedback between points C, D and A, B on the transfer characteristic (Fig. 4b). Fig. 4 Characteristics of circuit in Fig. 3 Hysteresis of both circuits in Figs. 1 and 3 depends on a Source/drain voltage of Tp2 against input voltage the ratio of the constants (PJPP) of Tn, Tnl, Tp and Tpl, 0) VSD,I=VU+\V'T,\ as (ii) *W = K + I VT,X1 well as on the geometries of Tn2 and Tp2, and not just the b Transfer characteristic supply voltage. It is of note that the hysteresis voltage of

IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 199 the circuits in Figs. 1 and 3 are equal when the ratios When the input voltage decreases to VT < Vin ^ VDD, T are n2 p reciprocal and when Kn is equal to Kp. This is is off and has no influence on the low threshold. This part shown in Fig. 5, for VDD = 15 V. The values of K , in of the transfer characteristic is almost the same as for the

•V DD

'P2

out 5 2 —o I"

0.25 0.5 0.75 1 1.25 1.5 1.75 IT K ( N V 'DD Fig. 5 Hysteresis voltage against geometry ratio 'N1 N2

ForKDD=15V, VTn= \VTp\ = 1.5 V Kn for circuit in Fig. 1, Kp for circuit in Fig. 3 Values of PJP (values in brackets are for Fig. 3): a 8(0.125) b 2(0.5) c 0.5 (2) d 0.125(8)

brackets, and the values of the ratio (/?n//?p) for the hyster- r esis voltage of the circuit in Fig. 3, are marked. So, for NI 10 example, the curve VH =f(Kn) at (PJPP) = 8 for the circuit \N in Fig. 1 is identical to VH =f(Kp) at (PJPP) = 0.125 for the circuit in Fig. 3.

NI 4 Circuit with three pairs of CMOS transistors o ( 4 3 the same geometry of transistors can be obtained if the Q. circuits in Figs. 1 and 3 are combined in one circuit, as shown in Fig. 6. Regenerative feedback, either at a positive or negative output voltage change, is realised through Tn3 L V. and Tp3, so the transfer characteristic is almost ideal. 0 1 | 2 3 ] A 5 6 10 The transfer characteristics for K = 5 V and K = DDnn DDnn V 10 V are shown in Fig. 6b for the integrated circuit of type I NI ^ I input v CD 4007. Certain deviations of the theoretical from the " "HI*1 experimental results are the consequence of taking typical, and not measured, transistor parameters, for example Fig. 6 Schmitt trigger with three pairs of CMOS transistors Kn = | Krp| = 1.5 V and /?„ = /?„, for the calculation. Approximate expressions for drain currents have also been Transistors are type CD4007 a Circuit used (see Appendix), and some effects on transistor par- b Transfer characteristic ameters like the substrate/source and supply voltages have been neglected. (i) V = 10 V For 0 ^ Vin < Vj, when the input voltage increases Tp2 DD (ii) VDD = 5 V is off, so the transfer characteristic in that part is almost theoretical the same as for the circuit in Fig. 1, and consequently the experimental high threshold is also almost the same. The only difference is that here we have two serial PMOS transistors, Tp and circuit in Fig. 3. The low threshold is obtained when Tpl, so instead of the ratio (f}J2($p) in eqn. 5, the ratio (PJPP) is substituted into eqn. 12 for the ratio (2pJPp), fij$p) should be used, for finl = Pn and 0pl = fip. There- which is due to the two serial NMOS transistors. There- fore fore Vnn + V, VI = PJPAVDD-VTn) (i + y^xi + JWP) (14) (15)

200 IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 The hysteresis voltage is given by increases with the increase of the high threshold and decrease of the low threshold. This can be realised by V« = decreasing the constants Kn and Kp (Fig. 7), through an increase in the channel width of transistors Tn2 and Tp2. For a required noise immunity, the total geometry of the (16) transistors will be minimised when Vj = VDD — Kf. This The dependence of the high and low thresholds, as a func- will be satisfied if V} = (VDD/2) + (VH/2) and Vj = (VDD/2) — (VH/2), i.e. the thresholds are symmetrical about tion of the supply voltage and geometry ratios of Tnl and T (/CJ, and T and T (K ), when the geometries of tran- 0.5 VDD, or when fiN = fiNl =fip = fipl and Kn = Kp. The n2 pl p2 p required noise immunity is realised through the corre- sistors Tn, Tnl, Tp and Tpl are such that pnl = ft = fipl = sponding geometry of transistors Tn2 and Tp2. So, for (3p, is shown in Fig. 7. The hysteresis voltage increases example, for Kn = Kp = 0.2, the noise immunity is greater when Kn and Kp decrease. than 75% of VDD, and for Kn = Kp= 1, VnS is smaller than 0.7 VDD. 13

5 Conclusions 12 The required hysteresis is realised through adequate 11 geometries of transistors in the feedback loop, Tn2 and Tp2. When the channels of transistors Tn2 and Tp2 are broader and shorter, the hysteresis voltage is greater. The 10 geometry of transistor Tn2 influences only the high threshold, while the geometry of Tp2 influences only the low threshold of the circuit. The geometries of the other transistors are designed according to the criteria valid for standard CMOS circuits. The transfer characteristic of the circuit with three pairs •o of CMOS transistors is optimal for noise immunity where o 7 the noise immunity can be greater than 70% of the supply voltage. £ 6 The Schmitt circuits and inverters described in this paper can be used as basic circuits for making more * .o complex logic circuits with hysteresis transfer character- •o 5 istics. NAND and NOR Schmitt circuits are formed in a a similar way to standard NAND and NOR logic circuits, by adding two pairs of CMOS transistors to each input.

6 Acknowledgment The author wishes to thank Aleksandar Szabo of Zagreb University for his help in the final manuscript preparation.

7 References

0.2 0A 0.6 0.6 1 1.2 1 NAGARAJ, K., and SATYAM, M.: 'Novel CMOS Schmitt trigger', Electron. Lett., 1981, 17, pp. 693-694 KM and Kp 2 STEINHAGEN, W., and ENGL, L.: 'Design of integrated analog CMOS circuits—a multichannel telemetry transmitter', IEEE J. Solid- State Circuits, 1978, SC-13, pp. 799-805 Fig. 7 Dependence of high and low threshold voltages on Kn and Kf respectively 3 BUURMA, G.: 'CMOS Schmitt trigger: a uniquely versatile design component'. National Semiconductor Report AN-140, 1975 4 DOK.IC, B.L.: 'Influence of series and parallel transistors on DC characteristics of CMOS logic circuits', Microelectron. J., 1982, 13, pp. a high threshold voltage, 25-30 b low threshold voltage, = 5 SCHAMIS, R.S.: 'Reduce system noise with CMOS circuits', Electron. *DD 15 V Des., 1973,25, pp. 112-115 v = io v DD 6 BLANDFORD, D.J.: 'A COS/MOS Schmitt trigger circuit', New Elec- tron. 1975, 8, pp. 50-54 4.2 Noise immunity The noise immunity of the CMOS Schmitt trigger in Fig. 8 Appendix da is very high, typically greater than 50% of the supply voltage, Hysteresis reduces the effect of noise, especially in To a first approximation, the relations for drain currents of systems where a significant amount of noise accompanies n and p-channel MOS transistors may be described by six the required signal [3, 5]. It can tolerate noise on a slow simple equations: input edge without false switching at the output, because n-channel transistor of the hysteresis built into the Schmitt trigger [6]. The DC In the nonsaturation region, i.e. VDSn < VGSn — VTn, then noise immunity Vni of the CMOS Schmitt trigger is given 2 by VDD-Vj) (Fig. 6b). Therefore, Vni IDn = pn[2{VGSn - VTn)VDSn - V DSn] (17)

IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 201 where VGSn is the gate/source voltage, VDSn is the drain/where 2 source voltage and VTn is the threshold voltage. pi = mobility of majority carriers, m /Vs In the saturation region, i.e. VDSn ^ VGSn — VTn e0 = permittivity of free space, As/Vm 8 = relative permittivity of SiO (18) 0X 2 Tn) tox = thickness of oxide layer between gate In the cut-off region, VGSn < VTn, then and channel, m W = channel width, m (19) L = channel length, m. p-channel transistor

In the nonsaturation region, i.e. VSDp < VSGp + VTp, then 2 IDP = PPl2(VSGp + VTp)VSDp - V SDp] (20) where VSGp is the source/gate voltage and VSDp is the source/drain voltage. Branko L. Dokic was born in Vrbica, near In the saturation region, VSDp ^ VSGp + VTp, and Livno, Yugoslavia in 1949. He received the ID = P (VSG +V )2 (21) B.Sc. and M.Sc. degrees in electronic engin- P P P TP eering, both from the Faculty of Electrical In the cut-off region, where VSGp < | VTp \, and where the Engineering, University of Banjaluka, in threshold voltage for the transistor is VTp < 0, then 1971 and 1978, respectively, and the degree of Ph.D. from the Faculty of Technical IDP = 0 (22) Science, University of Novi Sad, Yugo- 2 slavia in 1982. In these equations, /?„ and /3p, measured in A/V , are given by From 1971 to 1979 he was a Research and Teaching Assistant, and since 1979 he has been an Assistant Professor in pulse and digital circuits and n e0 £ox ** n (23) microelectronics at the Faculty of Electrical Engineering, Depart- Pn = f^n t— K7" tox ment of Electronics, University of Banjaluka. Since 1982 he has also been a Research Fellow at the industrial electronics factory b ry "0 ox i (24) 'Rudi Cajavec' Banjaluka. His main research interests are in the tnr L, areas of integrated circuits, and pulse and digital electronics.

Author of Paper 3262G: Jerzy O. Rutkowski was born in England, in December 1946. In 1970 he received the M.Sc. degree in electrical engineering and, in 1978, the Ph.D. degree in technical sci- ences, both from the Silesian Technical University in Gliwice, Poland. He became a research and teaching assistant in 1970, and an assistant professor in 1978, at the Insti- tute of Electronics, Silesian Technical Uni- versity. His teaching and research interests are in circuit theory and design. Present research interests include nonlinear network theory, analysis of large-scale systems and circuits, and automatic analogue fault location.

202 IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984