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CMOS Schmitt Triggers B.L

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CMOS Schmitt Triggers B.L CMOS Schmitt triggers B.L. Dokic, Ph.D. Indexing terms: Metal-oxide-semiconductor structures, Integrated circuits, Circuit theory and design Abstract: Two variants of CMOS Schmitt triggers, consisting of only four enhancement-type MOS transistors, are proposed in the paper. One consists of three NMOS transistors and one PMOS transistor, while the other consists of one NMOS and three PMOS transistors. A Schmitt trigger with three pairs of CMOS transistors is also described. The hysteresis voltage depends on supply voltage and transistor geometry. 1 Introduction are off, and with Vin = VDD, transistors Tp and Tn2 are also off; hence the consumption in both static states is negligi- A very simple circuit for a CMOS Schmitt trigger, consist- ble, for only leakage currents of the transistors are present. ing of four MOS transistors, has been proposed in Refer- ence 1. Three transistors are of enhancement type and one is of depletion type. For fabrication of the channel of the depletion device, with reference to conventional CMOS technology, a further ion-implantation stage is necessary. On the other hand, the depletion device is conducting in both static states, so consumption exists, as in MOS inte- grated circuits. Reference 2 describes a CMOS Schmitt trigger which uses a total of eight MOS transistors. New circuits, which are proposed in this paper, also use ou t four MOS transistors; three transistors are of the same type, p or n, and one of the opposite type, n or p. However, all transistors are of enhancement type, and can be imple- mented using conventional CMOS technology. Static con- sumption is negligible, as in standard CMOS circuits. The Schmitt trigger with three pairs of CMOS tran- sistors will also be described. Referring to circuits with four devices, using the same transistor geometry, the transfer •VDD characteristic is improved and the hysteresis voltage increased. This circuit is the same as the input circuit of the CMOS Schmitt trigger MM54/74C14 [3], which has two additional stages. The second stage is a latch made of two inverters, while the third is an inverter. The latch also has an influence on the hysteresis voltage. So far as the author is aware, there is no detailed analysis of the circuit MM54/74C14 in the literature, except for a very short Fig. 1 Circuit with one PMOS and three NMOS transistors description in Reference 3. It must be pointed out that the bad design of some devices can bring into question the 2.2 Transfer characteristic analysis reliable operation of the circuit, especially when referring to Assume that the input voltage is increasing from zero to the transistors making up the inverter in the latch, whose the supply voltage VDD. Then, the transfer characteristic, output is connected to the output of the first stage. The with reference to the states of individual transistors, can be Schmitt trigger with only six transistors, without a latch as divided into the seven different regions shown in Fig. 2. in the 74C14, is proposed here. The analysis given in this The first region is for 0 ^ Vin ^ VTnl, where VTnl is the paper can also be applied to the circuit 74C14, if the threshold voltage of the transistor T . In this case, T and channel width/length ratio of the inverter transistor, whose nl n Tnl are off and Tp and Tn2 are on, where Tp is non- output is connected to the output of the first stage, is much saturated and T is saturated. The output voltage V = smaller than the same ratio for the other transistors. n2 out VDD and the source voltage of Tn and Tn2 is VSn = VSn2 = V V v> 2 wh Dsm = DD - Tn2 (see Fig- )> ere V'Tn2 is the thresh- old voltage of T , taking into account the influence of the 2 Schmitt trigger with three NMOS and one PMOS n2 transistor substrate/source voltage. In the second region, Tnl is on and saturated, while the state of the other transistors 2.1 Circuit remains unchanged. VDSnX is decreasing linearly. Through equalisation of the drain currents of T and T (see The Schmitt trigger, consisting of one PMOS and three nl n2 Appendix) in saturation, we obtain NMOS transistors, is shown in Fig. 1. The transfer charac- teristic has the shape of the hysteresis curve, because of the - V'Tn2 - in - VTnX) (1) effect of transistors Tnl and Tn2. Regenerative feedback is obtained using transistor Tn2 which, during the change of where state, works like a source follower. With input voltage equal to zero, transistors Tn and Tnl vDSnl vTn iWJLnl) Paper 3307G (E10), received 23rd May 1983 The author is with the Elektrotehnicki Fakultet, University 'Djuro Pucar Stari' of Banjaluka, V. Butozana 3, 78.000 Banjaluka, Yukoslavia the geometry ratio of transistors Tnl and Tn2. IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 197 For VDSnl ^ Vin — VTnl, Tn2 is nonsaturated. Since the is threshold voltage of the transistor Tn is V'Tn > VTnl, due to (3) Pn + Pn and the threshold voltage is determined by eqn. 2, i.e. VTne = V\n. So, in region V of the transfer characteristic, with Tn and Tp in saturation, we obtain VTp - (4) Since in this region Vin = Vj, assuming that finl = fin and VTnl = VTn, we find from eqn. 4 that the high threshold is f YDD ^T (VDD - VTn) (5) The first term in eqn. 5 is the threshold voltage of the stan- dard CMOS inverter without hysteresis, taking (fiJ2) instead of /?„. For V} < Vin < VDD + VTp (region VI), Tn2 is off, while the others are on, i.e. Tp is saturated and Tn and Tnl are nonsaturated. In region VII, where VDD + VTp < Vin ^ VDD, then Tp and Tn2 are off, Tn and Tnl are on and non- saturated, and the output voltage Vout = 0. When the input voltage decreases, Tn2 is off until both Tn and Tp are saturated (point C on the transfer characteristic). When the transistor Tn2 starts to conduct, regenerative feedback takes place, and we obtain a much steeper transfer characteristic than with the standard inverter. Owing to Tn2 being off immediately before the regenerative process starts, the low threshold is determined in the same way as the threshold of the standard inverter Fig. 2 Characteristics of circuit in Fig. 1 with two serial NMOS transistors, and is equal to the first a Drain/source voltage of T as a function of input voltage nl term in eqn. 5, namely (i) VDD ~ V'rm iw.i m m (iv) VDD + VTp Vnn + V, (v) VTml (vi) yTn (6) b Transfer characteristic the influence of the substrate/source voltage, this transistor Therefore, the hysteresis voltage is equal to the second is still off. It starts becoming on when the input voltage term in eqn. 5, that is V'in=V Although for VpSnl + VT DSnl T p ^DSni + V'rn (region III in Fig. 2b) Tnl is nonsaturated, and it can be taken that VDSnl is an approximately linear func- (7) tion of the input voltage, given by eqn. 1, so we have vH = (1 + V Kn VTnl DD (2) 1 +JK Regenerative feedback exists between points A and B, and C and D, on the transfer characteristic (Fig. 2b). taking into account that V'Tn = V'Tn2 when the individual thresholds of Tn and Tn2 are equal. Now all transistors are on, and Tn and Tn2 are saturated while Tp and Tnl are 3 Circuit with three PMOS transistors and one nonsaturated (region IV). In region V, which is reached NMOS transistor when Tp becomes saturated, the state at the output is sud- denly changed. Namely, the regenerative feedback loop is The circuit diagram of the Schmitt trigger with three closed across Tn2, so that the transfer characteristic in that PMOS transitors and one NMOS transistor is shown in part is nearly vertical (VinA = VinB), and the input voltage is Fig. 3. The transfer characteristic has a hysteresis form, equal to the high threshold V j of the Schmitt trigger. The because of Tpl and Tp2. When the input voltage is equal high threshold can be determined from the equation to zero, Tn and Tp2 are off and Tp and Tpl are on, while for obtained through equalisation of the drain currents of Vin = VDD, Tn and Tp2 are on and Tp and Tpl are off. For transistors Tp and Tn in saturation. As Tn2 is off at the end this circuit, the supply current in both static states is negli- of the regenerative process (point B), it will not influence gible. the current of transistor Tn. Transistors Tn and Tnl can be The source/drain voltage VSDp2 of Tp2, as a function of replaced by one equivalent NMOS transistor, whose fl [4] the input voltage, as well as the transfer characteristic, is 198 IEE PROCEEDINGS, Vol. 131, Pt. G, No. 5, OCTOBER 1984 shown in Fig. 4. For 0 ^ Vin < V j, Tp2 is off and has no threshold voltage of the standard inverter, taking (/?p/2) influence on the high threshold, so that Vj is equal to the instead of j?p, owing to the combination two serial PMOS transistors. If individual thresholds and values of /? for Tp and Tpl are equal, we obtain (8) When the input voltage decreases, the transfer character- istic can be divided into seven regions, similar to the case of the increase of input voltage for the circuit in Fig. 1. Only the characteristic regions will be analysed separately. For Vpsp2 +Vj Vppi VDD + VTpl, Tpl is on and satu- rated while Tp is off.
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