A Tandy / RadioShack TRS-80 Model 1 Microcomputer clone.

Built in 2019 using current-production parts.

Glen Kleinschmidt www.glensstuff.com Jan. 2020 Introduction

Having been thoroughly bitten by the old-school 8-bit computing bug and with my Commodore PET 2001 clone ( http://www.glensstuff.com/pet2001/pet2001.htm ) done and dusted, it was time to start investigating potential prospects for the next project.

Released in 1977 (the year I made my own appearance), the TRS-80 Model 1 microcomputer was, for a period of time, one of the best selling, if not the best selling, personal computers for the enthusiast at home. In common with the PET 2001, a CMOS variant of the machine’s original microprocessor, even after all of these intervening years and technological progress, is still in active production and readily available.

Additionally, as per the PET 2001, the machines primitive monochrome video display graphics were generated by means of straightforward TTL logic circuity rather than utilising any kind of propriety or now long-obsolete video graphics-generating integrated circuits or similar. There was one odd-ball chip thrown into the mix though – a single IC manufactured by Motorola designated the MCM6670 and rather grandiosely given the title of a “Character Generator”. This IC, not so much in the way of an actual generator, was in fact just a small mask- programmable ROM housed in an 18-pin plastic DIP. It featured 5-bit words and was presumably chosen by the hardware designer(s) of the TRS-80 for being a cheaper storage medium for the computers character set than something like the MM2716E UV-erasable PROMs that were used for storing the operating system.

Suffice to say, the TRS-80 was the perfect candidate for my next 8-bit retro computer clone project. At this juncture it’s worth mentioning that, just as per my PET 2001 project, this clone is a functional replica of the original computer in the traditional hardware sense. It’s not an FPGA port or an emulator running on a Raspberry Pi and nor is it a part-for-part duplication of the original circuitry, but a complete ground-up re-design using contemporary discrete CMOS logic and memory devices, with some additional features thrown in for good measure. At the time of writing every component used in this project is a current-production part.

74HC(T) CMOS family logic entirely displaces the original LS TTL logic and great simplifications were made by using modern memory devices. The self-contained TRS-80 Model 1 keyboard unit was originally offered with as little as 4 kilobytes of system RAM, but could be expanded to a maximum of 16 kilobytes. The BASIC operating system, however, could recognise an expandable maximum of 48 kilobytes. To get the full 48 kilobytes of system RAM you needed a 16 kilobyte-equipped keyboard unit in addition to either a third- party memory unit or the official Expansion Unit; these being external devices which plug into the keyboard unit’s Expansion Interface port.

The Expansion Unit was an optional accessory which, amongst other things, provided a floppy disk drive controller and a Centronics parallel printer port. The Expansion Unit could also be provisioned with the additional 32 kilobytes of RAM. Note that my clone project detailed here, except for sporting the full 48 kilobytes of system RAM, does not replicate the functions of the Expansion Unit.

A single modern static RAM chip, part # AS6C1008, provides the full 48 kilobytes of system RAM and dispenses with a great deal of address decoding logic. There’s no need for arrays of single-bit-wide dynamic memory chips in this day and age! All of the address multiplexing and refresh logic associated with the original DRAM memory has therefore been conveniently dispensed with.

The circuit simplifications continue on to the systems read-only memory which stores the operating system. A single AT27C256 chip serves as the system ROM and is in fact large enough to contain both the early (“Level I”) and the later, revised and expanded (“Level II”) versions of the BASIC operating system; more about this later.

Back in the day if you wanted sound effects for games (or for any other purpose) you would unplug your data cassette unit and feed the “CASSOUT” signal available at pin 5 of the “Cassette I/O” port to an external audio amplifier. The TRS-80 Model 1 didn’t have any dedicated hardware specifically for producing sound as such, but utilising the data cassette output register bits for this purpose soon became the established method for generating computer game beeps, zaps and primitive tunes.

My clone design incorporates an LM386 audio amplifier with volume control and a source- select function giving the additional handy utility of letting the user listen in on the read and write signals from or to the external data cassette storage device.

I also designed a universal PS/2 keyboard interface, which is accommodated on a separate, self-contained circuit board and is compatible with any TRS-80 Model 1, not just my clone design. Via a length of ribbon cable it plugs into the keyboard interface connector and permits the connection and use of any standard PS/2-protocol keyboard with the computer.

Compete schematic diagrams, bills of material and further technical descriptions follow in this document.

A complete set of Gerber files for the PCBs, ROM image binary files and firmware for the PS/2 keyboard interface are available for downloading on my website: www.glensstuff.com

You can view a Youtube video of my competed TRS-80 Model 1 clone loading and running a version of the computer game Sea Dragon here: https://www.youtube.com/watch?v=LTg4eb-QqK0

Here you can see a video of the computer in the early developmental phase, built and operational entirely on solderless breadboard! The computer at this stage was sporting 16k of RAM, ran BASIC Level I and is shown loading and running RadioShack Flying Saucers: https://www.youtube.com/watch?v=dClOHNcpnVw

The motherboard

The video generator board

The PS/2 keyboard interface board

Hardware Overview

With the exception of some small amount of logic associated with the keyboard, all of the circuitry in the original TRS-80 Model 1 was accommodated on one large PCB. In my clone design I have split the video generation circuitry onto a separate PCB. There are thus two PCBs, designated the “motherboard” and the “video generator board”.

The motherboard contains:

The power supply circuitry, CPU and support circuitry, System RAM & ROM, All peripheral I/O interface circuitry, The audio amplifier and associated circuitry.

Video generator board

The video generator board contains all of the circuity required to generate the TRS-80’s 64 (32 in low-resolution mode) column by 16 row, character-based video display. This includes the screen, or video, display RAM, the character ROM and a 16 MHz master oscillator module from which the 1.7778 MHz CPU/system clock, as well as all video timing signals, are derived. In numerous aspects the circuitry departs from the original design fairly significantly.

Note that in the TRS-80 the video RAM and ROM space is in addition to and separate from the system RAM and ROM space. There are 64 x 16 = 1024 bytes of system-accessible video RAM to define each individual character location. The video ROM simply contains the data defining the TRS-80’s alpha-numeric and graphical character set and is continuously and exclusively accessed by the circuitry concerned with producing the video display. The video character ROM is not hardware accessible to the CPU.

In high-resolution mode, each character location occupies a grid of 6(h) x 12(v) pixels. The complete display is therefore composed of 384(h) x 192(v) pixels. There were some weird design decisions made with the original TRS-80; for example the odd-ball 10.6445 MHz pixel-shifting clock frequency. Perhaps that was a commonly available crystal 40+ years ago, but you certainly can't buy a 10.6445 MHz crystal off the shelf today.

That high frequency meant that all 384 pixels of a complete horizontal row were serially shifted out in just 36 uS of the complete 63.13 uS line period. This means that unless displayed on a TV or monitor having a tweakable (expandable) width control for the horizontal picture size, the result will be a fairly squished up display, horizontally. An additional bother is that 10.6445 MHz is pushing the video bandwidth limitation of your typical TV-based display monitor a bit too far and it was a complaint back in the day that the high-resolution video characters were a bit ill-defined and blurry on screen; even on the re- purposed, modified and re-decaled B&W television set that was originally sold as a dedicated display monitor for the TRS-80. Maybe the Tandy Corporation just had a pre-existing stockpile of 10.6445 MHz crystals to find a use for?

To mitigate these issues and to avoid having to source an unobtanium 10.6445 MHz crystal, in my clone design I've divided the 16 MHz master clock by two to deliver a lowered pixel- shifting clock frequency of 8 MHz. After re-working the divider chains, all 384 horizontal pixels are now shifted out in 48 uS of a complete 64.5 uS line period. This results in a generated video display which fills the screen horizontally. Jumper JP1 on the video generator board permits the field frequency to be set to either a 50 Hz or 60 Hz frame rate, for display compatibility between standards. By virtue of the way the divider chains work out, the selectable frame rates, at 49.69 Hz and 59.73 Hz, aren’t precisely 50 Hz and 60 Hz, but neither were they in the original machine and they are still well within acceptable limits. I have yet to find a modern digital TV (that is those still having a composite video input), let alone any old analogue display monitor which will refuse to sync.

In the original TRS-80 the 10.6445 MHz master clock was divided by 6 to deliver a CPU clock signal for the Z80 microprocessor of 1.7741 MHz. In my clone design I divide the 16 MHz master clock by 9 to deliver a 1.7778 MHz clock for the Z84C microprocessor. 1.7778 MHz is more than close enough to the original frequency so as to not cause any compatibility problems with data cassette baud rates and the like. I guess that I can even boast that my clone design runs a little bit faster than the original item too. Ha!

Lower case modification

The original TRS-80 Model 1, unless modified, was incapable of displaying lower case characters; even so lower case characters were present inside the MCM6670 character ROM chip. This proved to be an issue when it came to applications a little more serious than computer games, such as word processing. In 1978 the Electric Pencil word processor program came with instructions detailing the hardware modifications required to enable the display of lower case letters of the alphabet. RadioShack itself eventually started selling a lower case conversion kit ( catalogue number 26-1104) which was more advanced, coming with a replacement/substitute character ROM chip to overcome some limitations incurred when enabling the display of lower case characters with the original ROM (more on this later).

My clone design implements the lower case modification and the character ROM contains both the original and the upgraded character sets. The “ CASE ” switch on the front panel permits the lower case modification to be either enabled (set to “ LOWER ”) or disabled (set to “UPPER ”). The “ FONT ” switch permits selection of either the “ ORIGINAL ” or the “ UPGRADED ” character set.

To properly understand the ins and outs of the lower case hardware modification a good place to start is by looking at the organisation and contents of the original character set and ROM:

Character locations 0 through 127 are those defined in the originally installed MCM6670 character ROM chip. The 64 characters occupying locations 128 through 191 are the TRS- 80’s “graphics” characters. These characters provide chunky (3 x 4 pixel-size block) pseudo- bitmapping and were originally generated by discrete 74LS logic circuitry independently of the character ROM.

In the original hardware, the weird and not particularly useful hieroglyph-like characters occupying ROM locations 0 through 31, in addition to all of the characters (which includes the lower case letters) defined in locations 96 through 127 were not accessible.

For the 1024 bytes of video RAM, the TRS-80 used and array of 1-bit wide data-I/O static RAM chips addressed in parallel, but there were only seven of them, not the eight required for a full byte! SRAM chips were expensive back in the day and the original hardware designer, counting his beans, simply decided to do without one. With only seven true bits, we can only access 2^7 = 128 unique characters out of the 191 actually defined.

The missing SRAM chip was in the position of bit 6. Note that when bit 7 (128 DEC ) is high we are selecting a graphics character. Bit 7 was therefore defined in the original service manual (under the title “VIDEO RAMS” on page 17) as the “graphical/alphanumeric definition” bit.

It’s worth pointing out at this juncture that in the same paragraph a bit of a turkey-brained and not particularly helpful explanation was given for the derivation and function of bit 6. In lieu of the missing SRAM chip, a pseudo bit 6 was generated by NORing bits 5 and 7 with one gate of a 74LS02.

We’re all good up ‘till this point, but the author then went on to explain that this “is a sneaky way of squeezing a seventh ASCII bit out of six RAMs”. Besides the minor niggle that the TRS-80’s character encoding isn’t entirely compliant with the ASCII standard, the real mischievousness here is in the insinuation that seven true bits of data were miraculously extracted from only six. Such a feat would have profound implications going well beyond the scope of this discussion and we would actually be able to access all 128 characters defined in the character ROM, rather than only a selection of 64, but no, I’m afraid this isn’t the case after all.

To help properly convey how the pseudo bit 6 impacts upon the addressing of the character ROM, I have produced the following table:

D6 Actual Data byte D5 D7 (64 DEC ) character location (32 DEC) (128 DEC) D5-NOR-D7 addressed 0-31 0 0 1 64-95 32-63 1 0 0 32-63 64-95 0 0 1 64-95 96-127 1 0 0 32-63 128-159 0 1 0 128-159 160-191 1 1 0 160-191 192-223 0 1 0 128-159 224-255 1 1 0 160-191

This table shows how the hieroglyph-like characters in ROM locations 0 through 31 in addition to the lower case and other characters in ROM locations 96 through 127 are barred access. Data bytes 0 through 31 don’t access the same locations in the ROM, but map directly to locations 64 through 95 instead. Similarly, data bytes 96 through 127 map directly to ROM locations 32 through 63.

So, if we write a BASIC program to sequentially dump all of the addressable characters to the screen in order, we simply end up getting two complete instances of the 64 characters defined in locations 32 through 95 of the character ROM, rather than the full set of 128 unique characters:

Note that I only dumped to screen characters 0 through 191; 192 through 255 just sequentially repeats the 64 graphics characters. The Electric Pencil lower case modification, mentioned previously, involved some track cutting, wiring and soldering in a substitute for the missing SRAM chip to deliver a true bit 6. This substitute SRAM chip was typically piggybacked on top of one of the existing ones and you had to lift up the data input and the data output pins and wire these into circuit independently. You also had to drill a hole somewhere in your computers plastic case for the mounting of a toggle switch. This toggle switch would be wired to effectively switch the lower case modification in and out of circuit, by selecting between either the true bit 6 now available (provided by the additional SRAM chip) or the original pseudo bit 6.

The reason that this switch to revert the computer to its standard mode of operation was required is made obvious by the following character set screen dump:

This is the exact same BASIC program and screen dump as exhibited in the previous photo, but now the “ CASE ” switch has been flicked to the “ LOWER ” position, enabling the lower case modification. As you can seen, the complete set of 128 unique characters, as defined in the character ROM, are now accessible and have been sequentially dumped to the screen (yay!), but, erm, we appear to have a problem, Houston.

Level II BASIC was originally written with the presumption that data values 0 through 31 will address ROM locations 64 through 95. As a result the BASIC program listing has turned into incomprehensible gobbledygook for anyone who isn’t a savant, as the computer is now printing text to the screen using the hieroglyphs.

When the computer running Level II BASIC wishes to display “C” in a specific location on the screen, it programs the corresponding location in the video RAM with a data value of 3DEC , which was previously redirected to address location 67 of the character ROM; that being the location defining the character “C”. But now, with the lower case modification enabled, data values in the video RAM directly address the same locations in the character ROM, so instead of “C” we actually get the mirror-image “L” that is defined in character ROM location number 3. The cure for this problem is a simple one; when not using the Electric Pencil word processor you can simply switch the lower case modification out of circuit, or you can simply update the character ROM to deliver the correct characters to the screen regardless. The latter was achieved by the updated/replacement character ROM of the RadioShack lower case modification kit mentioned earlier:

In the upgraded character ROM the 32 weird hieroglyph-like characters originally in locations 0 through 31 are deleted and substituted with a copy/repeat of the 32 characters of locations 64 through 95. With this character ROM, when the BASIC operating system calls for the display of character number 3 is gets its “C”, whether the lower case modification is enabled or not.

Now here is a repeat of the character set screen dump, but this time the “ FONT ” switch has been flicked to “ UPGRADED ”, enabling the page of the character ROM programmed with the upgraded character set; as though a genie has waved his magic wand (I’m fairly sure I’ve seen at least one genie wield a magic wand and that mastery of this instrument isn’t solely the purview of fairies), the BASIC listing is transformed back into legibility, even so the lower case modification remains enabled:

Another thing that had been “fixed” with the upgraded character ROM, which you’ve probably noticed already, is that the lower case letters of the alphabet have been revised. They are more aesthetically pleasing now and the letters “g”, “j”, “p”, “q” and “y” have single-line descenders this time ‘round.

The original MCM6670 character ROM chip was mask-programmable. It was sold with either a default, pre-defined character set, or, given some specific minimum order quantity, Motorola could custom-program the device to your personal specification. The latter I guess is obviously how RadioShack procured their upgraded character ROM and maybe their original character ROMs too, as there are a few deviations from the character set graphically defined in the MCM6670’s original datasheet.

There was good reason why the lower case letters of this chip’s default character set had that funky look without the descenders though; it wasn’t just due to the weird artistic bent of some integrated circuit designer. The MCM6670 had 5 bit words and eight such words (or “bytes” incomplete by 3 bits) defined each character. Each character thus occupied a 5(h) x 8(v) pixel grid, but only 7 of the 8 available rows were generally used in practice. The chip was referred to in Motorola literature as a “….5 x 7 Character Generator”.

When defining alphanumeric characters, you had to leave either the topmost or the bottommost row of pixels of all of your defined characters blank to ensure that, between lines of displayed text, there would be at least one pixel of vertical separation. This is why no characters are higher than 7 of the 8 available pixels. To implement descenders on the lower case characters with acceptable legibility, all of the 8 pixels available vertically need to be utilised.

The TRS-80 can get away with using all 8 of those vertical pixels though, and we can have our lower case descenders. This is because the TRS-80’s video hardware unconventionally puts four additional and permanently blank horizontal scan lines under each and every non- graphical character.

The video generation circuitry of my clone design has been simplified significantly over the original circuitry. A single SRAM chip with an 8 bit-wide data bus (U15) serves as the video RAM. NOR gate U16D generates the pseudo bit 6 to emulate the original operation, while quad NAND gate U17 comprises a 2-input multiplexer/data selector which selects between either the pseudo bit 6 or the true bit 6 available directly from the video RAM. When the “lower case” select line is unasserted, it is pulled low by resistor R10. In this state U17 selects and addresses the Character ROM using the pseudo bit 6. When the “ CASE ” switch is closed, by being flicked to the “ LOWER ” position, the “lower case” line is switched high and U17 selects and addresses the Character ROM using the true bit 6; lower case mode is enabled.

To knock about five discrete logic chips out of the design, I did away with the discrete logic circuitry for generating the graphics characters and have instead defined all displayable characters in the character ROM, U20. Address line A12 of U20 is used as a page-select line, under the control of the “ FONT ” switch. The first 4 kilobyte page of U20 contains a replication of the original character set, while the second 4 kilobyte page contains the upgraded character set.

Rock stable composite sync generation and manual control over the raster positioning is provided by a proper pair of monostable ICs (75HC4538), U24 and U25. The original TRS- 80 used a funky arrangement of R-C networks and 74C04 inverters, which proved troublesome over time.

Memory, address decode and BASIC

Referring to page 2 of the motherboard schematic set, U201 is the system ROM. This 32 kilobyte memory contains both versions of the BASIC operating system originally produced for the TRS-80 Model 1.

U201 is programmed with the original “Level I” BASIC in the first 4 kilobytes of the first 16 kilobyte page and the upgraded “Level II” BASIC in the first 12 kilobytes of the other. Page selection is decided by the “BASIC” selector switch which connects to the motherboard via header P202. When the “BASIC” selector switch is open, R204 keeps address pin A14 of U201 low, selecting the lower 16 kilobyte page and thus causing the TRS-80 to run Level I BASIC. Closing the “BASIC” selector switch pulls A14 high and selects Level II BASIC.

All of the computers memory address decoding logic, aside from that for the data cassette I/O register, has been simplified to a ROM look-up table stored in U203. The four separate areas of addressable memory under the direction of U203 are the:

System ROM System RAM Video RAM And the memory-mapped keyboard interface.

The “ R.A.M.” switch on the front panel asserts a page select on the address decoder (U203) and permits the user to select between an addressable system RAM quantity of either 16 or 48 kilobytes.

The BASIC command “ PRINT MEM ” returns the number of “free” system RAM bytes available above that reserved for the functions of the operating system, which, apparently, is 812 bytes for BASIC Level II. In all honesty I’m not too sure how useful this feature will be in practice, but if anyone who might replicate my clone design for themself would like to simulate running out of RAM at the limit that was originally imposed upon the keyboard unit itself, then there you go!

From TTL to CMOS and booting in Level II BASIC

Referring to sheet #2 of the Motherboard schematic (“Memory and Address Decode”), resistor array RP201 provides a passive, TTL-level logic-high pull-up to all data bus lines.

In the original TRS-80, a trio of TTL 74LS367 Hex Bus Drivers, working together as transceivers, buffered the bi-directional 8-bit data port of the Z80 microprocessor to the outside world. In my clone design this function is performed by a single CMOS 74HCT245 Octal Transceiver chip.

Unlike the TTL inputs of 74LS-series logic ICs, the CMOS inputs of 74HC-series ICs do not effectively have internal pull-up resistors by virtue of the structure of their internal architecture; if left unconnected, 74LS-series inputs float high. When any one of the high- impedance inputs of a 74HCT245 is left to float on its own accord, said input will assume an arbitrary voltage level which, for most practical purposes, can be thought to depend upon the phase of the moon as much as anything else.

When the TRS-80 boots running Level II BASIC, one of the first things it does is read the data bus whilst not addressing any of the memory devices or registers contained within the keyboard unit. It does this to check for the presence of that, back in the day coveted, optional external accessory; the Expansion Unit. If the data bus returns any value other than 0x00 or 0xFF the operating system will assume that an Expansion Unit is connected and it will then attempt to talk with the floppy disk controller present in said Expansion Unit.

When the operating system performs this check without an Expansion Unit connected, the data bus is essentially floating as, as already mentioned, no memory devices or registers internal to the keyboard unit are being addressed; simply put, nothing is receiving a request to put data onto the bus. In this state, the 74LS367 chips would reliably present a data bus value of 0xFF to the microprocessor, by virtue of their internal pull-ups which cause all non-driven inputs to float high. The operating system accepts 0xFF as an indication that an expansion unit isn’t connected to the computers Expansion Port and it then proceeds to boot into BASIC.

Here I have detailed for you, dear reader, an unforseen and potential gotcha when it comes to re-designing old TTL computer hardware with CMOS. It was when breadboarding my clone circuitry (yes, I really did build the entire computer on solderless breadboard) that I discovered the above detailed quirk of the boot sequence for Level II BASIC.

My CMOS 74HCT245 transceiver chip, rather than giving a reliable 0xFF, was presenting random byte values to the microprocessor during the test for the Expansion Unit at boot up, causing Level II BASIC to hang practically every time I turned the power on. Failing the 0xFF test, the computer erroneously assumed that an Expansion Unit was connected and it then became stuck in a hopeless loop trying talk with an external floppy disk controller.

Due to good fortune, however, this wasn’t cause to angrily swipe the whole convoluted mess of breadboard from the bench, abandoning all hope and writing off many hours of work and the endeavour of an all-CMOS clone as a pipedream and lost cause. All I had to do was add the passive pull-ups to the data bus lines as I have detailed here in the final design. Phew!

Data cassette interface.

The TRS-80 Model 1 keyboard unit did all of it’s loading and storage of programs and data from and to an external data cassette recorder. This was just a conventional audio cassette recorder which RadioShack re-decaled, rewired and sold as a dedicated peripheral to plug into the 5-pin DIN connector that was the TRS-80’s “Cassette I/O” port.

Given that practically any half decent audio-frequency recording device can be adapted to perform program and data storage for the TRS-80, I wanted a little more flexibility over the cassette interface designed into the original computer for my clone implementation. Different recording devices have different record-input signal sensitivities and output signal levels and drive capability, so I wanted a “cassette” interface which could reasonably accommodate these varied requirements.

The original design was notorious for its unreliability; for example the playback signal level from the cassette recorder was fairly critical and needed to be set to be within a relatively narrow window for reliable operation. The original cassette interface hardware design was based on some sound ideas, but the implementation just wasn’t particularly great.

I wanted none of any of that and at risk of sounding big-headed I will state that my interface circuitry works as flexibly and reliably as anyone could hope for. I have most of my programs and data saved as either MP3 or WAV files, recorded and played back via digital recording devices; namely either a small, portable pocket audio recorder or the desktop PC which resides in my electronics shack.

Programs and data to be loaded into the computer are received via the “ CASSETTE READ IN ” RCA jack on the front panel. This audio input is buffered by voltage-follower U301A and presents a high input impedance of 100k and therefore negligible loading of the source. In the original TRS-80 the signal input was terminated by a 100R resistor. This was done because no form of buffering was employed and an adequately low source impedance was required for predictable operation of the active filter stage that followed. This is all fine and dandy, so long as the playback device has no issue driving a 100 ohm load (which means that it must have a rather low output impedance already); so not overly flexible. The TRS-80 saves data by sending out a stream of pulses which repeat at a fixed interval dependant upon the baud rate (250 baud for Level I BASIC and 500 baud for Level II BASIC). Some of the pulses in this repetitive stream go missing though; each one of these represents a logical zero. The pulses that do not go missing are originally produced as a squarewave-approximation of one cycle of a sinewave; two of the bits of the data cassette output register operate as a crude 3-level DAC in combination with an external resistor network.

The recorded pulses, received from a playback device, are bandpass filtered by the combination of the low-pass filter based on U301B followed by the high-pass filter based on U301C. These are both 2-pole Butterworth filters and the corners frequencies are 7 kHz and 200 Hz respectively.

This 200-7000 Hz bandwidth simultaneously passes the wanted signal without unnecessary distortion whist adequately rejecting extraneous junk. I’ve found that the audio output of my digital playback devices (I’m looking at you, desktop PC) can contain a great deal of high frequency digital noise and interference. A 5m-long audio hook-up lead seems to act as a decent antenna for the emissions of a nasty compact fluorescent lamp too. It only takes one blink/blip of HF interference to poof that 250 baud digital load, which you’ve perceivably been waiting ages and ages for to finish already, into oblivion.

The received pulses are next full-wave rectified and converted to logic-level signals by splicing comparator U303. The splicing threshold/level is automatically maintained at approximately two-thirds of the peak amplitude of the rectified pulses. This means that the pulse detection works reliably and is relatively insensitive to received signal amplitude over a large dynamic range.

So that I’m not flying blind when connecting up and setting the signal level of an external signal source, I utilised the splicing threshold detector to perform the additional function and utility of driving a small (250 uA FSD) analogue panel meter to give an indication of received signal level. It’s handy to have this simple indicator to instantly let you know that both a signal of adequate level is actually being received and that you aren’t grossly overdriving the input.

I’ve reliably loaded programs in both a state of overload and with a signal meter indication of substantially less than one out of ten, but I generally just set for a deflection to around about half scale.

When saving data or programs, the serial data pulse stream to be recorded is sent out of the front panel RCA jack labelled “ CASSETTE WRITE OUT ”. The four-position “ CASSETTE WRITE LEVEL ” switch permits the signal amplitude to be set to one of the four labelled levels; these being 0.2V, 0.5V, 1V or 2V. These are unloaded peak-peak amplitudes and they drop to approximately half with of 600 ohm load.

Whenever the TRS-80 sends data out of the cassette port with the intent that it be recorded, a bit is set in the cassette port output register (integrated circuit U308) to activate the cassette motor relay. The normally-open contacts of this relay are accessible in my clone design via the 2-pin DIN connector on the front panel, logically labelled “ CASSETTE MOTOR ”.

I’ve already mentioned that I mostly use digital recording and storage devices for my programs, where there’s not much in the way of an electric motor to put under the command of the computer, so it might be wondered why I bothered to replicate this level of original functionality. Well, I happen to have an old reel-to-reel tape recorder that I would eventually like to press into data storage service, just for the alluring inconvenience and unpracticality of it all. The red LED on the front panel associated with the “ CASSETTE MOTOR ” DIN connector lights up whenever the cassette motor relay is energized.

Audio line-out and power amplifier

The audio circuitry located on the motherboard is quite simple. Referring to page 4 of the motherboard schematic set, the signal input to the audio power amplifier is under the command of the “ AUDIO SOURCE ” select switch (connecting to header P401), which has the following four positions:

• OFF No audio source is selected and no sounds will emanate from the loudspeaker, even with the volume control turned all the way up.

• S_FX An abbreviation for Sound Effects. This position selects the 2-bit DAC for the cassette port write output (which was universally repurposed by the writers of computer games and hackers alike for sound production) as the signal source. Rather cleverly though, the audio is muted when the register bit that activates the relay which controls the data cassette drive motor is set. This means that you will not hear the screeching sounds of either the incoming or outgoing serial data streams when loading or saving programs or data.

• WRITE Similar to S_FX, but this time the audio is un-muted only when the data cassette motor relay is energised. This means that you will only hear those outgoing serial data streams that are sent when saving programs or data.

• READ The opposite of WRITE; you will hear the serial data streams that are received via the data cassette port whilst loading either programs or data. The serial input data flip- flop, whose reset state is controlled by the microprocessor, is selected as the signal source. This means that you will only hear incoming serial data when the computer itself is listening for it.

A good old LM386 audio power amplifier, U401, is utilised for speaker-driving duties and op-amp U302D serves as a line-level output buffer. The line-level output signal connects to the “ AUDIO OUT ” RCA jack mounted on the front panel of my clone and serves as an output which can handily drive, say, the audio input of a video monitor or an external power amplifier, if desired. In this case the computers own internal amplifier and speaker can be muted by turning the volume control down to zero; the volume control does not affect the line-level output.

Power supply

There’s not much to say about the power supply circuitry. A regulated +5V supply rail is provided for the logic circuitry and a pair of well filtered, though unregulated, supply potentials of approximately +/- 10V are provided for the analogue circuitry of the data cassette interface. The +5V regulator has reserve capacity for powering peripheral devices via the Expansion Port.

A surface-mount, SOT-223 version of the old-school LM7805 linear regulator takes care of the regulated +5V rail, in conjunction with helper transistor Q502, which passes the majority of the load current and dissipates almost all of the regulators wasted power. Q501 serves as a current limiter to protect Q502.

Header P502 serves as an isolation jumper for the +5V rail so that operation of the +5V regulator can be tested and verified without risk of frying the computers logic circuitry. The regulator is short-circuit proof. Operation is checked by ensuring the isolation jumper P502 has not yet been installed, applying power, checking the +5V rail and then shorting the collector of Q502 to ground. If fuse F501 doesn’t blow and the collector of Q502 returns to +5V once the short to ground is removed, then the regulator can be assumed to be functional.

PS/2 keyboard interface

The motherboard of my clone design is compatible with a standard TRS-80 keyboard. It would actually work with an original unit so long as an adaptor cable is soldered up to connect to the 34-pin, double-row boxed header that I’ve used as the keyboard interface connector.

I didn’t think that the best option for my clone build, however, was to try to procure an original keyboard assembly or to try to replicate one in current-production electro-mechanical hardware. The simplest and most practical solution was to design a little adaptor board to interface a standard PS/2 keyboard to the TRS-80. This adaptor board which I have designed is universal in the sense that it can interface a PS/2 keyboard to any TRS-80 Model 1, not just my clone design.

No all of the TRS-80’s original keys copy directly over to the PS/2 keyboard layout. For example, BREAK and CLEAR have been assigned to ESC and HOME respectively. There are a few other differences and on the page following this written description is a graphical keyboard legend (standard US layout) which I have produced as a typing aide. I printed this legend out and laminated it, to serve as a handy lookup and reminder card when typing. The differences are few, however, and easily remembered once you get typing.

VIDEO GENERATOR BOARD U10B 74HC393

13 11 CLKB Q1B

U1 12 9 U2A U3 RSTB Q3B +5V 16MHz +5V +5V +5V 8 74HC74 74HC157 Q4B 7 GND 14 4 14 2 16 VCC S1 VCC A0 VCC 1 3 R1 B0 8 5 4 C28 OUT Q1 Y0 3 5 9 47uF +5V CLK1 A1 7 2 6 6 7 8 16V GND D1 Q1 B1 Y1 10 1.778 MHz 1.778 11 9 U11C A2 Y2 10 74HC08 B2 C29 1 MODE SELECT R4 SEL 470uF 14 15 220R R6 A3 OE 16V P1 13 8 68R B3 GND +5V +5V +5V +5V +5V 2 COMPOSITE 1 VIDEO OUTPUT

Q1 R5 CHAIN 666.66 kHz BC860C 10k C1 C2 C3 C4 C5 U21 100nF 100nF 100nF 100nF 100nF 74HCT165 +5V +5V U22B U6C R1 74HC74 DOT 1 16 74HC08 2k2 SH/LD VCC 2 9 9 11 9 CLK QH CLK2 Q2 U6B 15 8 12 CLK_INH D2 74HC08 10 8 10

SER A B C D E F G H GND 4 10 +5V +5V +5V +5V +5V S2 6 LOAD 13 7 R2 GND 5 +5V 3 4 5 6

11 12 13 14 P2

U5D R2 R3 U22A 1 C6 C7 C8 C9 C10 74HC00 +5V +5V 5k1 1k U4 74HC74 2 100nF 100nF 100nF 100nF 100nF +5V 12 74HC161 11 LOAD 4 14 S1 VCC 2 16 U6A 13 1 CLK VCC R1 9 74HC08 +5V LOAD 7 1 3 ENP CLK1 10 3 SHIFT 2 5 ENT D1 Q1 U5B 2 +5V +5V +5V +5V +5V

3 14 74HC00 28 1 11 12 13 15 16 17 22 20 P0 Q0 4 13 4 9 P1 Q1 5 12 6 8 U20 P2 Q2 6 11 5 10 AT27C256 OE CE IO0 IO1 IO2 IO3 IO4 IO5 P3 Q3 VCC VPP U23A U23B C11 C12 C13 C14 C15 CHARACTER +5V +5V +5V +5V

1 2 74HC74 74HC74 100nF 100nF 100nF 100nF 100nF 8 1 U5C R.O.M. GND RST 74HC00 +5V 3 14 11 9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND CLK1 VCC CLK2 Q2 U5A 2 5 12 R7 R8 D1 Q1 D2 74HC00 9 10 10k 10k Q2 S2

13 9 8 7 6 5 4 3 2 4 10

R2 10 25 24 21 23 26 27 14 S1 S2 8 1 13 7 Q2 R1 R2 GND 11 +5V +5V +5V +5V +5V 3 CLK2 7 12 GND D2

VIDEO SELECT U2B 74HC74 C16 C17 C18 C19 C20

L1 L2 L4 L8 DV0 DV1 DV2 DV3 DV4 DV5 DV6C DV7 100nF 100nF 100nF 100nF 100nF

R9 U18 10k 74HCT244 P3 U7 U12 READ +5V +5V +5V IDC50 74HC393 74HC157 BUFFER +5V +5V +5V +5V +5V 13 14 C1 3 16 1 20 2 1 CLKB VCC B0 VCC ENA VCC 2) CPU CLOCK C2 6 +5V 4 3 B1 4) MODESEL 1 3 C2 C4 10 DV0 2 18 D0 6 5 CLKA Q1A B2 A1 YA1 6) VIDEOSEL 4 C4 C8 13 4 10 28 DV1 4 16 D1 8 7 Q2A B3 Y0 A0 VCC A2 YA2 8) FONTSEL C21 C22 C23 C24 C25 2 7 9 DV2 6 14 D2 10 9 RSTA Y1 A1 A3 YA3 10) LOWER_CASE 100nF 100nF 100nF 100nF 100nF 11 C8 A0 2 9 8 11 DV0 DV3 8 12 D3 D0 12 11 Q1B A0 Y2 A2 IO0 A4 YA4 LSB 12 10 C16 A1 5 12 7 12 DV1 DV4 11 9 D4 D1 14 13 RSTB Q2B A1 Y3 A3 IO1 B1 YB1 9 C32 A2 11 6 13 DV2 DV5 13 7 D5 D2 16 15 Q3B A2 A4 IO2 B2 YB2 7 8 A3 14 5 15 DV3 DV6C 15 5 D6 D3 18 17 GND Q4B A3 A5 IO3 B3 YB3 15 4 16 DV4 DV7 17 3 D7 D4 20 19 OE A6 IO4 B4 YB4 1 2 4 5 1 8 3 17 DV5 D5 22 21 SEL GND A7 IO5 25 18 DV6 19 10 D6 24 23 +5V +5V A8 IO6 ENB GND U8A 24 19 DV7 D7 26 25 A9 IO7 MSB 74HC08 21 DV6C WR 28 27 A10 28) WR C26 C27 23 27 RD 30 29

U13 A11 WE 12 11 30) RD 1uF 1uF U8C U8B +5V 2 A0 32 31

74HC157 A12 11 LSB 16V 16V

74HC08 3 6 74HC08 26 20 A1 34 33 A13 CE U19 9 C16 3 16 1 U16D A2 36 35 B0 VCC A14 74HC244 8 C32 6 14 22 74HCT02 A3 38 37 B1 GND OE WRITE 10 R1 10 U17D +5V A4 40 39 B2 BUFFER R2 13 4 U17A 74HCT00 A5 42 41 B3 Y0 SYNC COMPOSITE 7 U15 74HCT00 20 1 A6 44 43 Y1 VCC ENA A4 2 9 AS7C256 13 1 A7 46 45 U9A A0 Y2 +5V A5 5 12 VIDEO 3 12 13 DV0 18 2 D0 A8 48 47 74HC393 A1 Y3 YA1 A1 A6 11 MEMORY 2 DV1 16 4 D1 A9 50 49 A2 YA2 A2 MSB 14 3 L1 A7 14 DV2 14 6 D2

VCC Q1A A3 6 YA3 A3 4 L2 15 DV3 12 8 D3 Q2A OE YA4 A4 1 5 L4 1 8 DV4 9 11 D4 CLKA Q3A SEL GND YB1 B1 6 L8 DV5 7 13 D5 Q4A YB2 B2 2 U17B DV6 5 15 D6 RSTA YB3 B3 74HCT00 DV7 3 17 D7 YB4 B4 U14 +5V +5V 10 19 74HC157 5 4 GND ENB 12 U17C U11D 11 R4 3 16 74HCT00 74HC08 B0 VCC 13 R8 6 9 12 B1 U8D 10 8 11 B2 74HC08 13 4 10 13 B3 Y0 7 Y1 A8 2 9 WRITE_RAM U9B A0 Y2 A9 5 12 READ_RAM U16A 74HC393 A1 Y3 WR 11 74HCT02 A2 13 11 R1 RD 14 LOWER CASE 2 CLKB Q1B A3 10 R2 15 1 Q2B OE 12 9 R4 1 8 3 RSTB Q3B SEL GND 8 R8 R10 Q4B 7 10k GND * = NPO/COG U16C 1 74HCT02 2 8 3 COMPOSITE BLANKING V_SYNC 12 10 11 9 U10A +5V JP1 - FIELD 13 74HC393 1-2 = 60 Hz RV1 RV3 C30*C31 *C32 *C33 * 1 14 2-3 = 50 Hz R12 100k +5V R13 RV2 +5V R14 5k +5V R15 RV4 +5V U6D

CLKA VCC 4 100nF 10nF 1nF 1nF 10k LIN.47k 50k 3k3 LIN. 3k3 5k 74HC08 2 3 VDRV RSTA Q1A

1 2 U16B 1 2 15 14 1 2 15 14 74HCT02 U11A ADJUST SET ADJUST SET 74HC08 +5V RASTER+5V VERTICAL +5V RASTER +5V HORIZONTAL 5 6 GND GND GND GND C1R1 VERTICAL C2R2 SYNC PULSE C1R1 HORIZONTAL C2R2 SYNC PULSE H_SYNC U11B 16 POSITION WIDTH 16 POSITION WIDTH +5V +5V +5V +5V +5V +5V VCC VCC 74HC08 3 13 9 3 13 9 3 RST1 RST2 Q2 RST1 RST2 Q2 4 R11 5 11 5 11 14 14 14 14 14 14 B1 B2 B1 B2 6 10k 4 7 12 8 4 7 12 8 A1 Q1 A2 GND A1 Q1 A2 GND 5 U5E U6E U8E U11E U16E U17E + + + + + + 74HC00 74HC08 74HC08 74HC08 74HCT02 74HCT00

U24A U24B U25A U25B G G G G G G 74HC4538 74HC4538 74HC4538 74HC4538

HRDV 7 7 7 7 7 7

Sheet_1 Sheet_2 Sheet_5 1) CPU.Sch 2) Memory and address decode.Sch 5) Power.Sch

SYSTEM ADDRESS BUS A[0..15] A[0..15] SYSTEM DATA BUS DATA[0..7] DATA[0..7]

1.778 MHz SYSTEM_CLOCK SYSTEM_CLOCK

RAS RAS

RD RD

WR WR

LOW_RES

Sheet_3 Sheet_4 3) Cassette interface.Sch 4) Sound.Sch

LOW_RES MOTOR MOTOR

A[0..7] A[0..7] MOTOR MOTOR

DATA[0..3] DATA[0..3] CASS_READ CASS_READ

DATA[6..7] DATA[6..7] CASS_WRITE CASS_WRITE

OUT OUT

IN IN 1) CPU

SYSTEM_CLOCK 2 TEST WAIT INT TEST +5V +5V U102D 74HCT32 11 27 12 VDD M1 R102 11 P101 R101 4k7 +5V R108 13

RESET 13 100R 4k7 10 25 1 BUSRQ U103F 2 U105A R109 21 1 74HCT04 RD 74HCT32 D101 U103E 4k7 3 LL4148 74HCT04 24 22 2 WAIT WR

U105B 12 R110 19 +5V +5V +5V

11 MREQ 74HCT32 4k7 4 U109 16 20 6 INT IORQ 74HC244 5 R111 R112 1 20 4k7 4k7 U105C ENA VCC 74HCT32 9 2 18 SYSRES A1 YA1 8 4 16 INTAK A2 YA2 U103A 10 6 14 A3 YA3 RAS 2 74HCT04 8 12 U105D A4 YA4 11 9 74HCT32 B1 YB1 RD 2 1 2 6 12 13 7 CLK B2 YB2 11 15 5 B3 YB3 WR 2 13 17 B4 R107 OUT 3 4k7 19 10 ENB GND U103B U106 IN 3 74HCT04 +5V 74HCT245

4 3 18 14 2 20 HALT D0 A1 VCC 15 3 D1 A2 12 4 1 D2 A3 DIR 8 5 D3 A4 U102A U103C 7 6 18 DATA0 D4 A5 B1 74HCT32 74HCT04 9 7 17 DATA1 U101A D5 A6 B2 +5V 1 10 8 16 DATA2 TLC556 D6 A7 B3 3 5 6 17 13 9 15 DATA3 NMI D7 A8 B4 14 5 2 14 DATA4 P102 VDD 1OUT B5 19 13 DATA5 EXPANSION OE B6 R103 R104 4 12 DATA6 INTERFACE 1RESET B7 1M 1M 10 11 DATA7 GND B8 2 3 +5V +5V 1THRES 1CONT U102B 1 74HCT32 1 2 1DISCH 4 3 4 TEST 6 6 5 6 SYSRES 1TRIG U107 5 +5V 7 8 WAIT 74HCT244 9 10 INT C111 C112 C113 1 20 11 12 INTAK ENA VCC 100nF 100nF 100nF 13 14 RAS 30 2 18 A0 15 16 IN A0 A1 YA1 31 4 16 A1 17 18 OUT A1 A2 YA2 32 6 14 A2 19 20 WR A2 A3 YA3 33 8 12 A3 21 22 RD A3 A4 YA4 U103D 34 11 9 A4 23 24 U101B A4 B1 YB1 +5V 74HCT04 35 13 7 A5 DATA0 25 26 DATA1 TLC556 A5 B2 YB2 36 15 5 A6 DATA2 27 28 DATA3 A6 B3 YB3 10 9 9 8 26 37 17 3 A7 DATA4 29 30 DATA5 2RESET 2OUT RESET A7 B4 YB4 DATA6 31 32 DATA7 R105 R106 19 10 33 34 ENB GND 1M 1M A0 35 36 A1 12 11 A2 37 38 A3 2THRES 2CONT A4 39 40 A5 13 C116 A6 41 42 A7 2DISCH 100nF A8 43 44 A9 U108 8 7 +5V A10 45 46 A11 2TRIG GND 74HCT244 A1247 48 A13 C115 1 20 A1449 50 A15 ENA VCC C114 1uF DATA[0..3] DATA[0..3] 3 100nF 16V 38 2 18 A8 A8 A1 YA1 TANT 39 4 16 A9 A9 A2 YA2 40 6 14 A10 A10 A3 YA3 1 8 12 A11 DATA[6..7] A11 A4 YA4 DATA[6..7] 3 2 11 9 A12 A12 B1 YB1 3 13 7 A13 A13 B2 YB2 4 15 5 A14 A14 B3 YB3 29 5 17 3 A15 DATA[0..7] GND A15 B4 YB4 DATA[0..7] 2

19 10 ENB GND U104 Z84C0006PEG A[0..7] A[0..7] 3 C.P.U.

A[0..15] A[0..15] 2

+5V +5V +5V 14 14 14

+5V +5V +5V +5V +5V +5V +5V +5V +5V +5V

+ U102E + U103G + U105E C110

G 74HCT32 G 74HCT04 G 74HCT32 1uF 16V C101 C102 C103 C104 C105 C106 C107 C108 C109

TANT 7 7 7 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 2) MEMORY AND ADDRESS DECODE

1 SYSTEM_CLOCK

3 LOW_RES

DATA[0..7] 1 DATA[0..7]

A[0..15] 1 A[0..15]

U201 U202 AT27C256 AS6C1008 SYSTEM R.O.M.+5V +TTL SYSTEM R.A.M. +5V

A0 10 28 1 16 DATA0 A0 12 32 A0 VCC A0 VCC A1 9 2 15 DATA1 A1 11 30 A1 A1 CE2 A2 8 1 3 14 DATA2 A2 10 A2 VPP A2 A3 7 4 13 DATA3 A3 9 13 DATA0 A3 A3 DQ0 +5V A4 6 11 DATA0 5 12 DATA4 A4 8 14 DATA1 A4 IO0 A4 DQ1 A5 5 12 DATA1 6 11 DATA5 A5 7 15 DATA2 P203 A5 IO1 A5 DQ2 P201 A6 4 13 DATA2 7 10 DATA6 A6 6 17 DATA3 IDC50 A6 IO2 A6 DQ3 CHAR. SET R201 A7 3 15 DATA3 8 9 DATA7 A7 5 18 DATA4 VIDEO A7 IO3 A7 DQ4 & CASE 560R A8 25 16 DATA4 A8 27 19 DATA5 GENERATOR A8 IO4 A8 DQ5 A9 24 17 DATA5 A9 26 20 DATA6 A9 IO5 A9 DQ6 A10 21 18 DATA6 RP201 A10 23 21 DATA7 2 1 1 A10 IO6 A10 DQ7 2) CPU CLOCK CHAR. SET 1/2 A11 23 19 DATA7 4816P-1-332LF A11 25 4 3 2 A11 IO7 A11 4) MODESEL A12 2 A12 4 29 6 5 3 A12 A12 WE 6) VIDEOSEL LOWER/UPPER A13 26 22 A13 28 24 8 7 4 A13 OE A13 OE 8) FONTSEL 27 A14 3 22 10 9 A14 A14 CE 10) LOWER_CASE 14 20 A15 31 DATA0 12 11 GND CE A15 LSB 2 16 DATA1 14 13 A16 VSS DATA2 16 15 +5V DATA3 18 17 DATA4 20 19 DATA P202 DATA5 22 21 O/S SELECT R202 DATA6 24 23 & MEM. SIZE 560R DATA7 26 25 MSB 28 27 28) WR 30 29 1 30) RD BASIC LEVEL 1/2 A0 32 31 2 LSB A1 34 33 3 16k/48k U203 A2 36 35 4 AT27C256 A3 38 37 ADDRESS +5V +5V A4 40 39 DECODER A5 42 41 ADDRESS

8 A6 44 43 A10 10 28 A7 46 45 A0 VCC A11 9 R205 R206 R207 R208 A8 48 47 A1 A12 8 1 10k 10k 10k 10k A9 50 49 A2 VPP MSB A13 7 A3 A14 6 11 A4 IO0 A15 5 12 U102C A5 IO1 9 4 13 10 74HCT32 P204 1 RAS A6 IO2 3 15 IDC34 A7 IO3 25 KEYBOARD +5V A8 24 A9 21 1 2 A10 23 A0 3 4 A11 R203 R204 2 A1 5 6 A12 10k 10k 26 22 A2 7 8 A13 OE 27 BASIC LEVEL 1 OCCUPIES A3 9 10 A14 14 20 FIRST 4kB OF FIRST 16kB A4 11 12 GND CE PAGE OF R.O.M. U201 A5 13 14 A6 15 16 BASIC LEVEL 2 OCCUPIES A7 17 18 FIRST 12kB OF SECOND 16kB DATA0 19 20 PAGE OF R.O.M. U201 DATA1 21 22 DATA2 23 24 DATA3 25 26 DATA4 27 28 DATA5 29 30 DATA6 31 32 DATA7 33 34 1 RD

1 WR

Q201 +5V BC850C +TTL

+5V +5V +5V +5V +5V +5V R209 330R P205 VIDEO BOARD C206 C207 C208 R210 +5V POWER 1uF 1uF 1uF 330R 16V 16V 16V D201 1 + C201 C202 C203 TANT TANT BZX84C3V6 TANT 2 - 100nF 100nF 100nF 3) CASSETTE INTERFACE P301 CASSETTE I/O

1 CASS_READ_SIGNAL 2 CASS_READ_GND C303* C308 3 CASS_WRITE_SIGNAL +ANALOG R305 R309 R311 3n3 10nF 4 CASS_WRITE_GND 7k5 20k 30k +ANALOG +5V 5 CASS_MOTOR_SW1 6 CASS_MOTOR_SW2 C301* 100nF R307 5 U303 R318 4 9 10k +ANALOG TS391SN2T1G 4k7 U304A 6 8 3 74HC132 R301 2 7 10 1 1

D302 4 10k 1 5 R308 R310 R312 4 3 BAT54S 3 10k 10k 10k 2 C305*C306 * R303 R304 2 1 2 100nF 47nF

7k5 15k C304* U301B R306 U301C 1 2 R302 C302 U301A 1n5 TL074 18k TL074 3 11

100k 100pF TL074 7 kHz 200 Hz 13 3 -ANALOG CASS READ LOW-PASS HIGH-PASS 14 U302A BUFFER FILTER FILTER 12 TL074 4 11 6 5 D303 C309 U301D -ANALOG R317 BAT54 100pF +ANALOG TL074 100k U304B FULL-WAVE 74HC132 2 RECTIFIER R313 D301 * = NPO/COG 220R R315 3 BAT54S 5 10k 7 C307* 6 100nF

1 R314 R316 4M7 U302B 20k -ANALOG TL074 RV301 20k R319 P302 U306A 10k 74HC32 250uA FSD 1 1 SIGNAL 1 OUT 2 3 METER 2 1 IN

U306B U307 U308 RLY301 *FF 74HC32 74HC244 +5V +5V 74HC175 R320 +5V DS1E-S-DC5V A[0..7] 5 10k 1 A[0..7] 6 1 20 16 2

ENA VCC VCC 1Q 1 12 4 A0 1 2 18 DATA7 1 R321 A1 YA1 CLR A1 2 4 16 DATA6 10k A2 YA2 A2 3 6 9 6 D304 D305 A3 CLK 2Q A3 4 8 LL4148 SMAJ30CA A4 8 11 DATA0 4 B1 1D A4 5 13 DATA1 5 10 B2 2D 3Q A5 6 15 DATA2 12 B3 3D 6 7 A6 11 U305A +5V 17 DATA3 13 11 B4 4D 3Q A7 12 74HC30 CASSETTE PORT 19 10 8 14 ENB GND GND 4Q ADDRESS DECODE Q301 BC850C R322 DATA[6..7] 1k 1 DATA[6..7]

DATA[0..3] 1 DATA[0..3]

2 LOW_RES

P303 CASS_MOTOR R323 L.E.D. 4 MOTOR 300R

4 MOTOR 1 A 2 K 4 CASS_READ

4 CASS_WRITE

R334 +5V 10k R335 +ANALOG +ANALOG +ANALOG 10k R325 C311 1k R326 9 100nF C312 C314 C316 30k 8 100nF 100nF 100nF 10 R336 560R R327 R329 R331 R333 U302C Q302 30k 10k 3k3 1M TL074 C313 C315 BC860C Q303 Q304 Q305 100nF 100nF BC850C BC850C BC850C R324 C310 3k6 1nF -ANALOG -ANALOG P304 CASSETTE +5V +5V +5V WRITE +5V +5V +5V +5V +5V LEVEL 14 14 14 +5V R337 SWITCH R328 R330 R332 10k U304E U305B U306E 10k 10k 10k + + + 1 COM. 74HC132 74HC30 74HC32

G G G 2 200mV 3 500mV C317 C318 C319 C320 C321 4 1V

100nF 100nF 100nF 100nF 100nF 7 7 7 2V = OPEN 4) SOUND

R409 R410 R411 C401 10k 10k 10k 1nF 12 3 CASS_WRITE 14 13

P402 C402 U302D AUDIO 10uF +5V R405 TL074 R414 OUTPUT R402 16V 10k 560R 10k 1 LINE (1Vp-p) 2 3 R401 R403 SPEAKER (8R) 4 10k 10k U306C R407 R408 74HC32 U304C 10k 10k 9 74HC132 R406 8 9 10k P403 10 8 R412 VOLUME 3 MOTOR 10 150k CONTROL

Q402 Q403 Q404 BC850C BC850C BC850C 1 U306D 2 74HC32 3 12 4 11 13 3 MOTOR

+UNREG Q405 +5V FZT1049A C403 10uF 16V R404 R413 R415 10k U304D 39k 560R 74HC132 C404 12 100nF 3 CASS_READ 11 13 D401 BZX84C6V8

Q401 BC850C R416 10k 6 U401 LM386 P401 3 AUDIO 5 SOURCE 2 SELECT R417 R418 C407 SWITCH 2k7 100R 470uF OFF = OPEN 4 7 16V SOUND_FX 1 C405 C406 CASS_WRITE 2 10uF 10nF CASS_READ 3 16V COM. 4 5) POWER

+UNREG

R502 Q502 1R 1W MJ2955 P502 ISO JMPR P501

Q501 1 2 9VAC 1 B501 F501 BC860C REG501 C.T. 2 R503 WO4 1A R504 LM7805MP C.T. 3 220R 2R2 9VAC 4 ~ 1 3 IN OUT +5V 2 TAB ~ COM COM R501 C501 10R C502 C503 R505 4700uF 470nF 100nF 330R 25V

P503 POWER-ON L.E.D.

B502 D501 1 A WO4 BAT54S 2 K ~ 2 1

~ Q503 FZT1049A 3

+ANALOG C504 R506 470uF 330R 16V C508 10uF C506 16V R507 47uF 3k3 16V

C507 R508 47uF 3k3 16V C509 10uF C505 16V R509 470uF 330R 16V -ANALOG

Q504 3 FZT1149A 1 2

D502 BAT54S

TANDY TRS-80 CLONE PS/2 KEYBOARD INTERFACE

P2 ICSP +5V +3V3 +5V +5V U1 U2 PIC16F876 EPM7064AETC44 P4 4 3 2 1 SERIAL MATRIX R7 IDC34 R3 COMMUNICATOR ENCODER 10k KEYBOARD 4k7 20 17 38 KYBD KYBD 1 2 VDD VCCINT KYBD 41 A0 3 4 VCCINT +5V +5V +5V 1 9 8 A0 A1 5 6 MCLR VCCIO A0 28 29 43 A1 A2 7 8 PGD VCCIO A1 27 39 A2 A3 9 10 PGC A2 11 20 10 A3 A4 11 12 RC0 D0 A3 P1 R1 R2 12 33 14 A4 A5 13 14 RC1 D1 A4 PS/2 4k7 4k7 13 42 13 A5 A6 15 16 RC2 D2 A5 14 23 31 A6 A7 17 18 RC3 D3 A6 15 40 21 A7 D0 19 20 +5V VCC (5) 1 RC4 D4 A7 2 16 37 D1 21 22 KBD_CLOCK (1) 2 RA0 RC5 D5 3 17 28 34 D0 D2 23 24 KBD_DATA (3) 3 RA1 RC6 D6 DATA0 18 22 19 D1 D3 25 26 GND (2) 4 RC7 D7 DATA1 11 D2 D4 27 28 DATA2 21 12 15 D3 D5 29 30 RB0 STRB0 DATA3 22 44 18 D4 D6 31 32 RB1 STRB1 DATA4 23 30 27 D5 D7 33 34 RB2 STRB2 DATA5 () = PIN NUMBERING 24 25 6 D6 RB3 STRB3 DATA6 FOR 6-PIN MINATURE 25 5 2 D7 RB4 STRB4 DATA7 D.I.N. CONNECTOR 26 3 RB5 STRB5 9 7 35 CLKI RA5 STRB6

1 4 TDI GND EPM7064 INPUTS ARE 5V TOLERANT REGARDLESS OF VCCIO R4 7 16 TMS GND EPM7064 OUTPUTS ARE TTL-LEVEL COMPATIBLE WITH VCCIO = 3V3 8 1k 32 24 VSS TDO GND 19 26 36 VSS TCK GND

U3 P3 REG1 +5V +5V +3V3 +3V3 +3V3 +3V3 10MHz +5V +3V3 JTAG +3V3 +3V3 TC1262-3V3

8 R5 1 2 3 1 VCC OUT IN 10k 3 4 TAB 2 COM COM 5 5 OUT C2 C1 10uF 47uF C3 C4 C5 C6 C7 C8 4 9 10 GND TANT 16V 100nF 100nF 100nF 100nF 100nF 100nF R6 10k

Parts for Motherboard PCB

Designator Component type Value Part # Manufacturer Package Description Quantity

R502 Resistor 1R 1W Various 2512 Chip, thin film 1 R504 Resistor 2R2 Various 1206 Chip, thin film 1 R501 Resistor 10R Various 1206 Chip, thin film 1 R101, R418 Resistor 100R Various 1206 Chip, thin film 2 R313, R503 Resistor 220R Various 1206 Chip, thin film 2 R323 Resistor 300R Various 1206 Chip, thin film 1 R209, R210, R505, R506, Resistor 330R Various 1206 Chip, thin film 5 R509 R201, R202, R336, R414, Resistor 560R Various 1206 Chip, thin film 5 R415 R322, R325 Resistor 1k Various 1206 Chip, thin film 2 R417 Resistor 2k7 Various 1206 Chip, thin film 1 R507, R508, R331 Resistor 3k3 Various 1206 Chip, thin film 3 RP201 Resistor array 3k3 x 8 4816P-1-332LF Bournes 16 pin SMT 1 R324 Resistor 3k6 Various 1206 Chip, thin film 1 R102, R107, R108, R109, Resistor 4k7 Various 1206 Chip, thin film 8 R110, R111, R112, R318 R303, R305 Resistor 7k5 Various 1206 Chip, thin film 2 R203, R204, R205, R206, Resistor 10k Various 1206 Chip, thin film 34 R207, R208, R301, R307, R308, R310, R312, R315, R319, R320, R321, R328, R329, R330, R332, R334, R335, R337, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R416 R304 Resistor 15k Various 1206 Chip, thin film 1 R306 Resistor 18k Various 1206 Chip, thin film 1 R309, R316 Resistor 20k Various 1206 Chip, thin film 2 R311, R326, R327 Resistor 30k Various 1206 Chip, thin film 3 R413 Resistor 39k Various 1206 Chip, thin film 1 R302, R317 Resistor 100k Various 1206 Chip, thin film 2 R412 Resistor 150k Various 1206 Chip, thin film 1 R103, R104, R105, R106, Resistor 1M Various 1206 Chip, thin film 5 R333 R314 Resistor 4M7 Various 1206 Chip, thin film 1 RV301 Trimpot 20k 3362F-1-203LF Bournes Top adjust 1

C302, C309 Capacitor 100pF Various 1206 Ceramic 2 C310, C401 Capacitor 1nF Various 1206 Ceramic 2 C304 Capacitor 1n5 Various 1206 NPO/COG 1 C303 Capacitor 3n3 Various 1206 NPO/COG 1 C308, C406 Capacitor 10nF Various 1206 Ceramic 2 C306 Capacitor 47nF Various 1206 NPO/COG 1 C301, C305, C307 Capacitor 100nF Various 1206 NPO/COG 3 C101, C102, C103, C104, Capacitor 100nF Various 1206 Ceramic 30 C105, C106, C107, C108, C109, C111, C112, C113, C114, C116, C201, C202, C203, C311, C312, C313, C314, C315, C316, C317, C318, C319, C320, C321, C404, C503

C502 Capacitor 470nF Various 1206 Ceramic 1 C110, C115, C206, C207, Capacitor 1uF / 16V Various 1206 Tantalum 5 C208 C402, C403, C405, C508, Capacitor 10uF / 16V EEE-1CA100SR Panasonic SMT Electrolytic 5 C509 C506, C507 Capacitor 47uF / 16V EEE-1CA470WR Panasonic SMT Electrolytic 2 C407, C504, C505 Capacitor 470uF / 16V EEE-1CA471UP Panasonic SMT Electrolytic 3 C501 Capacitor 4700uF / 25V Various Through hole. Pitch = Electrolytic 1 7.5mm. Diameter = 16mm.

U103 I.C. 74HCT04 Various SOIC Hex inverter 1 U305 I.C. 74HC30 Various SOIC 8-input NAND gate 1 U306 I.C. 74HC32 Various SOIC Quad 2-input OR 1 U304 I.C. 74HC132 Various SOIC Quad 2-input NAND S/T 1 U308 I.C. 74HC175 Various SOIC Quad D-type flip-flop 1 U109, U307 I.C. 74HC244 Various SOIC - WIDE Octal buffer / driver 2 U102, U105 I.C. 74HCT32 Various SOIC Quad 2-input OR 2 U107, U108 I.C. 74HCT244 Various SOIC - WIDE Octal buffer / driver 2 U106 I.C. 74HCT245 Various SOIC - WIDE Octal bus transceiver 1 U202 I.C. AS6C1008 Alliance Memory SOP 128k x 8 SRAM 1 U201, U203 I.C. AT27C256 Atmel DIP 32k x 8 OTP ROM 2 U104 I.C. Z84C0006PEG Zilog DIP Microprocessor 1 U401 I.C. LM386 Texas Instruments DIP Audio power amplifier 1 REG501 I.C. LM7805MP Texas Instruments SOT-223 +5V fixed regulator 1 U301, U302 I.C. TL074 Various SOIC Quad JFET-input opamp 2 U101 I.C. TLC556 Texas Instruments SOIC Dual timer 1 U303 I.C. TS391SN2T1G On Semiconductor TSOP-5 Comparator 1

B501, B502 Bridge rectifier W04 Various TH 2 D305 TVS diode SMAJ30CA Various DO214AC 1 D303 Single diode BAT54 Various SOT-23 1 D301, D302, D501, D502 Dual diode BAT54S Various SOT-23 4 D101, D304 Diode LL4148 Various SOD-80 2 D201 Zener diode BZX84C3V6 Various SOT-23 1 D401 Zener diode BZX84C6V8 Various SOT-23 1 Q201, Q301, Q303, Q304, Transistor BC850C Various SOT-23 NPN 9 Q305, Q401, Q402, Q403, Q404 Q302, Q501 Transistor BC860C Various SOT-23 PNP 2 Q405, Q503 Transistor FZT1049A Diodes Inc. SOT-223 NPN 2 Q504 Transistor FZT1149A Diodes Inc. SOT-223 PNP 1 Q502 Transistor MJ2955 Various TO-3 PNP 1

P501 Connector 640445-4 TE Connectivity TH 3.96mm-pitch header, 4-way 1 P101, P205, P302, P303, Connector 0022272021 Molex TH KK-254 vertical header, 2-way 6 P502, P503 P201, P202, P304, P401, Connector 0022272041 Molex TH KK-254 vertical header, 4-way 6 P402, P403 P301 Connector 0022272061 Molex TH KK-254 vertical header, 6-way 1 P204 Connector Various TH 34-way IDC boxed header 1 P102, P203 Connector Various TH 50-way IDC boxed header 2

F501 Fuse holder 64600001003 Littlefuse TH 5x20mm PCB mount 1 Cover 64800001009 Littlefuse For fuse holder F501 1 RLY301 Relay DS1E-S-DC5V Panasonic TH 5VDC coil, SPDT 1 Heatsink 506007B00000G Aavid Board Level Heatsink for TO-3 1

Q502 mounted with M3 hardware. Machined-pin sockets recommended for all DIP integrated circuits.

Parts for Video Generator PCB

Designator Component type Value Part # Manufacturer Package Description Quantity

R6 Resistor 68R Various 1206 Chip, thin film 1 R4 Resistor 220R Various 1206 Chip, thin film 1 R3 Resistor 1k Various 1206 Chip, thin film 1 R1 Resistor 2k2 Various 1206 Chip, thin film 1 R14, R15 Resistor 3k3 Various 1206 Chip, thin film 2 R2 Resistor 5k1 Various 1206 Chip, thin film 1 R5, R7, R8, R9, R10, R11, Resistor 10k Various 1206 Chip, thin film 7 R12 R13 Resistor 47k Various 1206 Chip, thin film 1 RV4 Trimpot 5k 3362F-1-502LF Bournes Cermet, top adjust 1 RV2 Trimpot 50k 3362F-1-503LF Bournes Cermet, top adjust 1 RV3 Potentiometer 5k linear 296XD CTS PCB mount, right angle 1 RV1 Potentiometer 100k linear 296XD CTS PCB mount, right angle 1

C32, C33 Capacitor 1nF Various 1206 NPO/COG 2 C31 Capacitor 10nF Various 1206 NPO/COG 1 C30 Capacitor 100nF Various 1206 NPO/COG 1 C1, C2, C3, C5, C5, C6, C7, Capacitor 100nF Various 1206 Ceramic 25 C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25 C26, C27 Capacitor 1uF / 16V Various 1206 Tantalum 2 C28 Capacitor 47uF / 16V EEE-1CA470WR Panasonic SMT Electrolytic 1 C29 Capacitor 470uF / 16V EEE-1CA471UP Panasonic SMT Electrolytic 1

U5 I.C. 74HC00 Various SOIC Quad NAND gate 1 U17 I.C. 74HCT00 Various SOIC Quad NAND gate 1 U6, U8, U11 I.C. 74HC08 Various SOIC Quad AND gate 3 U2, U22, U23 I.C. 74HC74 Various SOIC Dual D flip-flop 3 U3, U12, U13, U14 I.C. 74HC157 Various SOIC Data selector / multiplexer 4 U4 I.C. 74HC161 Various SOIC 4-bit synchronous counter 1 U7, U9, U10 I.C. 74HC393 Various SOIC Dual counter 3 U24, U25 I.C. 74HC4538 Various SOIC Dual monostable 2 U16 I.C. 74HCT02 Various SOIC Quad 2-input NOR 1 U21 I.C. 74HCT165 Various SOIC Shift register 1 U19 I.C. 74HC244 Various SOIC - WIDE Octal buffer / driver 1 U18 I.C. 74HCT244 Various SOIC - WIDE Octal buffer / driver 1 U15 I.C. AS7C256 Alliance Memory SOJ 32k x 8 SRAM 1 U20 I.C. AT27C256 Atmel DIP 32k x 8 OTP ROM 1 U1 I.C. MX045-3C-16M0000 CTS Elec. Comp. DIP 16 MHz oscillator, 14 pin DIP 1

Q1 Transistor BC860C Various SOT-23 PNP 1

P1, P2 Connector 0022272021 Molex TH KK-254 vertical header, 2-way 2 P3 Connector Various TH 50-way IDC boxed header 1 JP1_A Jumper SPC02SYAN Sullins 0.1" pitch 1 JP1_B 3 pin header Various TH Single row 0.1" pitch male pins 1

Machined-pin socket recommended for U20.

Parts for Keyboard Interface PCB

Designator Component type Value Part # Manufacturer Package Description Quantity

R4 Resistor 1k Various 1206 Chip, thin film 1 R1, R2, R3 Resistor 4k7 Various 1206 Chip, thin film 3 R5, R6, R7 Resistor 10k Various 1206 Chip, thin film 3

C3, C4, C5, C6, C7, C8 Capacitor 100nF Various 1206 Ceramic 6 C1 Capacitor 47uF / 16V EEE-1CA470WR Panasonic SMT Electrolytic 1 C2 Capacitor 10uF / 25V T491C106K025AT Kemet 2312 Tantalum ESR 1.5 ohms 1

U1 I.C. PIC16F876A Microchip SOIC - WIDE Microcontroller 1 U2 I.C. EPM7064AETC44 Intel TQFP-44 CPLD 1 U3 I.C. MXO45HS-3C CTS Elec. Comp. DIP 10 MHz oscillator, 8 pin DIP 1 REG1 I.C. TC1262-3V3 Microchip SOT-223 3.3V regulator 1

P4 Connector Various TH 34-way IDC boxed header 1 P1 Connector 0022272041 Molex TH KK-254 vertical header, 4-way 1 P2 4 pin header Various TH Single row 0.1" pitch male pins 1 P3 8 pin header Various TH Double row 0.1" pitch male pins 1